1 /***************************************************************************
2 * Copyright (C) 2015 by Uwe Bonnes *
3 * bon@elektron.ikp.physik.tu-darmstadt.de *
5 * Copyright (C) 2019 by Tarek Bochkati for STMicroelectronics *
6 * tarek.bouchkati@gmail.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
20 ***************************************************************************/
27 #include <helper/align.h>
28 #include <helper/binarybuffer.h>
29 #include <target/algorithm.h>
30 #include <target/cortex_m.h>
34 /* STM32L4xxx series for reference.
36 * RM0351 (STM32L4x5/STM32L4x6)
37 * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
39 * RM0394 (STM32L43x/44x/45x/46x)
40 * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
42 * RM0432 (STM32L4R/4Sxx)
43 * http://www.st.com/resource/en/reference_manual/dm00310109.pdf
45 * STM32L476RG Datasheet (for erase timing)
46 * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
48 * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
49 * an option byte is available to map all sectors to the first bank.
50 * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
53 * RM0394 devices have a single bank only.
55 * RM0432 devices have single and dual bank operating modes.
56 * - for STM32L4R/Sxx the FLASH size is 2Mbyte or 1Mbyte.
57 * - for STM32L4P/Q5x the FLASH size is 1Mbyte or 512Kbyte.
58 * Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
60 * Bank mode is controlled by two different bits in option bytes register.
62 * In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
63 * In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
65 * In 1M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
66 * In 512K FLASH devices bit 21 (DB512K) controls Dual Bank mode.
70 /* STM32WBxxx series for reference.
73 * http://www.st.com/resource/en/reference_manual/dm00318631.pdf
76 * http://www.st.com/resource/en/reference_manual/dm00622834.pdf
79 /* STM32WLxxx series for reference.
82 * http://www.st.com/resource/en/reference_manual/dm00530369.pdf
85 * http://www.st.com/resource/en/reference_manual/dm00451556.pdf
88 /* STM32G0xxx series for reference.
91 * http://www.st.com/resource/en/reference_manual/dm00371828.pdf
94 * http://www.st.com/resource/en/reference_manual/dm00463896.pdf
97 /* STM32G4xxx series for reference.
99 * RM0440 (STM32G43x/44x/47x/48x/49x/4Ax)
100 * http://www.st.com/resource/en/reference_manual/dm00355726.pdf
102 * Cat. 2 devices have single bank only, page size is 2kByte.
104 * Cat. 3 devices have single and dual bank operating modes,
105 * Page size is 2kByte (dual mode) or 4kByte (single mode).
107 * Bank mode is controlled by bit 22 (DBANK) in option bytes register.
108 * Both banks are treated as a single OpenOCD bank.
110 * Cat. 4 devices have single bank only, page size is 2kByte.
113 /* STM32L5xxx series for reference.
115 * RM0428 (STM32L552xx/STM32L562xx)
116 * http://www.st.com/resource/en/reference_manual/dm00346336.pdf
119 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
121 #define FLASH_ERASE_TIMEOUT 250
122 #define FLASH_WRITE_TIMEOUT 50
125 /* relevant STM32L4 flags ****************************************************/
127 /* this flag indicates if the device flash is with dual bank architecture */
128 #define F_HAS_DUAL_BANK BIT(0)
129 /* this flags is used for dual bank devices only, it indicates if the
130 * 4 WRPxx are usable if the device is configured in single-bank mode */
131 #define F_USE_ALL_WRPXX BIT(1)
132 /* this flag indicates if the device embeds a TrustZone security feature */
133 #define F_HAS_TZ BIT(2)
134 /* this flag indicates if the device has the same flash registers as STM32L5 */
135 #define F_HAS_L5_FLASH_REGS BIT(3)
136 /* this flag indicates that programming should be done in quad-word
137 * the default programming word size is double-word */
138 #define F_QUAD_WORD_PROG BIT(4)
139 /* end of STM32L4 flags ******************************************************/
142 enum stm32l4_flash_reg_index
{
143 STM32_FLASH_ACR_INDEX
,
144 STM32_FLASH_KEYR_INDEX
,
145 STM32_FLASH_OPTKEYR_INDEX
,
146 STM32_FLASH_SR_INDEX
,
147 STM32_FLASH_CR_INDEX
,
148 /* for some devices like STM32WL5x, the CPU2 have a dedicated C2CR register w/o LOCKs,
149 * so it uses the C2CR for flash operations and CR for checking locks and locking */
150 STM32_FLASH_CR_WLK_INDEX
, /* FLASH_CR_WITH_LOCK */
151 STM32_FLASH_OPTR_INDEX
,
152 STM32_FLASH_WRP1AR_INDEX
,
153 STM32_FLASH_WRP1BR_INDEX
,
154 STM32_FLASH_WRP2AR_INDEX
,
155 STM32_FLASH_WRP2BR_INDEX
,
156 STM32_FLASH_REG_INDEX_NUM
,
161 RDP_LEVEL_0_5
= 0x55, /* for devices with TrustZone enabled */
166 static const uint32_t stm32l4_flash_regs
[STM32_FLASH_REG_INDEX_NUM
] = {
167 [STM32_FLASH_ACR_INDEX
] = 0x000,
168 [STM32_FLASH_KEYR_INDEX
] = 0x008,
169 [STM32_FLASH_OPTKEYR_INDEX
] = 0x00C,
170 [STM32_FLASH_SR_INDEX
] = 0x010,
171 [STM32_FLASH_CR_INDEX
] = 0x014,
172 [STM32_FLASH_OPTR_INDEX
] = 0x020,
173 [STM32_FLASH_WRP1AR_INDEX
] = 0x02C,
174 [STM32_FLASH_WRP1BR_INDEX
] = 0x030,
175 [STM32_FLASH_WRP2AR_INDEX
] = 0x04C,
176 [STM32_FLASH_WRP2BR_INDEX
] = 0x050,
179 static const uint32_t stm32wl_cpu2_flash_regs
[STM32_FLASH_REG_INDEX_NUM
] = {
180 [STM32_FLASH_ACR_INDEX
] = 0x000,
181 [STM32_FLASH_KEYR_INDEX
] = 0x008,
182 [STM32_FLASH_OPTKEYR_INDEX
] = 0x010,
183 [STM32_FLASH_SR_INDEX
] = 0x060,
184 [STM32_FLASH_CR_INDEX
] = 0x064,
185 [STM32_FLASH_CR_WLK_INDEX
] = 0x014,
186 [STM32_FLASH_OPTR_INDEX
] = 0x020,
187 [STM32_FLASH_WRP1AR_INDEX
] = 0x02C,
188 [STM32_FLASH_WRP1BR_INDEX
] = 0x030,
191 static const uint32_t stm32l5_ns_flash_regs
[STM32_FLASH_REG_INDEX_NUM
] = {
192 [STM32_FLASH_ACR_INDEX
] = 0x000,
193 [STM32_FLASH_KEYR_INDEX
] = 0x008, /* NSKEYR */
194 [STM32_FLASH_OPTKEYR_INDEX
] = 0x010,
195 [STM32_FLASH_SR_INDEX
] = 0x020, /* NSSR */
196 [STM32_FLASH_CR_INDEX
] = 0x028, /* NSCR */
197 [STM32_FLASH_OPTR_INDEX
] = 0x040,
198 [STM32_FLASH_WRP1AR_INDEX
] = 0x058,
199 [STM32_FLASH_WRP1BR_INDEX
] = 0x05C,
200 [STM32_FLASH_WRP2AR_INDEX
] = 0x068,
201 [STM32_FLASH_WRP2BR_INDEX
] = 0x06C,
204 static const uint32_t stm32l5_s_flash_regs
[STM32_FLASH_REG_INDEX_NUM
] = {
205 [STM32_FLASH_ACR_INDEX
] = 0x000,
206 [STM32_FLASH_KEYR_INDEX
] = 0x00C, /* SECKEYR */
207 [STM32_FLASH_OPTKEYR_INDEX
] = 0x010,
208 [STM32_FLASH_SR_INDEX
] = 0x024, /* SECSR */
209 [STM32_FLASH_CR_INDEX
] = 0x02C, /* SECCR */
210 [STM32_FLASH_OPTR_INDEX
] = 0x040,
211 [STM32_FLASH_WRP1AR_INDEX
] = 0x058,
212 [STM32_FLASH_WRP1BR_INDEX
] = 0x05C,
213 [STM32_FLASH_WRP2AR_INDEX
] = 0x068,
214 [STM32_FLASH_WRP2BR_INDEX
] = 0x06C,
222 struct stm32l4_part_info
{
224 const char *device_str
;
225 const struct stm32l4_rev
*revs
;
226 const size_t num_revs
;
227 const uint16_t max_flash_size_kb
;
228 const uint32_t flags
; /* one bit per feature, see STM32L4 flags: macros F_XXX */
229 const uint32_t flash_regs_base
;
230 const uint32_t fsize_addr
;
231 const uint32_t otp_base
;
232 const uint32_t otp_size
;
235 struct stm32l4_flash_bank
{
238 unsigned int bank1_sectors
;
241 uint32_t user_bank_size
;
243 uint32_t cr_bker_mask
;
244 uint32_t sr_bsy_mask
;
245 uint32_t wrpxxr_mask
;
246 const struct stm32l4_part_info
*part_info
;
247 uint32_t flash_regs_base
;
248 const uint32_t *flash_regs
;
250 bool use_flashloader
;
251 enum stm32l4_rdp rdp
;
263 enum stm32l4_flash_reg_index reg_idx
;
271 /* human readable list of families this drivers supports (sorted alphabetically) */
272 static const char *device_families
= "STM32G0/G4/L4/L4+/L5/U5/WB/WL";
274 static const struct stm32l4_rev stm32_415_revs
[] = {
275 { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
278 static const struct stm32l4_rev stm32_435_revs
[] = {
279 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
282 static const struct stm32l4_rev stm32_456_revs
[] = {
286 static const struct stm32l4_rev stm32_460_revs
[] = {
287 { 0x1000, "A/Z" } /* A and Z, no typo in RM! */, { 0x2000, "B" },
290 static const struct stm32l4_rev stm32_461_revs
[] = {
291 { 0x1000, "A" }, { 0x2000, "B" },
294 static const struct stm32l4_rev stm32_462_revs
[] = {
295 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
298 static const struct stm32l4_rev stm32_464_revs
[] = {
299 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
302 static const struct stm32l4_rev stm32_466_revs
[] = {
303 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2000, "B" },
306 static const struct stm32l4_rev stm32_467_revs
[] = {
310 static const struct stm32l4_rev stm32_468_revs
[] = {
311 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
314 static const struct stm32l4_rev stm32_469_revs
[] = {
315 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
318 static const struct stm32l4_rev stm32_470_revs
[] = {
319 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" },
322 static const struct stm32l4_rev stm32_471_revs
[] = {
326 static const struct stm32l4_rev stm32_472_revs
[] = {
327 { 0x1000, "A" }, { 0x2000, "B" },
330 static const struct stm32l4_rev stm32_479_revs
[] = {
334 static const struct stm32l4_rev stm32_482_revs
[] = {
335 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x2000, "B" },
338 static const struct stm32l4_rev stm32_495_revs
[] = {
342 static const struct stm32l4_rev stm32_496_revs
[] = {
346 static const struct stm32l4_rev stm32_497_revs
[] = {
350 static const struct stm32l4_part_info stm32l4_parts
[] = {
353 .revs
= stm32_415_revs
,
354 .num_revs
= ARRAY_SIZE(stm32_415_revs
),
355 .device_str
= "STM32L47/L48xx",
356 .max_flash_size_kb
= 1024,
357 .flags
= F_HAS_DUAL_BANK
,
358 .flash_regs_base
= 0x40022000,
359 .fsize_addr
= 0x1FFF75E0,
360 .otp_base
= 0x1FFF7000,
365 .revs
= stm32_435_revs
,
366 .num_revs
= ARRAY_SIZE(stm32_435_revs
),
367 .device_str
= "STM32L43/L44xx",
368 .max_flash_size_kb
= 256,
370 .flash_regs_base
= 0x40022000,
371 .fsize_addr
= 0x1FFF75E0,
372 .otp_base
= 0x1FFF7000,
377 .revs
= stm32_456_revs
,
378 .num_revs
= ARRAY_SIZE(stm32_456_revs
),
379 .device_str
= "STM32G05/G06xx",
380 .max_flash_size_kb
= 64,
382 .flash_regs_base
= 0x40022000,
383 .fsize_addr
= 0x1FFF75E0,
384 .otp_base
= 0x1FFF7000,
389 .revs
= stm32_460_revs
,
390 .num_revs
= ARRAY_SIZE(stm32_460_revs
),
391 .device_str
= "STM32G07/G08xx",
392 .max_flash_size_kb
= 128,
394 .flash_regs_base
= 0x40022000,
395 .fsize_addr
= 0x1FFF75E0,
396 .otp_base
= 0x1FFF7000,
401 .revs
= stm32_461_revs
,
402 .num_revs
= ARRAY_SIZE(stm32_461_revs
),
403 .device_str
= "STM32L49/L4Axx",
404 .max_flash_size_kb
= 1024,
405 .flags
= F_HAS_DUAL_BANK
,
406 .flash_regs_base
= 0x40022000,
407 .fsize_addr
= 0x1FFF75E0,
408 .otp_base
= 0x1FFF7000,
413 .revs
= stm32_462_revs
,
414 .num_revs
= ARRAY_SIZE(stm32_462_revs
),
415 .device_str
= "STM32L45/L46xx",
416 .max_flash_size_kb
= 512,
418 .flash_regs_base
= 0x40022000,
419 .fsize_addr
= 0x1FFF75E0,
420 .otp_base
= 0x1FFF7000,
425 .revs
= stm32_464_revs
,
426 .num_revs
= ARRAY_SIZE(stm32_464_revs
),
427 .device_str
= "STM32L41/L42xx",
428 .max_flash_size_kb
= 128,
430 .flash_regs_base
= 0x40022000,
431 .fsize_addr
= 0x1FFF75E0,
432 .otp_base
= 0x1FFF7000,
437 .revs
= stm32_466_revs
,
438 .num_revs
= ARRAY_SIZE(stm32_466_revs
),
439 .device_str
= "STM32G03/G04xx",
440 .max_flash_size_kb
= 64,
442 .flash_regs_base
= 0x40022000,
443 .fsize_addr
= 0x1FFF75E0,
444 .otp_base
= 0x1FFF7000,
449 .revs
= stm32_467_revs
,
450 .num_revs
= ARRAY_SIZE(stm32_467_revs
),
451 .device_str
= "STM32G0Bx/G0Cx",
452 .max_flash_size_kb
= 512,
453 .flags
= F_HAS_DUAL_BANK
,
454 .flash_regs_base
= 0x40022000,
455 .fsize_addr
= 0x1FFF75E0,
456 .otp_base
= 0x1FFF7000,
461 .revs
= stm32_468_revs
,
462 .num_revs
= ARRAY_SIZE(stm32_468_revs
),
463 .device_str
= "STM32G43/G44xx",
464 .max_flash_size_kb
= 128,
466 .flash_regs_base
= 0x40022000,
467 .fsize_addr
= 0x1FFF75E0,
468 .otp_base
= 0x1FFF7000,
473 .revs
= stm32_469_revs
,
474 .num_revs
= ARRAY_SIZE(stm32_469_revs
),
475 .device_str
= "STM32G47/G48xx",
476 .max_flash_size_kb
= 512,
477 .flags
= F_HAS_DUAL_BANK
| F_USE_ALL_WRPXX
,
478 .flash_regs_base
= 0x40022000,
479 .fsize_addr
= 0x1FFF75E0,
480 .otp_base
= 0x1FFF7000,
485 .revs
= stm32_470_revs
,
486 .num_revs
= ARRAY_SIZE(stm32_470_revs
),
487 .device_str
= "STM32L4R/L4Sxx",
488 .max_flash_size_kb
= 2048,
489 .flags
= F_HAS_DUAL_BANK
| F_USE_ALL_WRPXX
,
490 .flash_regs_base
= 0x40022000,
491 .fsize_addr
= 0x1FFF75E0,
492 .otp_base
= 0x1FFF7000,
497 .revs
= stm32_471_revs
,
498 .num_revs
= ARRAY_SIZE(stm32_471_revs
),
499 .device_str
= "STM32L4P5/L4Q5x",
500 .max_flash_size_kb
= 1024,
501 .flags
= F_HAS_DUAL_BANK
| F_USE_ALL_WRPXX
,
502 .flash_regs_base
= 0x40022000,
503 .fsize_addr
= 0x1FFF75E0,
504 .otp_base
= 0x1FFF7000,
509 .revs
= stm32_472_revs
,
510 .num_revs
= ARRAY_SIZE(stm32_472_revs
),
511 .device_str
= "STM32L55/L56xx",
512 .max_flash_size_kb
= 512,
513 .flags
= F_HAS_DUAL_BANK
| F_USE_ALL_WRPXX
| F_HAS_TZ
| F_HAS_L5_FLASH_REGS
,
514 .flash_regs_base
= 0x40022000,
515 .fsize_addr
= 0x0BFA05E0,
516 .otp_base
= 0x0BFA0000,
521 .revs
= stm32_479_revs
,
522 .num_revs
= ARRAY_SIZE(stm32_479_revs
),
523 .device_str
= "STM32G49/G4Axx",
524 .max_flash_size_kb
= 512,
526 .flash_regs_base
= 0x40022000,
527 .fsize_addr
= 0x1FFF75E0,
528 .otp_base
= 0x1FFF7000,
533 .revs
= stm32_482_revs
,
534 .num_revs
= ARRAY_SIZE(stm32_482_revs
),
535 .device_str
= "STM32U57/U58xx",
536 .max_flash_size_kb
= 2048,
537 .flags
= F_HAS_DUAL_BANK
| F_QUAD_WORD_PROG
| F_HAS_TZ
| F_HAS_L5_FLASH_REGS
,
538 .flash_regs_base
= 0x40022000,
539 .fsize_addr
= 0x0BFA07A0,
540 .otp_base
= 0x0BFA0000,
545 .revs
= stm32_495_revs
,
546 .num_revs
= ARRAY_SIZE(stm32_495_revs
),
547 .device_str
= "STM32WB5x",
548 .max_flash_size_kb
= 1024,
550 .flash_regs_base
= 0x58004000,
551 .fsize_addr
= 0x1FFF75E0,
552 .otp_base
= 0x1FFF7000,
557 .revs
= stm32_496_revs
,
558 .num_revs
= ARRAY_SIZE(stm32_496_revs
),
559 .device_str
= "STM32WB3x",
560 .max_flash_size_kb
= 512,
562 .flash_regs_base
= 0x58004000,
563 .fsize_addr
= 0x1FFF75E0,
564 .otp_base
= 0x1FFF7000,
569 .revs
= stm32_497_revs
,
570 .num_revs
= ARRAY_SIZE(stm32_497_revs
),
571 .device_str
= "STM32WLEx/WL5x",
572 .max_flash_size_kb
= 256,
574 .flash_regs_base
= 0x58004000,
575 .fsize_addr
= 0x1FFF75E0,
576 .otp_base
= 0x1FFF7000,
581 /* flash bank stm32l4x <base> <size> 0 0 <target#> */
582 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command
)
584 struct stm32l4_flash_bank
*stm32l4_info
;
587 return ERROR_COMMAND_SYNTAX_ERROR
;
589 /* fix-up bank base address: 0 is used for normal flash memory */
591 bank
->base
= STM32_FLASH_BANK_BASE
;
593 stm32l4_info
= calloc(1, sizeof(struct stm32l4_flash_bank
));
595 return ERROR_FAIL
; /* Checkme: What better error to use?*/
596 bank
->driver_priv
= stm32l4_info
;
598 stm32l4_info
->probed
= false;
599 stm32l4_info
->otp_enabled
= false;
600 stm32l4_info
->user_bank_size
= bank
->size
;
601 stm32l4_info
->use_flashloader
= true;
606 /* bitmap helper extension */
612 static void bitmap_to_ranges(unsigned long *bitmap
, unsigned int nbits
,
613 struct range
*ranges
, unsigned int *ranges_count
) {
615 bool last_bit
= 0, cur_bit
;
616 for (unsigned int i
= 0; i
< nbits
; i
++) {
617 cur_bit
= test_bit(i
, bitmap
);
619 if (cur_bit
&& !last_bit
) {
621 ranges
[*ranges_count
- 1].start
= i
;
622 ranges
[*ranges_count
- 1].end
= i
;
623 } else if (cur_bit
&& last_bit
) {
624 /* update (increment) the end this range */
625 ranges
[*ranges_count
- 1].end
= i
;
632 static inline int range_print_one(struct range
*range
, char *str
)
634 if (range
->start
== range
->end
)
635 return sprintf(str
, "[%d]", range
->start
);
637 return sprintf(str
, "[%d,%d]", range
->start
, range
->end
);
640 static char *range_print_alloc(struct range
*ranges
, unsigned int ranges_count
)
642 /* each range will be printed like the following: [start,end]
643 * start and end, both are unsigned int, an unsigned int takes 10 characters max
644 * plus 3 characters for '[', ',' and ']'
645 * thus means each range can take maximum 23 character
646 * after each range we add a ' ' as separator and finally we need the '\0'
647 * if the ranges_count is zero we reserve one char for '\0' to return an empty string */
648 char *str
= calloc(1, ranges_count
* (24 * sizeof(char)) + 1);
651 for (unsigned int i
= 0; i
< ranges_count
; i
++) {
652 ptr
+= range_print_one(&(ranges
[i
]), ptr
);
654 if (i
< ranges_count
- 1)
661 /* end of bitmap helper extension */
663 static inline bool stm32l4_is_otp(struct flash_bank
*bank
)
665 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
666 return bank
->base
== stm32l4_info
->part_info
->otp_base
;
669 static int stm32l4_otp_enable(struct flash_bank
*bank
, bool enable
)
671 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
673 if (!stm32l4_is_otp(bank
))
676 char *op_str
= enable
? "enabled" : "disabled";
678 LOG_INFO("OTP memory (bank #%d) is %s%s for write commands",
680 stm32l4_info
->otp_enabled
== enable
? "already " : "",
683 stm32l4_info
->otp_enabled
= enable
;
688 static inline bool stm32l4_otp_is_enabled(struct flash_bank
*bank
)
690 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
691 return stm32l4_info
->otp_enabled
;
694 static void stm32l4_sync_rdp_tzen(struct flash_bank
*bank
)
696 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
700 if (stm32l4_info
->part_info
->flags
& F_HAS_TZ
)
701 tzen
= (stm32l4_info
->optr
& FLASH_TZEN
) != 0;
703 uint32_t rdp
= stm32l4_info
->optr
& FLASH_RDP_MASK
;
705 /* for devices without TrustZone:
706 * RDP level 0 and 2 values are to 0xAA and 0xCC
707 * Any other value corresponds to RDP level 1
708 * for devices with TrusZone:
709 * RDP level 0 and 2 values are 0xAA and 0xCC
710 * RDP level 0.5 value is 0x55 only if TZEN = 1
711 * Any other value corresponds to RDP level 1, including 0x55 if TZEN = 0
714 if (rdp
!= RDP_LEVEL_0
&& rdp
!= RDP_LEVEL_2
) {
715 if (!tzen
|| (tzen
&& rdp
!= RDP_LEVEL_0_5
))
719 stm32l4_info
->tzen
= tzen
;
720 stm32l4_info
->rdp
= rdp
;
723 static inline uint32_t stm32l4_get_flash_reg(struct flash_bank
*bank
, uint32_t reg_offset
)
725 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
726 return stm32l4_info
->flash_regs_base
+ reg_offset
;
729 static inline uint32_t stm32l4_get_flash_reg_by_index(struct flash_bank
*bank
,
730 enum stm32l4_flash_reg_index reg_index
)
732 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
733 return stm32l4_get_flash_reg(bank
, stm32l4_info
->flash_regs
[reg_index
]);
736 static inline int stm32l4_read_flash_reg(struct flash_bank
*bank
, uint32_t reg_offset
, uint32_t *value
)
738 return target_read_u32(bank
->target
, stm32l4_get_flash_reg(bank
, reg_offset
), value
);
741 static inline int stm32l4_read_flash_reg_by_index(struct flash_bank
*bank
,
742 enum stm32l4_flash_reg_index reg_index
, uint32_t *value
)
744 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
745 return stm32l4_read_flash_reg(bank
, stm32l4_info
->flash_regs
[reg_index
], value
);
748 static inline int stm32l4_write_flash_reg(struct flash_bank
*bank
, uint32_t reg_offset
, uint32_t value
)
750 return target_write_u32(bank
->target
, stm32l4_get_flash_reg(bank
, reg_offset
), value
);
753 static inline int stm32l4_write_flash_reg_by_index(struct flash_bank
*bank
,
754 enum stm32l4_flash_reg_index reg_index
, uint32_t value
)
756 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
757 return stm32l4_write_flash_reg(bank
, stm32l4_info
->flash_regs
[reg_index
], value
);
760 static int stm32l4_wait_status_busy(struct flash_bank
*bank
, int timeout
)
762 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
764 int retval
= ERROR_OK
;
766 /* wait for busy to clear */
768 retval
= stm32l4_read_flash_reg_by_index(bank
, STM32_FLASH_SR_INDEX
, &status
);
769 if (retval
!= ERROR_OK
)
771 LOG_DEBUG("status: 0x%" PRIx32
"", status
);
772 if ((status
& stm32l4_info
->sr_bsy_mask
) == 0)
774 if (timeout
-- <= 0) {
775 LOG_ERROR("timed out waiting for flash");
781 if (status
& FLASH_WRPERR
) {
782 LOG_ERROR("stm32x device protected");
786 /* Clear but report errors */
787 if (status
& FLASH_ERROR
) {
788 if (retval
== ERROR_OK
)
790 /* If this operation fails, we ignore it and report the original
793 stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_SR_INDEX
, status
& FLASH_ERROR
);
799 /** set all FLASH_SECBB registers to the same value */
800 static int stm32l4_set_secbb(struct flash_bank
*bank
, uint32_t value
)
802 /* This function should be used only with device with TrustZone, do just a security check */
803 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
804 assert(stm32l4_info
->part_info
->flags
& F_HAS_TZ
);
806 /* based on RM0438 Rev6 for STM32L5x devices:
807 * to modify a page block-based security attribution, it is recommended to
808 * 1- check that no flash operation is ongoing on the related page
809 * 2- add ISB instruction after modifying the page security attribute in SECBBxRy
810 * this step is not need in case of JTAG direct access
812 int retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
813 if (retval
!= ERROR_OK
)
816 /* write SECBBxRy registers */
817 LOG_DEBUG("setting secure block-based areas registers (SECBBxRy) to 0x%08x", value
);
819 const uint8_t secbb_regs
[] = {
820 FLASH_SECBB1(1), FLASH_SECBB1(2), FLASH_SECBB1(3), FLASH_SECBB1(4), /* bank 1 SECBB register offsets */
821 FLASH_SECBB2(1), FLASH_SECBB2(2), FLASH_SECBB2(3), FLASH_SECBB2(4) /* bank 2 SECBB register offsets */
825 unsigned int num_secbb_regs
= ARRAY_SIZE(secbb_regs
);
827 /* in single bank mode, it's useless to modify FLASH_SECBB2Rx registers
828 * then consider only the first half of secbb_regs
830 if (!stm32l4_info
->dual_bank_mode
)
833 for (unsigned int i
= 0; i
< num_secbb_regs
; i
++) {
834 retval
= stm32l4_write_flash_reg(bank
, secbb_regs
[i
], value
);
835 if (retval
!= ERROR_OK
)
842 static inline int stm32l4_get_flash_cr_with_lock_index(struct flash_bank
*bank
)
844 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
845 return (stm32l4_info
->flash_regs
[STM32_FLASH_CR_WLK_INDEX
]) ?
846 STM32_FLASH_CR_WLK_INDEX
: STM32_FLASH_CR_INDEX
;
849 static int stm32l4_unlock_reg(struct flash_bank
*bank
)
851 const uint32_t flash_cr_index
= stm32l4_get_flash_cr_with_lock_index(bank
);
854 /* first check if not already unlocked
855 * otherwise writing on STM32_FLASH_KEYR will fail
857 int retval
= stm32l4_read_flash_reg_by_index(bank
, flash_cr_index
, &ctrl
);
858 if (retval
!= ERROR_OK
)
861 if ((ctrl
& FLASH_LOCK
) == 0)
864 /* unlock flash registers */
865 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_KEYR_INDEX
, KEY1
);
866 if (retval
!= ERROR_OK
)
869 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_KEYR_INDEX
, KEY2
);
870 if (retval
!= ERROR_OK
)
873 retval
= stm32l4_read_flash_reg_by_index(bank
, flash_cr_index
, &ctrl
);
874 if (retval
!= ERROR_OK
)
877 if (ctrl
& FLASH_LOCK
) {
878 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32
, ctrl
);
879 return ERROR_TARGET_FAILURE
;
885 static int stm32l4_unlock_option_reg(struct flash_bank
*bank
)
887 const uint32_t flash_cr_index
= stm32l4_get_flash_cr_with_lock_index(bank
);
890 int retval
= stm32l4_read_flash_reg_by_index(bank
, flash_cr_index
, &ctrl
);
891 if (retval
!= ERROR_OK
)
894 if ((ctrl
& FLASH_OPTLOCK
) == 0)
897 /* unlock option registers */
898 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_OPTKEYR_INDEX
, OPTKEY1
);
899 if (retval
!= ERROR_OK
)
902 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_OPTKEYR_INDEX
, OPTKEY2
);
903 if (retval
!= ERROR_OK
)
906 retval
= stm32l4_read_flash_reg_by_index(bank
, flash_cr_index
, &ctrl
);
907 if (retval
!= ERROR_OK
)
910 if (ctrl
& FLASH_OPTLOCK
) {
911 LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32
, ctrl
);
912 return ERROR_TARGET_FAILURE
;
918 static int stm32l4_perform_obl_launch(struct flash_bank
*bank
)
922 retval
= stm32l4_unlock_reg(bank
);
923 if (retval
!= ERROR_OK
)
926 retval
= stm32l4_unlock_option_reg(bank
);
927 if (retval
!= ERROR_OK
)
930 /* Set OBL_LAUNCH bit in CR -> system reset and option bytes reload,
931 * but the RMs explicitly do *NOT* list this as power-on reset cause, and:
932 * "Note: If the read protection is set while the debugger is still
933 * connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset."
936 /* "Setting OBL_LAUNCH generates a reset so the option byte loading is performed under system reset" */
937 /* Due to this reset ST-Link reports an SWD_DP_ERROR, despite the write was successful,
938 * then just ignore the returned value */
939 stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, FLASH_OBL_LAUNCH
);
941 /* Need to re-probe after change */
942 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
943 stm32l4_info
->probed
= false;
946 retval2
= stm32l4_write_flash_reg_by_index(bank
, stm32l4_get_flash_cr_with_lock_index(bank
),
947 FLASH_LOCK
| FLASH_OPTLOCK
);
949 if (retval
!= ERROR_OK
)
955 static int stm32l4_write_option(struct flash_bank
*bank
, uint32_t reg_offset
,
956 uint32_t value
, uint32_t mask
)
958 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
962 retval
= stm32l4_read_flash_reg(bank
, reg_offset
, &optiondata
);
963 if (retval
!= ERROR_OK
)
966 /* for STM32L5 and similar devices, use always non-secure
967 * registers for option bytes programming */
968 const uint32_t *saved_flash_regs
= stm32l4_info
->flash_regs
;
969 if (stm32l4_info
->part_info
->flags
& F_HAS_L5_FLASH_REGS
)
970 stm32l4_info
->flash_regs
= stm32l5_ns_flash_regs
;
972 retval
= stm32l4_unlock_reg(bank
);
973 if (retval
!= ERROR_OK
)
976 retval
= stm32l4_unlock_option_reg(bank
);
977 if (retval
!= ERROR_OK
)
980 optiondata
= (optiondata
& ~mask
) | (value
& mask
);
982 retval
= stm32l4_write_flash_reg(bank
, reg_offset
, optiondata
);
983 if (retval
!= ERROR_OK
)
986 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, FLASH_OPTSTRT
);
987 if (retval
!= ERROR_OK
)
990 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
993 retval2
= stm32l4_write_flash_reg_by_index(bank
, stm32l4_get_flash_cr_with_lock_index(bank
),
994 FLASH_LOCK
| FLASH_OPTLOCK
);
995 stm32l4_info
->flash_regs
= saved_flash_regs
;
997 if (retval
!= ERROR_OK
)
1003 static int stm32l4_get_one_wrpxy(struct flash_bank
*bank
, struct stm32l4_wrp
*wrpxy
,
1004 enum stm32l4_flash_reg_index reg_idx
, int offset
)
1006 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1009 wrpxy
->reg_idx
= reg_idx
;
1010 wrpxy
->offset
= offset
;
1012 ret
= stm32l4_read_flash_reg_by_index(bank
, wrpxy
->reg_idx
, &wrpxy
->value
);
1013 if (ret
!= ERROR_OK
)
1016 wrpxy
->first
= (wrpxy
->value
& stm32l4_info
->wrpxxr_mask
) + wrpxy
->offset
;
1017 wrpxy
->last
= ((wrpxy
->value
>> 16) & stm32l4_info
->wrpxxr_mask
) + wrpxy
->offset
;
1018 wrpxy
->used
= wrpxy
->first
<= wrpxy
->last
;
1023 static int stm32l4_get_all_wrpxy(struct flash_bank
*bank
, enum stm32_bank_id dev_bank_id
,
1024 struct stm32l4_wrp
*wrpxy
, unsigned int *n_wrp
)
1026 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1031 /* for single bank devices there is 2 WRP regions.
1032 * for dual bank devices there is 2 WRP regions per bank,
1033 * if configured as single bank only 2 WRP are usable
1034 * except for STM32L4R/S/P/Q, G4 cat3, L5 ... all 4 WRP are usable
1035 * note: this should be revised, if a device will have the SWAP banks option
1038 int wrp2y_sectors_offset
= -1; /* -1 : unused */
1040 /* if bank_id is BANK1 or ALL_BANKS */
1041 if (dev_bank_id
!= STM32_BANK2
) {
1042 /* get FLASH_WRP1AR */
1043 ret
= stm32l4_get_one_wrpxy(bank
, &wrpxy
[(*n_wrp
)++], STM32_FLASH_WRP1AR_INDEX
, 0);
1044 if (ret
!= ERROR_OK
)
1048 ret
= stm32l4_get_one_wrpxy(bank
, &wrpxy
[(*n_wrp
)++], STM32_FLASH_WRP1BR_INDEX
, 0);
1049 if (ret
!= ERROR_OK
)
1052 /* for some devices (like STM32L4R/S) in single-bank mode, the 4 WRPxx are usable */
1053 if ((stm32l4_info
->part_info
->flags
& F_USE_ALL_WRPXX
) && !stm32l4_info
->dual_bank_mode
)
1054 wrp2y_sectors_offset
= 0;
1057 /* if bank_id is BANK2 or ALL_BANKS */
1058 if (dev_bank_id
!= STM32_BANK1
&& stm32l4_info
->dual_bank_mode
)
1059 wrp2y_sectors_offset
= stm32l4_info
->bank1_sectors
;
1061 if (wrp2y_sectors_offset
> -1) {
1063 ret
= stm32l4_get_one_wrpxy(bank
, &wrpxy
[(*n_wrp
)++], STM32_FLASH_WRP2AR_INDEX
, wrp2y_sectors_offset
);
1064 if (ret
!= ERROR_OK
)
1068 ret
= stm32l4_get_one_wrpxy(bank
, &wrpxy
[(*n_wrp
)++], STM32_FLASH_WRP2BR_INDEX
, wrp2y_sectors_offset
);
1069 if (ret
!= ERROR_OK
)
1076 static int stm32l4_write_one_wrpxy(struct flash_bank
*bank
, struct stm32l4_wrp
*wrpxy
)
1078 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1080 int wrp_start
= wrpxy
->first
- wrpxy
->offset
;
1081 int wrp_end
= wrpxy
->last
- wrpxy
->offset
;
1083 uint32_t wrp_value
= (wrp_start
& stm32l4_info
->wrpxxr_mask
) | ((wrp_end
& stm32l4_info
->wrpxxr_mask
) << 16);
1085 return stm32l4_write_option(bank
, stm32l4_info
->flash_regs
[wrpxy
->reg_idx
], wrp_value
, 0xffffffff);
1088 static int stm32l4_write_all_wrpxy(struct flash_bank
*bank
, struct stm32l4_wrp
*wrpxy
, unsigned int n_wrp
)
1092 for (unsigned int i
= 0; i
< n_wrp
; i
++) {
1093 ret
= stm32l4_write_one_wrpxy(bank
, &wrpxy
[i
]);
1094 if (ret
!= ERROR_OK
)
1101 static int stm32l4_protect_check(struct flash_bank
*bank
)
1104 struct stm32l4_wrp wrpxy
[4];
1106 int ret
= stm32l4_get_all_wrpxy(bank
, STM32_ALL_BANKS
, wrpxy
, &n_wrp
);
1107 if (ret
!= ERROR_OK
)
1110 /* initialize all sectors as unprotected */
1111 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++)
1112 bank
->sectors
[i
].is_protected
= 0;
1114 /* now check WRPxy and mark the protected sectors */
1115 for (unsigned int i
= 0; i
< n_wrp
; i
++) {
1116 if (wrpxy
[i
].used
) {
1117 for (int s
= wrpxy
[i
].first
; s
<= wrpxy
[i
].last
; s
++)
1118 bank
->sectors
[s
].is_protected
= 1;
1125 static int stm32l4_erase(struct flash_bank
*bank
, unsigned int first
,
1128 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1129 int retval
, retval2
;
1131 assert((first
<= last
) && (last
< bank
->num_sectors
));
1133 if (stm32l4_is_otp(bank
)) {
1134 LOG_ERROR("cannot erase OTP memory");
1135 return ERROR_FLASH_OPER_UNSUPPORTED
;
1138 if (bank
->target
->state
!= TARGET_HALTED
) {
1139 LOG_ERROR("Target not halted");
1140 return ERROR_TARGET_NOT_HALTED
;
1143 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0
)) {
1144 /* set all FLASH pages as secure */
1145 retval
= stm32l4_set_secbb(bank
, FLASH_SECBB_SECURE
);
1146 if (retval
!= ERROR_OK
) {
1147 /* restore all FLASH pages as non-secure */
1148 stm32l4_set_secbb(bank
, FLASH_SECBB_NON_SECURE
); /* ignore the return value */
1153 retval
= stm32l4_unlock_reg(bank
);
1154 if (retval
!= ERROR_OK
)
1159 To erase a sector, follow the procedure below:
1160 1. Check that no Flash memory operation is ongoing by
1161 checking the BSY bit in the FLASH_SR register
1162 2. Set the PER bit and select the page and bank
1163 you wish to erase in the FLASH_CR register
1164 3. Set the STRT bit in the FLASH_CR register
1165 4. Wait for the BSY bit to be cleared
1168 for (unsigned int i
= first
; i
<= last
; i
++) {
1169 uint32_t erase_flags
;
1170 erase_flags
= FLASH_PER
| FLASH_STRT
;
1172 if (i
>= stm32l4_info
->bank1_sectors
) {
1174 snb
= i
- stm32l4_info
->bank1_sectors
;
1175 erase_flags
|= snb
<< FLASH_PAGE_SHIFT
| stm32l4_info
->cr_bker_mask
;
1177 erase_flags
|= i
<< FLASH_PAGE_SHIFT
;
1178 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, erase_flags
);
1179 if (retval
!= ERROR_OK
)
1182 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
1183 if (retval
!= ERROR_OK
)
1188 retval2
= stm32l4_write_flash_reg_by_index(bank
, stm32l4_get_flash_cr_with_lock_index(bank
), FLASH_LOCK
);
1190 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0
)) {
1191 /* restore all FLASH pages as non-secure */
1192 int retval3
= stm32l4_set_secbb(bank
, FLASH_SECBB_NON_SECURE
);
1193 if (retval3
!= ERROR_OK
)
1197 if (retval
!= ERROR_OK
)
1203 static int stm32l4_protect(struct flash_bank
*bank
, int set
, unsigned int first
, unsigned int last
)
1205 struct target
*target
= bank
->target
;
1206 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1210 if (stm32l4_is_otp(bank
)) {
1211 LOG_ERROR("cannot protect/unprotect OTP memory");
1212 return ERROR_FLASH_OPER_UNSUPPORTED
;
1215 if (target
->state
!= TARGET_HALTED
) {
1216 LOG_ERROR("Target not halted");
1217 return ERROR_TARGET_NOT_HALTED
;
1220 /* the requested sectors could be located into bank1 and/or bank2 */
1221 bool use_bank2
= false;
1222 if (last
>= stm32l4_info
->bank1_sectors
) {
1223 if (first
< stm32l4_info
->bank1_sectors
) {
1224 /* the requested sectors for (un)protection are shared between
1225 * bank 1 and 2, then split the operation */
1227 /* 1- deal with bank 1 sectors */
1228 LOG_DEBUG("The requested sectors for %s are shared between bank 1 and 2",
1229 set
? "protection" : "unprotection");
1230 ret
= stm32l4_protect(bank
, set
, first
, stm32l4_info
->bank1_sectors
- 1);
1231 if (ret
!= ERROR_OK
)
1234 /* 2- then continue with bank 2 sectors */
1235 first
= stm32l4_info
->bank1_sectors
;
1241 /* refresh the sectors' protection */
1242 ret
= stm32l4_protect_check(bank
);
1243 if (ret
!= ERROR_OK
)
1246 /* check if the desired protection is already configured */
1247 for (i
= first
; i
<= last
; i
++) {
1248 if (bank
->sectors
[i
].is_protected
!= set
)
1250 else if (i
== last
) {
1251 LOG_INFO("The specified sectors are already %s", set
? "protected" : "unprotected");
1256 /* all sectors from first to last (or part of them) could have different
1257 * protection other than the requested */
1259 struct stm32l4_wrp wrpxy
[4];
1261 ret
= stm32l4_get_all_wrpxy(bank
, use_bank2
? STM32_BANK2
: STM32_BANK1
, wrpxy
, &n_wrp
);
1262 if (ret
!= ERROR_OK
)
1265 /* use bitmap and range helpers to optimize the WRP usage */
1266 DECLARE_BITMAP(pages
, bank
->num_sectors
);
1267 bitmap_zero(pages
, bank
->num_sectors
);
1269 for (i
= 0; i
< n_wrp
; i
++) {
1270 if (wrpxy
[i
].used
) {
1271 for (int p
= wrpxy
[i
].first
; p
<= wrpxy
[i
].last
; p
++)
1276 /* we have at most 'n_wrp' WRP areas
1277 * add one range if the user is trying to protect a fifth range */
1278 struct range ranges
[n_wrp
+ 1];
1279 unsigned int ranges_count
= 0;
1281 bitmap_to_ranges(pages
, bank
->num_sectors
, ranges
, &ranges_count
);
1283 /* pretty-print the currently protected ranges */
1284 if (ranges_count
> 0) {
1285 char *ranges_str
= range_print_alloc(ranges
, ranges_count
);
1286 LOG_DEBUG("current protected areas: %s", ranges_str
);
1289 LOG_DEBUG("current protected areas: none");
1291 if (set
) { /* flash protect */
1292 for (i
= first
; i
<= last
; i
++)
1294 } else { /* flash unprotect */
1295 for (i
= first
; i
<= last
; i
++)
1296 clear_bit(i
, pages
);
1299 /* check the ranges_count after the user request */
1300 bitmap_to_ranges(pages
, bank
->num_sectors
, ranges
, &ranges_count
);
1302 /* pretty-print the requested areas for protection */
1303 if (ranges_count
> 0) {
1304 char *ranges_str
= range_print_alloc(ranges
, ranges_count
);
1305 LOG_DEBUG("requested areas for protection: %s", ranges_str
);
1308 LOG_DEBUG("requested areas for protection: none");
1310 if (ranges_count
> n_wrp
) {
1311 LOG_ERROR("cannot set the requested protection "
1312 "(only %u write protection areas are available)" , n_wrp
);
1316 /* re-init all WRPxy as disabled (first > last)*/
1317 for (i
= 0; i
< n_wrp
; i
++) {
1318 wrpxy
[i
].first
= wrpxy
[i
].offset
+ 1;
1319 wrpxy
[i
].last
= wrpxy
[i
].offset
;
1322 /* then configure WRPxy areas */
1323 for (i
= 0; i
< ranges_count
; i
++) {
1324 wrpxy
[i
].first
= ranges
[i
].start
;
1325 wrpxy
[i
].last
= ranges
[i
].end
;
1328 /* finally write WRPxy registers */
1329 return stm32l4_write_all_wrpxy(bank
, wrpxy
, n_wrp
);
1332 /* count is the size divided by stm32l4_info->data_width */
1333 static int stm32l4_write_block(struct flash_bank
*bank
, const uint8_t *buffer
,
1334 uint32_t offset
, uint32_t count
)
1336 struct target
*target
= bank
->target
;
1337 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1338 struct working_area
*write_algorithm
;
1339 struct working_area
*source
;
1340 uint32_t address
= bank
->base
+ offset
;
1341 struct reg_param reg_params
[5];
1342 struct armv7m_algorithm armv7m_info
;
1343 int retval
= ERROR_OK
;
1345 static const uint8_t stm32l4_flash_write_code
[] = {
1346 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
1349 if (target_alloc_working_area(target
, sizeof(stm32l4_flash_write_code
),
1350 &write_algorithm
) != ERROR_OK
) {
1351 LOG_WARNING("no working area available, can't do block memory writes");
1352 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1355 retval
= target_write_buffer(target
, write_algorithm
->address
,
1356 sizeof(stm32l4_flash_write_code
),
1357 stm32l4_flash_write_code
);
1358 if (retval
!= ERROR_OK
) {
1359 target_free_working_area(target
, write_algorithm
);
1363 /* data_width should be multiple of double-word */
1364 assert(stm32l4_info
->data_width
% 8 == 0);
1365 const size_t extra_size
= sizeof(struct stm32l4_work_area
);
1366 uint32_t buffer_size
= target_get_working_area_avail(target
) - extra_size
;
1367 /* buffer_size should be multiple of stm32l4_info->data_width */
1368 buffer_size
&= ~(stm32l4_info
->data_width
- 1);
1370 if (buffer_size
< 256) {
1371 LOG_WARNING("large enough working area not available, can't do block memory writes");
1372 target_free_working_area(target
, write_algorithm
);
1373 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1374 } else if (buffer_size
> 16384) {
1375 /* probably won't benefit from more than 16k ... */
1376 buffer_size
= 16384;
1379 if (target_alloc_working_area_try(target
, buffer_size
+ extra_size
, &source
) != ERROR_OK
) {
1380 LOG_ERROR("allocating working area failed");
1381 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1384 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
1385 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
1387 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* buffer start, status (out) */
1388 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* buffer end */
1389 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* target address */
1390 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
); /* count (of stm32l4_info->data_width) */
1391 init_reg_param(®_params
[4], "sp", 32, PARAM_OUT
); /* write algo stack pointer */
1393 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1394 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
+ source
->size
);
1395 buf_set_u32(reg_params
[2].value
, 0, 32, address
);
1396 buf_set_u32(reg_params
[3].value
, 0, 32, count
);
1397 buf_set_u32(reg_params
[4].value
, 0, 32, source
->address
+
1398 offsetof(struct stm32l4_work_area
, stack
) + LDR_STACK_SIZE
);
1400 struct stm32l4_loader_params loader_extra_params
;
1402 target_buffer_set_u32(target
, (uint8_t *) &loader_extra_params
.flash_sr_addr
,
1403 stm32l4_get_flash_reg_by_index(bank
, STM32_FLASH_SR_INDEX
));
1404 target_buffer_set_u32(target
, (uint8_t *) &loader_extra_params
.flash_cr_addr
,
1405 stm32l4_get_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
));
1406 target_buffer_set_u32(target
, (uint8_t *) &loader_extra_params
.flash_word_size
,
1407 stm32l4_info
->data_width
);
1408 target_buffer_set_u32(target
, (uint8_t *) &loader_extra_params
.flash_sr_bsy_mask
,
1409 stm32l4_info
->sr_bsy_mask
);
1411 retval
= target_write_buffer(target
, source
->address
, sizeof(loader_extra_params
),
1412 (uint8_t *) &loader_extra_params
);
1413 if (retval
!= ERROR_OK
)
1416 retval
= target_run_flash_async_algorithm(target
, buffer
, count
, stm32l4_info
->data_width
,
1418 ARRAY_SIZE(reg_params
), reg_params
,
1419 source
->address
+ offsetof(struct stm32l4_work_area
, fifo
),
1420 source
->size
- offsetof(struct stm32l4_work_area
, fifo
),
1421 write_algorithm
->address
, 0,
1424 if (retval
== ERROR_FLASH_OPERATION_FAILED
) {
1425 LOG_ERROR("error executing stm32l4 flash write algorithm");
1428 stm32l4_read_flash_reg_by_index(bank
, STM32_FLASH_SR_INDEX
, &error
);
1429 error
&= FLASH_ERROR
;
1431 if (error
& FLASH_WRPERR
)
1432 LOG_ERROR("flash memory write protected");
1435 LOG_ERROR("flash write failed = %08" PRIx32
, error
);
1436 /* Clear but report errors */
1437 stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_SR_INDEX
, error
);
1438 retval
= ERROR_FAIL
;
1442 target_free_working_area(target
, source
);
1443 target_free_working_area(target
, write_algorithm
);
1445 destroy_reg_param(®_params
[0]);
1446 destroy_reg_param(®_params
[1]);
1447 destroy_reg_param(®_params
[2]);
1448 destroy_reg_param(®_params
[3]);
1449 destroy_reg_param(®_params
[4]);
1454 /* count is the size divided by stm32l4_info->data_width */
1455 static int stm32l4_write_block_without_loader(struct flash_bank
*bank
, const uint8_t *buffer
,
1456 uint32_t offset
, uint32_t count
)
1458 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1459 struct target
*target
= bank
->target
;
1460 uint32_t address
= bank
->base
+ offset
;
1461 int retval
= ERROR_OK
;
1463 /* wait for BSY bit */
1464 retval
= stm32l4_wait_status_busy(bank
, FLASH_WRITE_TIMEOUT
);
1465 if (retval
!= ERROR_OK
)
1468 /* set PG in FLASH_CR */
1469 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, FLASH_PG
);
1470 if (retval
!= ERROR_OK
)
1474 /* write directly to flash memory */
1475 const uint8_t *src
= buffer
;
1476 const uint32_t data_width_in_words
= stm32l4_info
->data_width
/ 4;
1478 retval
= target_write_memory(target
, address
, 4, data_width_in_words
, src
);
1479 if (retval
!= ERROR_OK
)
1482 /* wait for BSY bit */
1483 retval
= stm32l4_wait_status_busy(bank
, FLASH_WRITE_TIMEOUT
);
1484 if (retval
!= ERROR_OK
)
1487 src
+= stm32l4_info
->data_width
;
1488 address
+= stm32l4_info
->data_width
;
1491 /* reset PG in FLASH_CR */
1492 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, 0);
1493 if (retval
!= ERROR_OK
)
1499 static int stm32l4_write(struct flash_bank
*bank
, const uint8_t *buffer
,
1500 uint32_t offset
, uint32_t count
)
1502 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1503 int retval
= ERROR_OK
, retval2
;
1505 if (stm32l4_is_otp(bank
) && !stm32l4_otp_is_enabled(bank
)) {
1506 LOG_ERROR("OTP memory is disabled for write commands");
1510 if (bank
->target
->state
!= TARGET_HALTED
) {
1511 LOG_ERROR("Target not halted");
1512 return ERROR_TARGET_NOT_HALTED
;
1515 /* ensure that stm32l4_info->data_width is 'at least' a multiple of dword */
1516 assert(stm32l4_info
->data_width
% 8 == 0);
1518 /* The flash write must be aligned to the 'stm32l4_info->data_width' boundary.
1519 * The flash infrastructure ensures it, do just a security check */
1520 assert(offset
% stm32l4_info
->data_width
== 0);
1521 assert(count
% stm32l4_info
->data_width
== 0);
1523 /* STM32G4xxx Cat. 3 devices may have gaps between banks, check whether
1524 * data to be written does not go into a gap:
1525 * suppose buffer is fully contained in bank from sector 0 to sector
1526 * num->sectors - 1 and sectors are ordered according to offset
1528 struct flash_sector
*head
= &bank
->sectors
[0];
1529 struct flash_sector
*tail
= &bank
->sectors
[bank
->num_sectors
- 1];
1531 while ((head
< tail
) && (offset
>= (head
+ 1)->offset
)) {
1532 /* buffer does not intersect head nor gap behind head */
1536 while ((head
< tail
) && (offset
+ count
<= (tail
- 1)->offset
+ (tail
- 1)->size
)) {
1537 /* buffer does not intersect tail nor gap before tail */
1541 LOG_DEBUG("data: 0x%08" PRIx32
" - 0x%08" PRIx32
", sectors: 0x%08" PRIx32
" - 0x%08" PRIx32
,
1542 offset
, offset
+ count
- 1, head
->offset
, tail
->offset
+ tail
->size
- 1);
1544 /* Now check that there is no gap from head to tail, this should work
1545 * even for multiple or non-symmetric gaps
1547 while (head
< tail
) {
1548 if (head
->offset
+ head
->size
!= (head
+ 1)->offset
) {
1549 LOG_ERROR("write into gap from " TARGET_ADDR_FMT
" to " TARGET_ADDR_FMT
,
1550 bank
->base
+ head
->offset
+ head
->size
,
1551 bank
->base
+ (head
+ 1)->offset
- 1);
1552 retval
= ERROR_FLASH_DST_OUT_OF_BANK
;
1557 if (retval
!= ERROR_OK
)
1560 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0
)) {
1561 /* set all FLASH pages as secure */
1562 retval
= stm32l4_set_secbb(bank
, FLASH_SECBB_SECURE
);
1563 if (retval
!= ERROR_OK
) {
1564 /* restore all FLASH pages as non-secure */
1565 stm32l4_set_secbb(bank
, FLASH_SECBB_NON_SECURE
); /* ignore the return value */
1570 retval
= stm32l4_unlock_reg(bank
);
1571 if (retval
!= ERROR_OK
)
1574 if (stm32l4_info
->use_flashloader
) {
1575 /* For TrustZone enabled devices, when TZEN is set and RDP level is 0.5,
1576 * the debug is possible only in non-secure state.
1577 * Thus means the flashloader will run in non-secure mode,
1578 * and the workarea need to be in non-secure RAM */
1579 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0_5
))
1580 LOG_INFO("RDP level is 0.5, the work-area should reside in non-secure RAM");
1582 retval
= stm32l4_write_block(bank
, buffer
, offset
,
1583 count
/ stm32l4_info
->data_width
);
1586 if (!stm32l4_info
->use_flashloader
|| retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
) {
1587 LOG_INFO("falling back to single memory accesses");
1588 retval
= stm32l4_write_block_without_loader(bank
, buffer
, offset
,
1589 count
/ stm32l4_info
->data_width
);
1593 retval2
= stm32l4_write_flash_reg_by_index(bank
, stm32l4_get_flash_cr_with_lock_index(bank
), FLASH_LOCK
);
1595 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0
)) {
1596 /* restore all FLASH pages as non-secure */
1597 int retval3
= stm32l4_set_secbb(bank
, FLASH_SECBB_NON_SECURE
);
1598 if (retval3
!= ERROR_OK
)
1602 if (retval
!= ERROR_OK
) {
1603 LOG_ERROR("block write failed");
1609 static int stm32l4_read_idcode(struct flash_bank
*bank
, uint32_t *id
)
1613 /* try reading possible IDCODE registers, in the following order */
1614 uint32_t dbgmcu_idcode
[] = {DBGMCU_IDCODE_L4_G4
, DBGMCU_IDCODE_G0
, DBGMCU_IDCODE_L5
};
1616 for (unsigned int i
= 0; i
< ARRAY_SIZE(dbgmcu_idcode
); i
++) {
1617 retval
= target_read_u32(bank
->target
, dbgmcu_idcode
[i
], id
);
1618 if ((retval
== ERROR_OK
) && ((*id
& 0xfff) != 0) && ((*id
& 0xfff) != 0xfff))
1622 /* Workaround for STM32WL5x devices:
1623 * DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1,
1624 * to solve this read the UID64 (IEEE 64-bit unique device ID register) */
1626 struct cortex_m_common
*cortex_m
= target_to_cm(bank
->target
);
1628 if (cortex_m
->core_info
->partno
== CORTEX_M0P_PARTNO
&& cortex_m
->armv7m
.debug_ap
->ap_num
== 1) {
1631 /* UID64 is contains
1632 * - Bits 63:32 : DEVNUM (unique device number, different for each individual device)
1633 * - Bits 31:08 : STID (company ID) = 0x0080E1
1634 * - Bits 07:00 : DEVID (device ID) = 0x15
1636 * read only the fixed values {STID,DEVID} from UID64_IDS to identify the device as STM32WLx
1638 retval
= target_read_u32(bank
->target
, UID64_IDS
, &uid64_ids
);
1639 if (retval
== ERROR_OK
&& uid64_ids
== UID64_IDS_STM32WL
) {
1640 /* force the DEV_ID to 0x497 and the REV_ID to unknown */
1646 LOG_ERROR("can't get the device id");
1647 return (retval
== ERROR_OK
) ? ERROR_FAIL
: retval
;
1650 static const char *get_stm32l4_rev_str(struct flash_bank
*bank
)
1652 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1653 const struct stm32l4_part_info
*part_info
= stm32l4_info
->part_info
;
1656 const uint16_t rev_id
= stm32l4_info
->idcode
>> 16;
1657 for (unsigned int i
= 0; i
< part_info
->num_revs
; i
++) {
1658 if (rev_id
== part_info
->revs
[i
].rev
)
1659 return part_info
->revs
[i
].str
;
1664 static const char *get_stm32l4_bank_type_str(struct flash_bank
*bank
)
1666 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1667 assert(stm32l4_info
->part_info
);
1668 return stm32l4_is_otp(bank
) ? "OTP" :
1669 stm32l4_info
->dual_bank_mode
? "Flash dual" :
1673 static int stm32l4_probe(struct flash_bank
*bank
)
1675 struct target
*target
= bank
->target
;
1676 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1677 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1678 const struct stm32l4_part_info
*part_info
;
1679 uint16_t flash_size_kb
= 0xffff;
1681 stm32l4_info
->probed
= false;
1683 /* read stm32 device id registers */
1684 int retval
= stm32l4_read_idcode(bank
, &stm32l4_info
->idcode
);
1685 if (retval
!= ERROR_OK
)
1688 const uint32_t device_id
= stm32l4_info
->idcode
& 0xFFF;
1690 for (unsigned int n
= 0; n
< ARRAY_SIZE(stm32l4_parts
); n
++) {
1691 if (device_id
== stm32l4_parts
[n
].id
) {
1692 stm32l4_info
->part_info
= &stm32l4_parts
[n
];
1697 if (!stm32l4_info
->part_info
) {
1698 LOG_WARNING("Cannot identify target as an %s family device.", device_families
);
1702 part_info
= stm32l4_info
->part_info
;
1703 const char *rev_str
= get_stm32l4_rev_str(bank
);
1704 const uint16_t rev_id
= stm32l4_info
->idcode
>> 16;
1706 LOG_INFO("device idcode = 0x%08" PRIx32
" (%s - Rev %s : 0x%04x)",
1707 stm32l4_info
->idcode
, part_info
->device_str
, rev_str
, rev_id
);
1709 stm32l4_info
->flash_regs_base
= stm32l4_info
->part_info
->flash_regs_base
;
1710 stm32l4_info
->data_width
= (part_info
->flags
& F_QUAD_WORD_PROG
) ? 16 : 8;
1711 stm32l4_info
->cr_bker_mask
= FLASH_BKER
;
1712 stm32l4_info
->sr_bsy_mask
= FLASH_BSY
;
1714 /* Set flash write alignment boundaries.
1715 * Ask the flash infrastructure to ensure required alignment */
1716 bank
->write_start_alignment
= bank
->write_end_alignment
= stm32l4_info
->data_width
;
1718 /* initialise the flash registers layout */
1719 if (part_info
->flags
& F_HAS_L5_FLASH_REGS
)
1720 stm32l4_info
->flash_regs
= stm32l5_ns_flash_regs
;
1722 stm32l4_info
->flash_regs
= stm32l4_flash_regs
;
1724 /* read flash option register */
1725 retval
= stm32l4_read_flash_reg_by_index(bank
, STM32_FLASH_OPTR_INDEX
, &stm32l4_info
->optr
);
1726 if (retval
!= ERROR_OK
)
1729 stm32l4_sync_rdp_tzen(bank
);
1731 /* for devices with trustzone, use flash secure registers when TZEN=1 and RDP is LEVEL_0 */
1732 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0
)) {
1733 if (part_info
->flags
& F_HAS_L5_FLASH_REGS
) {
1734 stm32l4_info
->flash_regs_base
|= STM32L5_REGS_SEC_OFFSET
;
1735 stm32l4_info
->flash_regs
= stm32l5_s_flash_regs
;
1737 LOG_ERROR("BUG: device supported incomplete");
1738 return ERROR_NOT_IMPLEMENTED
;
1742 if (part_info
->flags
& F_HAS_TZ
)
1743 LOG_INFO("TZEN = %d : TrustZone %s by option bytes",
1745 stm32l4_info
->tzen
? "enabled" : "disabled");
1747 LOG_INFO("RDP level %s (0x%02X)",
1748 stm32l4_info
->rdp
== RDP_LEVEL_0
? "0" : stm32l4_info
->rdp
== RDP_LEVEL_0_5
? "0.5" : "1",
1751 if (stm32l4_is_otp(bank
)) {
1752 bank
->size
= part_info
->otp_size
;
1754 LOG_INFO("OTP size is %d bytes, base address is " TARGET_ADDR_FMT
, bank
->size
, bank
->base
);
1756 /* OTP memory is considered as one sector */
1757 free(bank
->sectors
);
1758 bank
->num_sectors
= 1;
1759 bank
->sectors
= alloc_block_array(0, part_info
->otp_size
, 1);
1761 if (!bank
->sectors
) {
1762 LOG_ERROR("failed to allocate bank sectors");
1766 stm32l4_info
->probed
= true;
1768 } else if (bank
->base
!= STM32_FLASH_BANK_BASE
&& bank
->base
!= STM32_FLASH_S_BANK_BASE
) {
1769 LOG_ERROR("invalid bank base address");
1773 /* get flash size from target. */
1774 retval
= target_read_u16(target
, part_info
->fsize_addr
, &flash_size_kb
);
1776 /* failed reading flash size or flash size invalid (early silicon),
1777 * default to max target family */
1778 if (retval
!= ERROR_OK
|| flash_size_kb
== 0xffff || flash_size_kb
== 0
1779 || flash_size_kb
> part_info
->max_flash_size_kb
) {
1780 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
1781 part_info
->max_flash_size_kb
);
1782 flash_size_kb
= part_info
->max_flash_size_kb
;
1785 /* if the user sets the size manually then ignore the probed value
1786 * this allows us to work around devices that have a invalid flash size register value */
1787 if (stm32l4_info
->user_bank_size
) {
1788 LOG_WARNING("overriding size register by configured bank size - MAY CAUSE TROUBLE");
1789 flash_size_kb
= stm32l4_info
->user_bank_size
/ 1024;
1792 LOG_INFO("flash size = %dkbytes", flash_size_kb
);
1794 /* did we assign a flash size? */
1795 assert((flash_size_kb
!= 0xffff) && flash_size_kb
);
1797 stm32l4_info
->bank1_sectors
= 0;
1798 stm32l4_info
->hole_sectors
= 0;
1801 int page_size_kb
= 0;
1803 stm32l4_info
->dual_bank_mode
= false;
1804 bool use_dbank_bit
= false;
1806 switch (device_id
) {
1807 case 0x415: /* STM32L47/L48xx */
1808 case 0x461: /* STM32L49/L4Axx */
1809 /* if flash size is max (1M) the device is always dual bank
1810 * 0x415: has variants with 512K
1811 * 0x461: has variants with 512 and 256
1812 * for these variants:
1813 * if DUAL_BANK = 0 -> single bank
1814 * else -> dual bank without gap
1815 * note: the page size is invariant
1818 num_pages
= flash_size_kb
/ page_size_kb
;
1819 stm32l4_info
->bank1_sectors
= num_pages
;
1821 /* check DUAL_BANK bit[21] if the flash is less than 1M */
1822 if (flash_size_kb
== 1024 || (stm32l4_info
->optr
& BIT(21))) {
1823 stm32l4_info
->dual_bank_mode
= true;
1824 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
1827 case 0x435: /* STM32L43/L44xx */
1828 case 0x456: /* STM32G05/G06xx */
1829 case 0x460: /* STM32G07/G08xx */
1830 case 0x462: /* STM32L45/L46xx */
1831 case 0x464: /* STM32L41/L42xx */
1832 case 0x466: /* STM32G03/G04xx */
1833 case 0x468: /* STM32G43/G44xx */
1834 case 0x479: /* STM32G49/G4Axx */
1835 /* single bank flash */
1837 num_pages
= flash_size_kb
/ page_size_kb
;
1838 stm32l4_info
->bank1_sectors
= num_pages
;
1840 case 0x467: /* STM32G0B/G0Cxx */
1841 /* single/dual bank depending on bit(21) */
1843 num_pages
= flash_size_kb
/ page_size_kb
;
1844 stm32l4_info
->bank1_sectors
= num_pages
;
1845 stm32l4_info
->cr_bker_mask
= FLASH_BKER_G0
;
1847 /* check DUAL_BANK bit */
1848 if (stm32l4_info
->optr
& BIT(21)) {
1849 stm32l4_info
->sr_bsy_mask
= FLASH_BSY
| FLASH_BSY2
;
1850 stm32l4_info
->dual_bank_mode
= true;
1851 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
1854 case 0x469: /* STM32G47/G48xx */
1855 /* STM32G47/8 can be single/dual bank:
1856 * if DUAL_BANK = 0 -> single bank
1857 * else -> dual bank WITH gap
1860 num_pages
= flash_size_kb
/ page_size_kb
;
1861 stm32l4_info
->bank1_sectors
= num_pages
;
1862 if (stm32l4_info
->optr
& BIT(22)) {
1863 stm32l4_info
->dual_bank_mode
= true;
1865 num_pages
= flash_size_kb
/ page_size_kb
;
1866 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
1868 /* for devices with trimmed flash, there is a gap between both banks */
1869 stm32l4_info
->hole_sectors
=
1870 (part_info
->max_flash_size_kb
- flash_size_kb
) / (2 * page_size_kb
);
1873 case 0x470: /* STM32L4R/L4Sxx */
1874 case 0x471: /* STM32L4P5/L4Q5x */
1875 /* STM32L4R/S can be single/dual bank:
1876 * if size = 2M check DBANK bit(22)
1877 * if size = 1M check DB1M bit(21)
1878 * STM32L4P/Q can be single/dual bank
1879 * if size = 1M check DBANK bit(22)
1880 * if size = 512K check DB512K bit(21)
1883 num_pages
= flash_size_kb
/ page_size_kb
;
1884 stm32l4_info
->bank1_sectors
= num_pages
;
1885 use_dbank_bit
= flash_size_kb
== part_info
->max_flash_size_kb
;
1886 if ((use_dbank_bit
&& (stm32l4_info
->optr
& BIT(22))) ||
1887 (!use_dbank_bit
&& (stm32l4_info
->optr
& BIT(21)))) {
1888 stm32l4_info
->dual_bank_mode
= true;
1890 num_pages
= flash_size_kb
/ page_size_kb
;
1891 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
1894 case 0x472: /* STM32L55/L56xx */
1895 /* STM32L55/L56xx can be single/dual bank:
1896 * if size = 512K check DBANK bit(22)
1897 * if size = 256K check DB256K bit(21)
1900 num_pages
= flash_size_kb
/ page_size_kb
;
1901 stm32l4_info
->bank1_sectors
= num_pages
;
1902 use_dbank_bit
= flash_size_kb
== part_info
->max_flash_size_kb
;
1903 if ((use_dbank_bit
&& (stm32l4_info
->optr
& BIT(22))) ||
1904 (!use_dbank_bit
&& (stm32l4_info
->optr
& BIT(21)))) {
1905 stm32l4_info
->dual_bank_mode
= true;
1907 num_pages
= flash_size_kb
/ page_size_kb
;
1908 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
1911 case 0x482: /* STM32U57/U58xx */
1912 /* if flash size is max (2M) the device is always dual bank
1913 * otherwise check DUALBANK bit(21)
1916 num_pages
= flash_size_kb
/ page_size_kb
;
1917 stm32l4_info
->bank1_sectors
= num_pages
;
1918 if ((flash_size_kb
== part_info
->max_flash_size_kb
) || (stm32l4_info
->optr
& BIT(21))) {
1919 stm32l4_info
->dual_bank_mode
= true;
1920 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
1923 case 0x495: /* STM32WB5x */
1924 case 0x496: /* STM32WB3x */
1925 /* single bank flash */
1927 num_pages
= flash_size_kb
/ page_size_kb
;
1928 stm32l4_info
->bank1_sectors
= num_pages
;
1930 case 0x497: /* STM32WLEx/WL5x */
1931 /* single bank flash */
1933 num_pages
= flash_size_kb
/ page_size_kb
;
1934 stm32l4_info
->bank1_sectors
= num_pages
;
1935 if (armv7m
->debug_ap
->ap_num
== 1)
1936 stm32l4_info
->flash_regs
= stm32wl_cpu2_flash_regs
;
1939 LOG_ERROR("unsupported device");
1943 LOG_INFO("flash mode : %s-bank", stm32l4_info
->dual_bank_mode
? "dual" : "single");
1945 const int gap_size_kb
= stm32l4_info
->hole_sectors
* page_size_kb
;
1947 if (gap_size_kb
!= 0) {
1948 LOG_INFO("gap detected from 0x%08x to 0x%08x",
1949 STM32_FLASH_BANK_BASE
+ stm32l4_info
->bank1_sectors
1950 * page_size_kb
* 1024,
1951 STM32_FLASH_BANK_BASE
+ (stm32l4_info
->bank1_sectors
1952 * page_size_kb
+ gap_size_kb
) * 1024 - 1);
1955 /* number of significant bits in WRPxxR differs per device,
1956 * always right adjusted, on some devices non-implemented
1957 * bits read as '0', on others as '1' ...
1958 * notably G4 Cat. 2 implement only 6 bits, contradicting the RM
1961 /* use *max_flash_size* instead of actual size as the trimmed versions
1962 * certainly use the same number of bits
1963 * max_flash_size is always power of two, so max_pages too
1965 uint32_t max_pages
= stm32l4_info
->part_info
->max_flash_size_kb
/ page_size_kb
;
1966 assert(IS_PWR_OF_2(max_pages
));
1968 /* in dual bank mode number of pages is doubled, but extra bit is bank selection */
1969 stm32l4_info
->wrpxxr_mask
= ((max_pages
>> (stm32l4_info
->dual_bank_mode
? 1 : 0)) - 1);
1970 assert((stm32l4_info
->wrpxxr_mask
& 0xFFFF0000) == 0);
1971 LOG_DEBUG("WRPxxR mask 0x%04" PRIx16
, (uint16_t)stm32l4_info
->wrpxxr_mask
);
1973 free(bank
->sectors
);
1975 bank
->size
= (flash_size_kb
+ gap_size_kb
) * 1024;
1976 bank
->num_sectors
= num_pages
;
1977 bank
->sectors
= malloc(sizeof(struct flash_sector
) * bank
->num_sectors
);
1978 if (!bank
->sectors
) {
1979 LOG_ERROR("failed to allocate bank sectors");
1983 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++) {
1984 bank
->sectors
[i
].offset
= i
* page_size_kb
* 1024;
1985 /* in dual bank configuration, if there is a gap between banks
1986 * we fix up the sector offset to consider this gap */
1987 if (i
>= stm32l4_info
->bank1_sectors
&& stm32l4_info
->hole_sectors
)
1988 bank
->sectors
[i
].offset
+= gap_size_kb
* 1024;
1989 bank
->sectors
[i
].size
= page_size_kb
* 1024;
1990 bank
->sectors
[i
].is_erased
= -1;
1991 bank
->sectors
[i
].is_protected
= 1;
1994 stm32l4_info
->probed
= true;
1998 static int stm32l4_auto_probe(struct flash_bank
*bank
)
2000 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
2001 if (stm32l4_info
->probed
) {
2004 /* read flash option register and re-probe if optr value is changed */
2005 int retval
= stm32l4_read_flash_reg_by_index(bank
, STM32_FLASH_OPTR_INDEX
, &optr_cur
);
2006 if (retval
!= ERROR_OK
)
2009 if (stm32l4_info
->optr
== optr_cur
)
2013 return stm32l4_probe(bank
);
2016 static int get_stm32l4_info(struct flash_bank
*bank
, struct command_invocation
*cmd
)
2018 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
2019 const struct stm32l4_part_info
*part_info
= stm32l4_info
->part_info
;
2022 const uint16_t rev_id
= stm32l4_info
->idcode
>> 16;
2023 command_print_sameline(cmd
, "%s - Rev %s : 0x%04x", part_info
->device_str
,
2024 get_stm32l4_rev_str(bank
), rev_id
);
2025 if (stm32l4_info
->probed
)
2026 command_print_sameline(cmd
, " - %s-bank", get_stm32l4_bank_type_str(bank
));
2028 command_print_sameline(cmd
, "Cannot identify target as an %s device", device_families
);
2034 static int stm32l4_mass_erase(struct flash_bank
*bank
)
2036 int retval
, retval2
;
2037 struct target
*target
= bank
->target
;
2038 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
2040 if (stm32l4_is_otp(bank
)) {
2041 LOG_ERROR("cannot erase OTP memory");
2042 return ERROR_FLASH_OPER_UNSUPPORTED
;
2045 uint32_t action
= FLASH_MER1
;
2047 if (stm32l4_info
->part_info
->flags
& F_HAS_DUAL_BANK
)
2048 action
|= FLASH_MER2
;
2050 if (target
->state
!= TARGET_HALTED
) {
2051 LOG_ERROR("Target not halted");
2052 return ERROR_TARGET_NOT_HALTED
;
2055 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0
)) {
2056 /* set all FLASH pages as secure */
2057 retval
= stm32l4_set_secbb(bank
, FLASH_SECBB_SECURE
);
2058 if (retval
!= ERROR_OK
) {
2059 /* restore all FLASH pages as non-secure */
2060 stm32l4_set_secbb(bank
, FLASH_SECBB_NON_SECURE
); /* ignore the return value */
2065 retval
= stm32l4_unlock_reg(bank
);
2066 if (retval
!= ERROR_OK
)
2069 /* mass erase flash memory */
2070 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
/ 10);
2071 if (retval
!= ERROR_OK
)
2074 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, action
);
2075 if (retval
!= ERROR_OK
)
2078 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, action
| FLASH_STRT
);
2079 if (retval
!= ERROR_OK
)
2082 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
2085 retval2
= stm32l4_write_flash_reg_by_index(bank
, stm32l4_get_flash_cr_with_lock_index(bank
), FLASH_LOCK
);
2087 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0
)) {
2088 /* restore all FLASH pages as non-secure */
2089 int retval3
= stm32l4_set_secbb(bank
, FLASH_SECBB_NON_SECURE
);
2090 if (retval3
!= ERROR_OK
)
2094 if (retval
!= ERROR_OK
)
2100 COMMAND_HANDLER(stm32l4_handle_mass_erase_command
)
2103 command_print(CMD
, "stm32l4x mass_erase <STM32L4 bank>");
2104 return ERROR_COMMAND_SYNTAX_ERROR
;
2107 struct flash_bank
*bank
;
2108 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2109 if (retval
!= ERROR_OK
)
2112 retval
= stm32l4_mass_erase(bank
);
2113 if (retval
== ERROR_OK
)
2114 command_print(CMD
, "stm32l4x mass erase complete");
2116 command_print(CMD
, "stm32l4x mass erase failed");
2121 COMMAND_HANDLER(stm32l4_handle_option_read_command
)
2124 command_print(CMD
, "stm32l4x option_read <STM32L4 bank> <option_reg offset>");
2125 return ERROR_COMMAND_SYNTAX_ERROR
;
2128 struct flash_bank
*bank
;
2129 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2130 if (retval
!= ERROR_OK
)
2133 uint32_t reg_offset
, reg_addr
;
2136 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], reg_offset
);
2137 reg_addr
= stm32l4_get_flash_reg(bank
, reg_offset
);
2139 retval
= stm32l4_read_flash_reg(bank
, reg_offset
, &value
);
2140 if (retval
!= ERROR_OK
)
2143 command_print(CMD
, "Option Register: <0x%" PRIx32
"> = 0x%" PRIx32
"", reg_addr
, value
);
2148 COMMAND_HANDLER(stm32l4_handle_option_write_command
)
2151 command_print(CMD
, "stm32l4x option_write <STM32L4 bank> <option_reg offset> <value> [mask]");
2152 return ERROR_COMMAND_SYNTAX_ERROR
;
2155 struct flash_bank
*bank
;
2156 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2157 if (retval
!= ERROR_OK
)
2160 uint32_t reg_offset
;
2162 uint32_t mask
= 0xFFFFFFFF;
2164 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], reg_offset
);
2165 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], value
);
2168 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[3], mask
);
2170 command_print(CMD
, "%s Option written.\n"
2171 "INFO: a reset or power cycle is required "
2172 "for the new settings to take effect.", bank
->driver
->name
);
2174 retval
= stm32l4_write_option(bank
, reg_offset
, value
, mask
);
2178 COMMAND_HANDLER(stm32l4_handle_trustzone_command
)
2180 if (CMD_ARGC
< 1 || CMD_ARGC
> 2)
2181 return ERROR_COMMAND_SYNTAX_ERROR
;
2183 struct flash_bank
*bank
;
2184 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2185 if (retval
!= ERROR_OK
)
2188 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
2189 if (!(stm32l4_info
->part_info
->flags
& F_HAS_TZ
)) {
2190 LOG_ERROR("This device does not have a TrustZone");
2194 retval
= stm32l4_read_flash_reg_by_index(bank
, STM32_FLASH_OPTR_INDEX
, &stm32l4_info
->optr
);
2195 if (retval
!= ERROR_OK
)
2198 stm32l4_sync_rdp_tzen(bank
);
2200 if (CMD_ARGC
== 1) {
2201 /* only display the TZEN value */
2202 LOG_INFO("Global TrustZone Security is %s", stm32l4_info
->tzen
? "enabled" : "disabled");
2207 COMMAND_PARSE_ENABLE(CMD_ARGV
[1], new_tzen
);
2209 if (new_tzen
== stm32l4_info
->tzen
) {
2210 LOG_INFO("The requested TZEN is already programmed");
2215 if (stm32l4_info
->rdp
!= RDP_LEVEL_0
) {
2216 LOG_ERROR("TZEN can be set only when RDP level is 0");
2219 retval
= stm32l4_write_option(bank
, stm32l4_info
->flash_regs
[STM32_FLASH_OPTR_INDEX
],
2220 FLASH_TZEN
, FLASH_TZEN
);
2222 /* Deactivation of TZEN (from 1 to 0) is only possible when the RDP is
2223 * changing to level 0 (from level 1 to level 0 or from level 0.5 to level 0). */
2224 if (stm32l4_info
->rdp
!= RDP_LEVEL_1
&& stm32l4_info
->rdp
!= RDP_LEVEL_0_5
) {
2225 LOG_ERROR("Deactivation of TZEN is only possible when the RDP is changing to level 0");
2229 retval
= stm32l4_write_option(bank
, stm32l4_info
->flash_regs
[STM32_FLASH_OPTR_INDEX
],
2230 RDP_LEVEL_0
, FLASH_RDP_MASK
| FLASH_TZEN
);
2233 if (retval
!= ERROR_OK
)
2236 return stm32l4_perform_obl_launch(bank
);
2239 COMMAND_HANDLER(stm32l4_handle_flashloader_command
)
2241 if (CMD_ARGC
< 1 || CMD_ARGC
> 2)
2242 return ERROR_COMMAND_SYNTAX_ERROR
;
2244 struct flash_bank
*bank
;
2245 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2246 if (retval
!= ERROR_OK
)
2249 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
2252 COMMAND_PARSE_ENABLE(CMD_ARGV
[1], stm32l4_info
->use_flashloader
);
2254 command_print(CMD
, "FlashLoader usage is %s", stm32l4_info
->use_flashloader
? "enabled" : "disabled");
2259 COMMAND_HANDLER(stm32l4_handle_option_load_command
)
2262 return ERROR_COMMAND_SYNTAX_ERROR
;
2264 struct flash_bank
*bank
;
2265 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2266 if (retval
!= ERROR_OK
)
2269 retval
= stm32l4_perform_obl_launch(bank
);
2270 if (retval
!= ERROR_OK
) {
2271 command_print(CMD
, "stm32l4x option load failed");
2276 command_print(CMD
, "stm32l4x option load completed. Power-on reset might be required");
2281 COMMAND_HANDLER(stm32l4_handle_lock_command
)
2283 struct target
*target
= NULL
;
2286 return ERROR_COMMAND_SYNTAX_ERROR
;
2288 struct flash_bank
*bank
;
2289 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2290 if (retval
!= ERROR_OK
)
2293 if (stm32l4_is_otp(bank
)) {
2294 LOG_ERROR("cannot lock/unlock OTP memory");
2295 return ERROR_FLASH_OPER_UNSUPPORTED
;
2298 target
= bank
->target
;
2300 if (target
->state
!= TARGET_HALTED
) {
2301 LOG_ERROR("Target not halted");
2302 return ERROR_TARGET_NOT_HALTED
;
2305 /* set readout protection level 1 by erasing the RDP option byte */
2306 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
2307 if (stm32l4_write_option(bank
, stm32l4_info
->flash_regs
[STM32_FLASH_OPTR_INDEX
],
2308 RDP_LEVEL_1
, FLASH_RDP_MASK
) != ERROR_OK
) {
2309 command_print(CMD
, "%s failed to lock device", bank
->driver
->name
);
2316 COMMAND_HANDLER(stm32l4_handle_unlock_command
)
2318 struct target
*target
= NULL
;
2321 return ERROR_COMMAND_SYNTAX_ERROR
;
2323 struct flash_bank
*bank
;
2324 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2325 if (retval
!= ERROR_OK
)
2328 if (stm32l4_is_otp(bank
)) {
2329 LOG_ERROR("cannot lock/unlock OTP memory");
2330 return ERROR_FLASH_OPER_UNSUPPORTED
;
2333 target
= bank
->target
;
2335 if (target
->state
!= TARGET_HALTED
) {
2336 LOG_ERROR("Target not halted");
2337 return ERROR_TARGET_NOT_HALTED
;
2340 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
2341 if (stm32l4_write_option(bank
, stm32l4_info
->flash_regs
[STM32_FLASH_OPTR_INDEX
],
2342 RDP_LEVEL_0
, FLASH_RDP_MASK
) != ERROR_OK
) {
2343 command_print(CMD
, "%s failed to unlock device", bank
->driver
->name
);
2350 COMMAND_HANDLER(stm32l4_handle_wrp_info_command
)
2352 if (CMD_ARGC
< 1 || CMD_ARGC
> 2)
2353 return ERROR_COMMAND_SYNTAX_ERROR
;
2355 struct flash_bank
*bank
;
2356 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2357 if (retval
!= ERROR_OK
)
2360 if (stm32l4_is_otp(bank
)) {
2361 LOG_ERROR("OTP memory does not have write protection areas");
2362 return ERROR_FLASH_OPER_UNSUPPORTED
;
2365 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
2366 enum stm32_bank_id dev_bank_id
= STM32_ALL_BANKS
;
2367 if (CMD_ARGC
== 2) {
2368 if (strcmp(CMD_ARGV
[1], "bank1") == 0)
2369 dev_bank_id
= STM32_BANK1
;
2370 else if (strcmp(CMD_ARGV
[1], "bank2") == 0)
2371 dev_bank_id
= STM32_BANK2
;
2373 return ERROR_COMMAND_ARGUMENT_INVALID
;
2376 if (dev_bank_id
== STM32_BANK2
) {
2377 if (!(stm32l4_info
->part_info
->flags
& F_HAS_DUAL_BANK
)) {
2378 LOG_ERROR("this device has no second bank");
2380 } else if (!stm32l4_info
->dual_bank_mode
) {
2381 LOG_ERROR("this device is configured in single bank mode");
2387 unsigned int n_wrp
, i
;
2388 struct stm32l4_wrp wrpxy
[4];
2390 ret
= stm32l4_get_all_wrpxy(bank
, dev_bank_id
, wrpxy
, &n_wrp
);
2391 if (ret
!= ERROR_OK
)
2394 /* use bitmap and range helpers to better describe protected areas */
2395 DECLARE_BITMAP(pages
, bank
->num_sectors
);
2396 bitmap_zero(pages
, bank
->num_sectors
);
2398 for (i
= 0; i
< n_wrp
; i
++) {
2399 if (wrpxy
[i
].used
) {
2400 for (int p
= wrpxy
[i
].first
; p
<= wrpxy
[i
].last
; p
++)
2405 /* we have at most 'n_wrp' WRP areas */
2406 struct range ranges
[n_wrp
];
2407 unsigned int ranges_count
= 0;
2409 bitmap_to_ranges(pages
, bank
->num_sectors
, ranges
, &ranges_count
);
2411 if (ranges_count
> 0) {
2412 /* pretty-print the protected ranges */
2413 char *ranges_str
= range_print_alloc(ranges
, ranges_count
);
2414 command_print(CMD
, "protected areas: %s", ranges_str
);
2417 command_print(CMD
, "no protected areas");
2422 COMMAND_HANDLER(stm32l4_handle_otp_command
)
2425 return ERROR_COMMAND_SYNTAX_ERROR
;
2427 struct flash_bank
*bank
;
2428 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2429 if (retval
!= ERROR_OK
)
2432 if (!stm32l4_is_otp(bank
)) {
2433 command_print(CMD
, "the specified bank is not an OTP memory");
2436 if (strcmp(CMD_ARGV
[1], "enable") == 0)
2437 stm32l4_otp_enable(bank
, true);
2438 else if (strcmp(CMD_ARGV
[1], "disable") == 0)
2439 stm32l4_otp_enable(bank
, false);
2440 else if (strcmp(CMD_ARGV
[1], "show") == 0)
2441 command_print(CMD
, "OTP memory bank #%d is %s for write commands.",
2442 bank
->bank_number
, stm32l4_otp_is_enabled(bank
) ? "enabled" : "disabled");
2444 return ERROR_COMMAND_SYNTAX_ERROR
;
2449 static const struct command_registration stm32l4_exec_command_handlers
[] = {
2452 .handler
= stm32l4_handle_lock_command
,
2453 .mode
= COMMAND_EXEC
,
2455 .help
= "Lock entire flash device.",
2459 .handler
= stm32l4_handle_unlock_command
,
2460 .mode
= COMMAND_EXEC
,
2462 .help
= "Unlock entire protected flash device.",
2465 .name
= "flashloader",
2466 .handler
= stm32l4_handle_flashloader_command
,
2467 .mode
= COMMAND_EXEC
,
2468 .usage
= "<bank_id> [enable|disable]",
2469 .help
= "Configure the flashloader usage",
2472 .name
= "mass_erase",
2473 .handler
= stm32l4_handle_mass_erase_command
,
2474 .mode
= COMMAND_EXEC
,
2476 .help
= "Erase entire flash device.",
2479 .name
= "option_read",
2480 .handler
= stm32l4_handle_option_read_command
,
2481 .mode
= COMMAND_EXEC
,
2482 .usage
= "bank_id reg_offset",
2483 .help
= "Read & Display device option bytes.",
2486 .name
= "option_write",
2487 .handler
= stm32l4_handle_option_write_command
,
2488 .mode
= COMMAND_EXEC
,
2489 .usage
= "bank_id reg_offset value mask",
2490 .help
= "Write device option bit fields with provided value.",
2493 .name
= "trustzone",
2494 .handler
= stm32l4_handle_trustzone_command
,
2495 .mode
= COMMAND_EXEC
,
2496 .usage
= "<bank_id> [enable|disable]",
2497 .help
= "Configure TrustZone security",
2501 .handler
= stm32l4_handle_wrp_info_command
,
2502 .mode
= COMMAND_EXEC
,
2503 .usage
= "bank_id [bank1|bank2]",
2504 .help
= "list the protected areas using WRP",
2507 .name
= "option_load",
2508 .handler
= stm32l4_handle_option_load_command
,
2509 .mode
= COMMAND_EXEC
,
2511 .help
= "Force re-load of device options (will cause device reset).",
2515 .handler
= stm32l4_handle_otp_command
,
2516 .mode
= COMMAND_EXEC
,
2517 .usage
= "<bank_id> <enable|disable|show>",
2518 .help
= "OTP (One Time Programmable) memory write enable/disable",
2520 COMMAND_REGISTRATION_DONE
2523 static const struct command_registration stm32l4_command_handlers
[] = {
2526 .mode
= COMMAND_ANY
,
2527 .help
= "stm32l4x flash command group",
2529 .chain
= stm32l4_exec_command_handlers
,
2531 COMMAND_REGISTRATION_DONE
2534 const struct flash_driver stm32l4x_flash
= {
2536 .commands
= stm32l4_command_handlers
,
2537 .flash_bank_command
= stm32l4_flash_bank_command
,
2538 .erase
= stm32l4_erase
,
2539 .protect
= stm32l4_protect
,
2540 .write
= stm32l4_write
,
2541 .read
= default_flash_read
,
2542 .probe
= stm32l4_probe
,
2543 .auto_probe
= stm32l4_auto_probe
,
2544 .erase_check
= default_flash_blank_check
,
2545 .protect_check
= stm32l4_protect_check
,
2546 .info
= get_stm32l4_info
,
2547 .free_driver_priv
= default_flash_free_driver_priv
,