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armv7m.h: relax dependency from 'arm_adi_v5.h'
[openocd.git] / src / flash / nor / stm32l4x.c
1 /***************************************************************************
2 * Copyright (C) 2015 by Uwe Bonnes *
3 * bon@elektron.ikp.physik.tu-darmstadt.de *
4 * *
5 * Copyright (C) 2019 by Tarek Bochkati for STMicroelectronics *
6 * tarek.bouchkati@gmail.com *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
20 ***************************************************************************/
21
22 #ifdef HAVE_CONFIG_H
23 #include "config.h"
24 #endif
25
26 #include "imp.h"
27 #include <helper/align.h>
28 #include <helper/binarybuffer.h>
29 #include <target/algorithm.h>
30 #include <target/arm_adi_v5.h>
31 #include <target/cortex_m.h>
32 #include "bits.h"
33 #include "stm32l4x.h"
34
35 /* STM32L4xxx series for reference.
36 *
37 * RM0351 (STM32L4x5/STM32L4x6)
38 * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
39 *
40 * RM0394 (STM32L43x/44x/45x/46x)
41 * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
42 *
43 * RM0432 (STM32L4R/4Sxx)
44 * http://www.st.com/resource/en/reference_manual/dm00310109.pdf
45 *
46 * STM32L476RG Datasheet (for erase timing)
47 * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
48 *
49 * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
50 * an option byte is available to map all sectors to the first bank.
51 * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
52 * handlers do!
53 *
54 * RM0394 devices have a single bank only.
55 *
56 * RM0432 devices have single and dual bank operating modes.
57 * - for STM32L4R/Sxx the FLASH size is 2Mbyte or 1Mbyte.
58 * - for STM32L4P/Q5x the FLASH size is 1Mbyte or 512Kbyte.
59 * Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
60 *
61 * Bank mode is controlled by two different bits in option bytes register.
62 * - for STM32L4R/Sxx
63 * In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
64 * In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
65 * - for STM32L4P5/Q5x
66 * In 1M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
67 * In 512K FLASH devices bit 21 (DB512K) controls Dual Bank mode.
68 */
69
70 /* STM32WBxxx series for reference.
71 *
72 * RM0434 (STM32WB55/WB35x)
73 * http://www.st.com/resource/en/reference_manual/dm00318631.pdf
74 *
75 * RM0471 (STM32WB50/WB30x)
76 * http://www.st.com/resource/en/reference_manual/dm00622834.pdf
77 *
78 * RM0473 (STM32WB15x)
79 * http://www.st.com/resource/en/reference_manual/dm00649196.pdf
80 *
81 * RM0478 (STM32WB10x)
82 * http://www.st.com/resource/en/reference_manual/dm00689203.pdf
83 */
84
85 /* STM32WLxxx series for reference.
86 *
87 * RM0461 (STM32WLEx)
88 * http://www.st.com/resource/en/reference_manual/dm00530369.pdf
89 *
90 * RM0453 (STM32WL5x)
91 * http://www.st.com/resource/en/reference_manual/dm00451556.pdf
92 */
93
94 /* STM32G0xxx series for reference.
95 *
96 * RM0444 (STM32G0x1)
97 * http://www.st.com/resource/en/reference_manual/dm00371828.pdf
98 *
99 * RM0454 (STM32G0x0)
100 * http://www.st.com/resource/en/reference_manual/dm00463896.pdf
101 */
102
103 /* STM32G4xxx series for reference.
104 *
105 * RM0440 (STM32G43x/44x/47x/48x/49x/4Ax)
106 * http://www.st.com/resource/en/reference_manual/dm00355726.pdf
107 *
108 * Cat. 2 devices have single bank only, page size is 2kByte.
109 *
110 * Cat. 3 devices have single and dual bank operating modes,
111 * Page size is 2kByte (dual mode) or 4kByte (single mode).
112 *
113 * Bank mode is controlled by bit 22 (DBANK) in option bytes register.
114 * Both banks are treated as a single OpenOCD bank.
115 *
116 * Cat. 4 devices have single bank only, page size is 2kByte.
117 */
118
119 /* STM32L5xxx series for reference.
120 *
121 * RM0428 (STM32L552xx/STM32L562xx)
122 * http://www.st.com/resource/en/reference_manual/dm00346336.pdf
123 */
124
125 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
126
127 #define FLASH_ERASE_TIMEOUT 250
128 #define FLASH_WRITE_TIMEOUT 50
129
130
131 /* relevant STM32L4 flags ****************************************************/
132 #define F_NONE 0
133 /* this flag indicates if the device flash is with dual bank architecture */
134 #define F_HAS_DUAL_BANK BIT(0)
135 /* this flags is used for dual bank devices only, it indicates if the
136 * 4 WRPxx are usable if the device is configured in single-bank mode */
137 #define F_USE_ALL_WRPXX BIT(1)
138 /* this flag indicates if the device embeds a TrustZone security feature */
139 #define F_HAS_TZ BIT(2)
140 /* this flag indicates if the device has the same flash registers as STM32L5 */
141 #define F_HAS_L5_FLASH_REGS BIT(3)
142 /* this flag indicates that programming should be done in quad-word
143 * the default programming word size is double-word */
144 #define F_QUAD_WORD_PROG BIT(4)
145 /* end of STM32L4 flags ******************************************************/
146
147
148 enum stm32l4_flash_reg_index {
149 STM32_FLASH_ACR_INDEX,
150 STM32_FLASH_KEYR_INDEX,
151 STM32_FLASH_OPTKEYR_INDEX,
152 STM32_FLASH_SR_INDEX,
153 STM32_FLASH_CR_INDEX,
154 /* for some devices like STM32WL5x, the CPU2 have a dedicated C2CR register w/o LOCKs,
155 * so it uses the C2CR for flash operations and CR for checking locks and locking */
156 STM32_FLASH_CR_WLK_INDEX, /* FLASH_CR_WITH_LOCK */
157 STM32_FLASH_OPTR_INDEX,
158 STM32_FLASH_WRP1AR_INDEX,
159 STM32_FLASH_WRP1BR_INDEX,
160 STM32_FLASH_WRP2AR_INDEX,
161 STM32_FLASH_WRP2BR_INDEX,
162 STM32_FLASH_REG_INDEX_NUM,
163 };
164
165 enum stm32l4_rdp {
166 RDP_LEVEL_0 = 0xAA,
167 RDP_LEVEL_0_5 = 0x55, /* for devices with TrustZone enabled */
168 RDP_LEVEL_1 = 0x00,
169 RDP_LEVEL_2 = 0xCC
170 };
171
172 static const uint32_t stm32l4_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
173 [STM32_FLASH_ACR_INDEX] = 0x000,
174 [STM32_FLASH_KEYR_INDEX] = 0x008,
175 [STM32_FLASH_OPTKEYR_INDEX] = 0x00C,
176 [STM32_FLASH_SR_INDEX] = 0x010,
177 [STM32_FLASH_CR_INDEX] = 0x014,
178 [STM32_FLASH_OPTR_INDEX] = 0x020,
179 [STM32_FLASH_WRP1AR_INDEX] = 0x02C,
180 [STM32_FLASH_WRP1BR_INDEX] = 0x030,
181 [STM32_FLASH_WRP2AR_INDEX] = 0x04C,
182 [STM32_FLASH_WRP2BR_INDEX] = 0x050,
183 };
184
185 static const uint32_t stm32wl_cpu2_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
186 [STM32_FLASH_ACR_INDEX] = 0x000,
187 [STM32_FLASH_KEYR_INDEX] = 0x008,
188 [STM32_FLASH_OPTKEYR_INDEX] = 0x010,
189 [STM32_FLASH_SR_INDEX] = 0x060,
190 [STM32_FLASH_CR_INDEX] = 0x064,
191 [STM32_FLASH_CR_WLK_INDEX] = 0x014,
192 [STM32_FLASH_OPTR_INDEX] = 0x020,
193 [STM32_FLASH_WRP1AR_INDEX] = 0x02C,
194 [STM32_FLASH_WRP1BR_INDEX] = 0x030,
195 };
196
197 static const uint32_t stm32l5_ns_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
198 [STM32_FLASH_ACR_INDEX] = 0x000,
199 [STM32_FLASH_KEYR_INDEX] = 0x008, /* NSKEYR */
200 [STM32_FLASH_OPTKEYR_INDEX] = 0x010,
201 [STM32_FLASH_SR_INDEX] = 0x020, /* NSSR */
202 [STM32_FLASH_CR_INDEX] = 0x028, /* NSCR */
203 [STM32_FLASH_OPTR_INDEX] = 0x040,
204 [STM32_FLASH_WRP1AR_INDEX] = 0x058,
205 [STM32_FLASH_WRP1BR_INDEX] = 0x05C,
206 [STM32_FLASH_WRP2AR_INDEX] = 0x068,
207 [STM32_FLASH_WRP2BR_INDEX] = 0x06C,
208 };
209
210 static const uint32_t stm32l5_s_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
211 [STM32_FLASH_ACR_INDEX] = 0x000,
212 [STM32_FLASH_KEYR_INDEX] = 0x00C, /* SECKEYR */
213 [STM32_FLASH_OPTKEYR_INDEX] = 0x010,
214 [STM32_FLASH_SR_INDEX] = 0x024, /* SECSR */
215 [STM32_FLASH_CR_INDEX] = 0x02C, /* SECCR */
216 [STM32_FLASH_OPTR_INDEX] = 0x040,
217 [STM32_FLASH_WRP1AR_INDEX] = 0x058,
218 [STM32_FLASH_WRP1BR_INDEX] = 0x05C,
219 [STM32_FLASH_WRP2AR_INDEX] = 0x068,
220 [STM32_FLASH_WRP2BR_INDEX] = 0x06C,
221 };
222
223 struct stm32l4_rev {
224 const uint16_t rev;
225 const char *str;
226 };
227
228 struct stm32l4_part_info {
229 uint16_t id;
230 const char *device_str;
231 const struct stm32l4_rev *revs;
232 const size_t num_revs;
233 const uint16_t max_flash_size_kb;
234 const uint32_t flags; /* one bit per feature, see STM32L4 flags: macros F_XXX */
235 const uint32_t flash_regs_base;
236 const uint32_t fsize_addr;
237 const uint32_t otp_base;
238 const uint32_t otp_size;
239 };
240
241 struct stm32l4_flash_bank {
242 bool probed;
243 uint32_t idcode;
244 unsigned int bank1_sectors;
245 bool dual_bank_mode;
246 int hole_sectors;
247 uint32_t user_bank_size;
248 uint32_t data_width;
249 uint32_t cr_bker_mask;
250 uint32_t sr_bsy_mask;
251 uint32_t wrpxxr_mask;
252 const struct stm32l4_part_info *part_info;
253 uint32_t flash_regs_base;
254 const uint32_t *flash_regs;
255 bool otp_enabled;
256 enum stm32l4_rdp rdp;
257 bool tzen;
258 uint32_t optr;
259 };
260
261 enum stm32_bank_id {
262 STM32_BANK1,
263 STM32_BANK2,
264 STM32_ALL_BANKS
265 };
266
267 struct stm32l4_wrp {
268 enum stm32l4_flash_reg_index reg_idx;
269 uint32_t value;
270 bool used;
271 int first;
272 int last;
273 int offset;
274 };
275
276 /* human readable list of families this drivers supports (sorted alphabetically) */
277 static const char *device_families = "STM32G0/G4/L4/L4+/L5/U5/WB/WL";
278
279 static const struct stm32l4_rev stm32l47_l48xx_revs[] = {
280 { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
281 };
282
283 static const struct stm32l4_rev stm32l43_l44xx_revs[] = {
284 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
285 };
286
287 static const struct stm32l4_rev stm32g05_g06xx_revs[] = {
288 { 0x1000, "A" },
289 };
290
291 static const struct stm32l4_rev stm32_g07_g08xx_revs[] = {
292 { 0x1000, "A/Z" } /* A and Z, no typo in RM! */, { 0x2000, "B" },
293 };
294
295 static const struct stm32l4_rev stm32l49_l4axx_revs[] = {
296 { 0x1000, "A" }, { 0x2000, "B" },
297 };
298
299 static const struct stm32l4_rev stm32l45_l46xx_revs[] = {
300 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
301 };
302
303 static const struct stm32l4_rev stm32l41_L42xx_revs[] = {
304 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
305 };
306
307 static const struct stm32l4_rev stm32g03_g04xx_revs[] = {
308 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2000, "B" },
309 };
310
311 static const struct stm32l4_rev stm32g0b_g0cxx_revs[] = {
312 { 0x1000, "A" },
313 };
314
315 static const struct stm32l4_rev stm32g43_g44xx_revs[] = {
316 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
317 };
318
319 static const struct stm32l4_rev stm32g47_g48xx_revs[] = {
320 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
321 };
322
323 static const struct stm32l4_rev stm32l4r_l4sxx_revs[] = {
324 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" },
325 };
326
327 static const struct stm32l4_rev stm32l4p_l4qxx_revs[] = {
328 { 0x1001, "Z" },
329 };
330
331 static const struct stm32l4_rev stm32l55_l56xx_revs[] = {
332 { 0x1000, "A" }, { 0x2000, "B" },
333 };
334
335 static const struct stm32l4_rev stm32g49_g4axx_revs[] = {
336 { 0x1000, "A" },
337 };
338
339 static const struct stm32l4_rev stm32u57_u58xx_revs[] = {
340 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x2000, "B" },
341 };
342
343 static const struct stm32l4_rev stm32wb1xx_revs[] = {
344 { 0x1000, "A" }, { 0x2000, "B" },
345 };
346
347 static const struct stm32l4_rev stm32wb5xx_revs[] = {
348 { 0x2001, "2.1" },
349 };
350
351 static const struct stm32l4_rev stm32wb3xx_revs[] = {
352 { 0x1000, "A" },
353 };
354
355 static const struct stm32l4_rev stm32wle_wl5xx_revs[] = {
356 { 0x1000, "1.0" },
357 };
358
359 static const struct stm32l4_part_info stm32l4_parts[] = {
360 {
361 .id = DEVID_STM32L47_L48XX,
362 .revs = stm32l47_l48xx_revs,
363 .num_revs = ARRAY_SIZE(stm32l47_l48xx_revs),
364 .device_str = "STM32L47/L48xx",
365 .max_flash_size_kb = 1024,
366 .flags = F_HAS_DUAL_BANK,
367 .flash_regs_base = 0x40022000,
368 .fsize_addr = 0x1FFF75E0,
369 .otp_base = 0x1FFF7000,
370 .otp_size = 1024,
371 },
372 {
373 .id = DEVID_STM32L43_L44XX,
374 .revs = stm32l43_l44xx_revs,
375 .num_revs = ARRAY_SIZE(stm32l43_l44xx_revs),
376 .device_str = "STM32L43/L44xx",
377 .max_flash_size_kb = 256,
378 .flags = F_NONE,
379 .flash_regs_base = 0x40022000,
380 .fsize_addr = 0x1FFF75E0,
381 .otp_base = 0x1FFF7000,
382 .otp_size = 1024,
383 },
384 {
385 .id = DEVID_STM32G05_G06XX,
386 .revs = stm32g05_g06xx_revs,
387 .num_revs = ARRAY_SIZE(stm32g05_g06xx_revs),
388 .device_str = "STM32G05/G06xx",
389 .max_flash_size_kb = 64,
390 .flags = F_NONE,
391 .flash_regs_base = 0x40022000,
392 .fsize_addr = 0x1FFF75E0,
393 .otp_base = 0x1FFF7000,
394 .otp_size = 1024,
395 },
396 {
397 .id = DEVID_STM32G07_G08XX,
398 .revs = stm32_g07_g08xx_revs,
399 .num_revs = ARRAY_SIZE(stm32_g07_g08xx_revs),
400 .device_str = "STM32G07/G08xx",
401 .max_flash_size_kb = 128,
402 .flags = F_NONE,
403 .flash_regs_base = 0x40022000,
404 .fsize_addr = 0x1FFF75E0,
405 .otp_base = 0x1FFF7000,
406 .otp_size = 1024,
407 },
408 {
409 .id = DEVID_STM32L49_L4AXX,
410 .revs = stm32l49_l4axx_revs,
411 .num_revs = ARRAY_SIZE(stm32l49_l4axx_revs),
412 .device_str = "STM32L49/L4Axx",
413 .max_flash_size_kb = 1024,
414 .flags = F_HAS_DUAL_BANK,
415 .flash_regs_base = 0x40022000,
416 .fsize_addr = 0x1FFF75E0,
417 .otp_base = 0x1FFF7000,
418 .otp_size = 1024,
419 },
420 {
421 .id = DEVID_STM32L45_L46XX,
422 .revs = stm32l45_l46xx_revs,
423 .num_revs = ARRAY_SIZE(stm32l45_l46xx_revs),
424 .device_str = "STM32L45/L46xx",
425 .max_flash_size_kb = 512,
426 .flags = F_NONE,
427 .flash_regs_base = 0x40022000,
428 .fsize_addr = 0x1FFF75E0,
429 .otp_base = 0x1FFF7000,
430 .otp_size = 1024,
431 },
432 {
433 .id = DEVID_STM32L41_L42XX,
434 .revs = stm32l41_L42xx_revs,
435 .num_revs = ARRAY_SIZE(stm32l41_L42xx_revs),
436 .device_str = "STM32L41/L42xx",
437 .max_flash_size_kb = 128,
438 .flags = F_NONE,
439 .flash_regs_base = 0x40022000,
440 .fsize_addr = 0x1FFF75E0,
441 .otp_base = 0x1FFF7000,
442 .otp_size = 1024,
443 },
444 {
445 .id = DEVID_STM32G03_G04XX,
446 .revs = stm32g03_g04xx_revs,
447 .num_revs = ARRAY_SIZE(stm32g03_g04xx_revs),
448 .device_str = "STM32G03x/G04xx",
449 .max_flash_size_kb = 64,
450 .flags = F_NONE,
451 .flash_regs_base = 0x40022000,
452 .fsize_addr = 0x1FFF75E0,
453 .otp_base = 0x1FFF7000,
454 .otp_size = 1024,
455 },
456 {
457 .id = DEVID_STM32G0B_G0CXX,
458 .revs = stm32g0b_g0cxx_revs,
459 .num_revs = ARRAY_SIZE(stm32g0b_g0cxx_revs),
460 .device_str = "STM32G0B/G0Cx",
461 .max_flash_size_kb = 512,
462 .flags = F_HAS_DUAL_BANK,
463 .flash_regs_base = 0x40022000,
464 .fsize_addr = 0x1FFF75E0,
465 .otp_base = 0x1FFF7000,
466 .otp_size = 1024,
467 },
468 {
469 .id = DEVID_STM32G43_G44XX,
470 .revs = stm32g43_g44xx_revs,
471 .num_revs = ARRAY_SIZE(stm32g43_g44xx_revs),
472 .device_str = "STM32G43/G44xx",
473 .max_flash_size_kb = 128,
474 .flags = F_NONE,
475 .flash_regs_base = 0x40022000,
476 .fsize_addr = 0x1FFF75E0,
477 .otp_base = 0x1FFF7000,
478 .otp_size = 1024,
479 },
480 {
481 .id = DEVID_STM32G47_G48XX,
482 .revs = stm32g47_g48xx_revs,
483 .num_revs = ARRAY_SIZE(stm32g47_g48xx_revs),
484 .device_str = "STM32G47/G48xx",
485 .max_flash_size_kb = 512,
486 .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
487 .flash_regs_base = 0x40022000,
488 .fsize_addr = 0x1FFF75E0,
489 .otp_base = 0x1FFF7000,
490 .otp_size = 1024,
491 },
492 {
493 .id = DEVID_STM32L4R_L4SXX,
494 .revs = stm32l4r_l4sxx_revs,
495 .num_revs = ARRAY_SIZE(stm32l4r_l4sxx_revs),
496 .device_str = "STM32L4R/L4Sxx",
497 .max_flash_size_kb = 2048,
498 .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
499 .flash_regs_base = 0x40022000,
500 .fsize_addr = 0x1FFF75E0,
501 .otp_base = 0x1FFF7000,
502 .otp_size = 1024,
503 },
504 {
505 .id = DEVID_STM32L4P_L4QXX,
506 .revs = stm32l4p_l4qxx_revs,
507 .num_revs = ARRAY_SIZE(stm32l4p_l4qxx_revs),
508 .device_str = "STM32L4P/L4Qxx",
509 .max_flash_size_kb = 1024,
510 .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
511 .flash_regs_base = 0x40022000,
512 .fsize_addr = 0x1FFF75E0,
513 .otp_base = 0x1FFF7000,
514 .otp_size = 1024,
515 },
516 {
517 .id = DEVID_STM32L55_L56XX,
518 .revs = stm32l55_l56xx_revs,
519 .num_revs = ARRAY_SIZE(stm32l55_l56xx_revs),
520 .device_str = "STM32L55/L56xx",
521 .max_flash_size_kb = 512,
522 .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX | F_HAS_TZ | F_HAS_L5_FLASH_REGS,
523 .flash_regs_base = 0x40022000,
524 .fsize_addr = 0x0BFA05E0,
525 .otp_base = 0x0BFA0000,
526 .otp_size = 512,
527 },
528 {
529 .id = DEVID_STM32G49_G4AXX,
530 .revs = stm32g49_g4axx_revs,
531 .num_revs = ARRAY_SIZE(stm32g49_g4axx_revs),
532 .device_str = "STM32G49/G4Axx",
533 .max_flash_size_kb = 512,
534 .flags = F_NONE,
535 .flash_regs_base = 0x40022000,
536 .fsize_addr = 0x1FFF75E0,
537 .otp_base = 0x1FFF7000,
538 .otp_size = 1024,
539 },
540 {
541 .id = DEVID_STM32U57_U58XX,
542 .revs = stm32u57_u58xx_revs,
543 .num_revs = ARRAY_SIZE(stm32u57_u58xx_revs),
544 .device_str = "STM32U57/U58xx",
545 .max_flash_size_kb = 2048,
546 .flags = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ | F_HAS_L5_FLASH_REGS,
547 .flash_regs_base = 0x40022000,
548 .fsize_addr = 0x0BFA07A0,
549 .otp_base = 0x0BFA0000,
550 .otp_size = 512,
551 },
552 {
553 .id = DEVID_STM32WB1XX,
554 .revs = stm32wb1xx_revs,
555 .num_revs = ARRAY_SIZE(stm32wb1xx_revs),
556 .device_str = "STM32WB1x",
557 .max_flash_size_kb = 320,
558 .flags = F_NONE,
559 .flash_regs_base = 0x58004000,
560 .fsize_addr = 0x1FFF75E0,
561 .otp_base = 0x1FFF7000,
562 .otp_size = 1024,
563 },
564 {
565 .id = DEVID_STM32WB5XX,
566 .revs = stm32wb5xx_revs,
567 .num_revs = ARRAY_SIZE(stm32wb5xx_revs),
568 .device_str = "STM32WB5x",
569 .max_flash_size_kb = 1024,
570 .flags = F_NONE,
571 .flash_regs_base = 0x58004000,
572 .fsize_addr = 0x1FFF75E0,
573 .otp_base = 0x1FFF7000,
574 .otp_size = 1024,
575 },
576 {
577 .id = DEVID_STM32WB3XX,
578 .revs = stm32wb3xx_revs,
579 .num_revs = ARRAY_SIZE(stm32wb3xx_revs),
580 .device_str = "STM32WB3x",
581 .max_flash_size_kb = 512,
582 .flags = F_NONE,
583 .flash_regs_base = 0x58004000,
584 .fsize_addr = 0x1FFF75E0,
585 .otp_base = 0x1FFF7000,
586 .otp_size = 1024,
587 },
588 {
589 .id = DEVID_STM32WLE_WL5XX,
590 .revs = stm32wle_wl5xx_revs,
591 .num_revs = ARRAY_SIZE(stm32wle_wl5xx_revs),
592 .device_str = "STM32WLE/WL5x",
593 .max_flash_size_kb = 256,
594 .flags = F_NONE,
595 .flash_regs_base = 0x58004000,
596 .fsize_addr = 0x1FFF75E0,
597 .otp_base = 0x1FFF7000,
598 .otp_size = 1024,
599 },
600 };
601
602 /* flash bank stm32l4x <base> <size> 0 0 <target#> */
603 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
604 {
605 struct stm32l4_flash_bank *stm32l4_info;
606
607 if (CMD_ARGC < 6)
608 return ERROR_COMMAND_SYNTAX_ERROR;
609
610 /* fix-up bank base address: 0 is used for normal flash memory */
611 if (bank->base == 0)
612 bank->base = STM32_FLASH_BANK_BASE;
613
614 stm32l4_info = calloc(1, sizeof(struct stm32l4_flash_bank));
615 if (!stm32l4_info)
616 return ERROR_FAIL; /* Checkme: What better error to use?*/
617 bank->driver_priv = stm32l4_info;
618
619 stm32l4_info->probed = false;
620 stm32l4_info->otp_enabled = false;
621 stm32l4_info->user_bank_size = bank->size;
622
623 return ERROR_OK;
624 }
625
626 /* bitmap helper extension */
627 struct range {
628 unsigned int start;
629 unsigned int end;
630 };
631
632 static void bitmap_to_ranges(unsigned long *bitmap, unsigned int nbits,
633 struct range *ranges, unsigned int *ranges_count) {
634 *ranges_count = 0;
635 bool last_bit = 0, cur_bit;
636 for (unsigned int i = 0; i < nbits; i++) {
637 cur_bit = test_bit(i, bitmap);
638
639 if (cur_bit && !last_bit) {
640 (*ranges_count)++;
641 ranges[*ranges_count - 1].start = i;
642 ranges[*ranges_count - 1].end = i;
643 } else if (cur_bit && last_bit) {
644 /* update (increment) the end this range */
645 ranges[*ranges_count - 1].end = i;
646 }
647
648 last_bit = cur_bit;
649 }
650 }
651
652 static inline int range_print_one(struct range *range, char *str)
653 {
654 if (range->start == range->end)
655 return sprintf(str, "[%d]", range->start);
656
657 return sprintf(str, "[%d,%d]", range->start, range->end);
658 }
659
660 static char *range_print_alloc(struct range *ranges, unsigned int ranges_count)
661 {
662 /* each range will be printed like the following: [start,end]
663 * start and end, both are unsigned int, an unsigned int takes 10 characters max
664 * plus 3 characters for '[', ',' and ']'
665 * thus means each range can take maximum 23 character
666 * after each range we add a ' ' as separator and finally we need the '\0'
667 * if the ranges_count is zero we reserve one char for '\0' to return an empty string */
668 char *str = calloc(1, ranges_count * (24 * sizeof(char)) + 1);
669 char *ptr = str;
670
671 for (unsigned int i = 0; i < ranges_count; i++) {
672 ptr += range_print_one(&(ranges[i]), ptr);
673
674 if (i < ranges_count - 1)
675 *(ptr++) = ' ';
676 }
677
678 return str;
679 }
680
681 /* end of bitmap helper extension */
682
683 static inline bool stm32l4_is_otp(struct flash_bank *bank)
684 {
685 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
686 return bank->base == stm32l4_info->part_info->otp_base;
687 }
688
689 static int stm32l4_otp_enable(struct flash_bank *bank, bool enable)
690 {
691 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
692
693 if (!stm32l4_is_otp(bank))
694 return ERROR_FAIL;
695
696 char *op_str = enable ? "enabled" : "disabled";
697
698 LOG_INFO("OTP memory (bank #%d) is %s%s for write commands",
699 bank->bank_number,
700 stm32l4_info->otp_enabled == enable ? "already " : "",
701 op_str);
702
703 stm32l4_info->otp_enabled = enable;
704
705 return ERROR_OK;
706 }
707
708 static inline bool stm32l4_otp_is_enabled(struct flash_bank *bank)
709 {
710 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
711 return stm32l4_info->otp_enabled;
712 }
713
714 static void stm32l4_sync_rdp_tzen(struct flash_bank *bank)
715 {
716 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
717
718 bool tzen = false;
719
720 if (stm32l4_info->part_info->flags & F_HAS_TZ)
721 tzen = (stm32l4_info->optr & FLASH_TZEN) != 0;
722
723 uint32_t rdp = stm32l4_info->optr & FLASH_RDP_MASK;
724
725 /* for devices without TrustZone:
726 * RDP level 0 and 2 values are to 0xAA and 0xCC
727 * Any other value corresponds to RDP level 1
728 * for devices with TrusZone:
729 * RDP level 0 and 2 values are 0xAA and 0xCC
730 * RDP level 0.5 value is 0x55 only if TZEN = 1
731 * Any other value corresponds to RDP level 1, including 0x55 if TZEN = 0
732 */
733
734 if (rdp != RDP_LEVEL_0 && rdp != RDP_LEVEL_2) {
735 if (!tzen || (tzen && rdp != RDP_LEVEL_0_5))
736 rdp = RDP_LEVEL_1;
737 }
738
739 stm32l4_info->tzen = tzen;
740 stm32l4_info->rdp = rdp;
741 }
742
743 static inline uint32_t stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
744 {
745 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
746 return stm32l4_info->flash_regs_base + reg_offset;
747 }
748
749 static inline uint32_t stm32l4_get_flash_reg_by_index(struct flash_bank *bank,
750 enum stm32l4_flash_reg_index reg_index)
751 {
752 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
753 return stm32l4_get_flash_reg(bank, stm32l4_info->flash_regs[reg_index]);
754 }
755
756 static inline int stm32l4_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
757 {
758 return target_read_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
759 }
760
761 static inline int stm32l4_read_flash_reg_by_index(struct flash_bank *bank,
762 enum stm32l4_flash_reg_index reg_index, uint32_t *value)
763 {
764 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
765 return stm32l4_read_flash_reg(bank, stm32l4_info->flash_regs[reg_index], value);
766 }
767
768 static inline int stm32l4_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
769 {
770 return target_write_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
771 }
772
773 static inline int stm32l4_write_flash_reg_by_index(struct flash_bank *bank,
774 enum stm32l4_flash_reg_index reg_index, uint32_t value)
775 {
776 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
777 return stm32l4_write_flash_reg(bank, stm32l4_info->flash_regs[reg_index], value);
778 }
779
780 static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
781 {
782 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
783 uint32_t status;
784 int retval = ERROR_OK;
785
786 /* wait for busy to clear */
787 for (;;) {
788 retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, &status);
789 if (retval != ERROR_OK)
790 return retval;
791 LOG_DEBUG("status: 0x%" PRIx32 "", status);
792 if ((status & stm32l4_info->sr_bsy_mask) == 0)
793 break;
794 if (timeout-- <= 0) {
795 LOG_ERROR("timed out waiting for flash");
796 return ERROR_FAIL;
797 }
798 alive_sleep(1);
799 }
800
801 if (status & FLASH_WRPERR) {
802 LOG_ERROR("stm32x device protected");
803 retval = ERROR_FAIL;
804 }
805
806 /* Clear but report errors */
807 if (status & FLASH_ERROR) {
808 if (retval == ERROR_OK)
809 retval = ERROR_FAIL;
810 /* If this operation fails, we ignore it and report the original
811 * retval
812 */
813 stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, status & FLASH_ERROR);
814 }
815
816 return retval;
817 }
818
819 /** set all FLASH_SECBB registers to the same value */
820 static int stm32l4_set_secbb(struct flash_bank *bank, uint32_t value)
821 {
822 /* This function should be used only with device with TrustZone, do just a security check */
823 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
824 assert(stm32l4_info->part_info->flags & F_HAS_TZ);
825
826 /* based on RM0438 Rev6 for STM32L5x devices:
827 * to modify a page block-based security attribution, it is recommended to
828 * 1- check that no flash operation is ongoing on the related page
829 * 2- add ISB instruction after modifying the page security attribute in SECBBxRy
830 * this step is not need in case of JTAG direct access
831 */
832 int retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
833 if (retval != ERROR_OK)
834 return retval;
835
836 /* write SECBBxRy registers */
837 LOG_DEBUG("setting secure block-based areas registers (SECBBxRy) to 0x%08x", value);
838
839 const uint8_t secbb_regs[] = {
840 FLASH_SECBB1(1), FLASH_SECBB1(2), FLASH_SECBB1(3), FLASH_SECBB1(4), /* bank 1 SECBB register offsets */
841 FLASH_SECBB2(1), FLASH_SECBB2(2), FLASH_SECBB2(3), FLASH_SECBB2(4) /* bank 2 SECBB register offsets */
842 };
843
844
845 unsigned int num_secbb_regs = ARRAY_SIZE(secbb_regs);
846
847 /* in single bank mode, it's useless to modify FLASH_SECBB2Rx registers
848 * then consider only the first half of secbb_regs
849 */
850 if (!stm32l4_info->dual_bank_mode)
851 num_secbb_regs /= 2;
852
853 for (unsigned int i = 0; i < num_secbb_regs; i++) {
854 retval = stm32l4_write_flash_reg(bank, secbb_regs[i], value);
855 if (retval != ERROR_OK)
856 return retval;
857 }
858
859 return ERROR_OK;
860 }
861
862 static inline int stm32l4_get_flash_cr_with_lock_index(struct flash_bank *bank)
863 {
864 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
865 return (stm32l4_info->flash_regs[STM32_FLASH_CR_WLK_INDEX]) ?
866 STM32_FLASH_CR_WLK_INDEX : STM32_FLASH_CR_INDEX;
867 }
868
869 static int stm32l4_unlock_reg(struct flash_bank *bank)
870 {
871 const uint32_t flash_cr_index = stm32l4_get_flash_cr_with_lock_index(bank);
872 uint32_t ctrl;
873
874 /* first check if not already unlocked
875 * otherwise writing on STM32_FLASH_KEYR will fail
876 */
877 int retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
878 if (retval != ERROR_OK)
879 return retval;
880
881 if ((ctrl & FLASH_LOCK) == 0)
882 return ERROR_OK;
883
884 /* unlock flash registers */
885 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_KEYR_INDEX, KEY1);
886 if (retval != ERROR_OK)
887 return retval;
888
889 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_KEYR_INDEX, KEY2);
890 if (retval != ERROR_OK)
891 return retval;
892
893 retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
894 if (retval != ERROR_OK)
895 return retval;
896
897 if (ctrl & FLASH_LOCK) {
898 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
899 return ERROR_TARGET_FAILURE;
900 }
901
902 return ERROR_OK;
903 }
904
905 static int stm32l4_unlock_option_reg(struct flash_bank *bank)
906 {
907 const uint32_t flash_cr_index = stm32l4_get_flash_cr_with_lock_index(bank);
908 uint32_t ctrl;
909
910 int retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
911 if (retval != ERROR_OK)
912 return retval;
913
914 if ((ctrl & FLASH_OPTLOCK) == 0)
915 return ERROR_OK;
916
917 /* unlock option registers */
918 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_OPTKEYR_INDEX, OPTKEY1);
919 if (retval != ERROR_OK)
920 return retval;
921
922 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_OPTKEYR_INDEX, OPTKEY2);
923 if (retval != ERROR_OK)
924 return retval;
925
926 retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
927 if (retval != ERROR_OK)
928 return retval;
929
930 if (ctrl & FLASH_OPTLOCK) {
931 LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
932 return ERROR_TARGET_FAILURE;
933 }
934
935 return ERROR_OK;
936 }
937
938 static int stm32l4_perform_obl_launch(struct flash_bank *bank)
939 {
940 int retval, retval2;
941
942 retval = stm32l4_unlock_reg(bank);
943 if (retval != ERROR_OK)
944 goto err_lock;
945
946 retval = stm32l4_unlock_option_reg(bank);
947 if (retval != ERROR_OK)
948 goto err_lock;
949
950 /* Set OBL_LAUNCH bit in CR -> system reset and option bytes reload,
951 * but the RMs explicitly do *NOT* list this as power-on reset cause, and:
952 * "Note: If the read protection is set while the debugger is still
953 * connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset."
954 */
955
956 /* "Setting OBL_LAUNCH generates a reset so the option byte loading is performed under system reset" */
957 /* Due to this reset ST-Link reports an SWD_DP_ERROR, despite the write was successful,
958 * then just ignore the returned value */
959 stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_OBL_LAUNCH);
960
961 /* Need to re-probe after change */
962 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
963 stm32l4_info->probed = false;
964
965 err_lock:
966 retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank),
967 FLASH_LOCK | FLASH_OPTLOCK);
968
969 if (retval != ERROR_OK)
970 return retval;
971
972 return retval2;
973 }
974
975 static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset,
976 uint32_t value, uint32_t mask)
977 {
978 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
979 uint32_t optiondata;
980 int retval, retval2;
981
982 retval = stm32l4_read_flash_reg(bank, reg_offset, &optiondata);
983 if (retval != ERROR_OK)
984 return retval;
985
986 /* for STM32L5 and similar devices, use always non-secure
987 * registers for option bytes programming */
988 const uint32_t *saved_flash_regs = stm32l4_info->flash_regs;
989 if (stm32l4_info->part_info->flags & F_HAS_L5_FLASH_REGS)
990 stm32l4_info->flash_regs = stm32l5_ns_flash_regs;
991
992 retval = stm32l4_unlock_reg(bank);
993 if (retval != ERROR_OK)
994 goto err_lock;
995
996 retval = stm32l4_unlock_option_reg(bank);
997 if (retval != ERROR_OK)
998 goto err_lock;
999
1000 optiondata = (optiondata & ~mask) | (value & mask);
1001
1002 retval = stm32l4_write_flash_reg(bank, reg_offset, optiondata);
1003 if (retval != ERROR_OK)
1004 goto err_lock;
1005
1006 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_OPTSTRT);
1007 if (retval != ERROR_OK)
1008 goto err_lock;
1009
1010 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1011
1012 err_lock:
1013 retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank),
1014 FLASH_LOCK | FLASH_OPTLOCK);
1015 stm32l4_info->flash_regs = saved_flash_regs;
1016
1017 if (retval != ERROR_OK)
1018 return retval;
1019
1020 return retval2;
1021 }
1022
1023 static int stm32l4_get_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy,
1024 enum stm32l4_flash_reg_index reg_idx, int offset)
1025 {
1026 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1027 int ret;
1028
1029 wrpxy->reg_idx = reg_idx;
1030 wrpxy->offset = offset;
1031
1032 ret = stm32l4_read_flash_reg_by_index(bank, wrpxy->reg_idx , &wrpxy->value);
1033 if (ret != ERROR_OK)
1034 return ret;
1035
1036 wrpxy->first = (wrpxy->value & stm32l4_info->wrpxxr_mask) + wrpxy->offset;
1037 wrpxy->last = ((wrpxy->value >> 16) & stm32l4_info->wrpxxr_mask) + wrpxy->offset;
1038 wrpxy->used = wrpxy->first <= wrpxy->last;
1039
1040 return ERROR_OK;
1041 }
1042
1043 static int stm32l4_get_all_wrpxy(struct flash_bank *bank, enum stm32_bank_id dev_bank_id,
1044 struct stm32l4_wrp *wrpxy, unsigned int *n_wrp)
1045 {
1046 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1047 int ret;
1048
1049 *n_wrp = 0;
1050
1051 /* for single bank devices there is 2 WRP regions.
1052 * for dual bank devices there is 2 WRP regions per bank,
1053 * if configured as single bank only 2 WRP are usable
1054 * except for STM32L4R/S/P/Q, G4 cat3, L5 ... all 4 WRP are usable
1055 * note: this should be revised, if a device will have the SWAP banks option
1056 */
1057
1058 int wrp2y_sectors_offset = -1; /* -1 : unused */
1059
1060 /* if bank_id is BANK1 or ALL_BANKS */
1061 if (dev_bank_id != STM32_BANK2) {
1062 /* get FLASH_WRP1AR */
1063 ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP1AR_INDEX, 0);
1064 if (ret != ERROR_OK)
1065 return ret;
1066
1067 /* get WRP1BR */
1068 ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP1BR_INDEX, 0);
1069 if (ret != ERROR_OK)
1070 return ret;
1071
1072 /* for some devices (like STM32L4R/S) in single-bank mode, the 4 WRPxx are usable */
1073 if ((stm32l4_info->part_info->flags & F_USE_ALL_WRPXX) && !stm32l4_info->dual_bank_mode)
1074 wrp2y_sectors_offset = 0;
1075 }
1076
1077 /* if bank_id is BANK2 or ALL_BANKS */
1078 if (dev_bank_id != STM32_BANK1 && stm32l4_info->dual_bank_mode)
1079 wrp2y_sectors_offset = stm32l4_info->bank1_sectors;
1080
1081 if (wrp2y_sectors_offset > -1) {
1082 /* get WRP2AR */
1083 ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP2AR_INDEX, wrp2y_sectors_offset);
1084 if (ret != ERROR_OK)
1085 return ret;
1086
1087 /* get WRP2BR */
1088 ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP2BR_INDEX, wrp2y_sectors_offset);
1089 if (ret != ERROR_OK)
1090 return ret;
1091 }
1092
1093 return ERROR_OK;
1094 }
1095
1096 static int stm32l4_write_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy)
1097 {
1098 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1099
1100 int wrp_start = wrpxy->first - wrpxy->offset;
1101 int wrp_end = wrpxy->last - wrpxy->offset;
1102
1103 uint32_t wrp_value = (wrp_start & stm32l4_info->wrpxxr_mask) | ((wrp_end & stm32l4_info->wrpxxr_mask) << 16);
1104
1105 return stm32l4_write_option(bank, stm32l4_info->flash_regs[wrpxy->reg_idx], wrp_value, 0xffffffff);
1106 }
1107
1108 static int stm32l4_write_all_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy, unsigned int n_wrp)
1109 {
1110 int ret;
1111
1112 for (unsigned int i = 0; i < n_wrp; i++) {
1113 ret = stm32l4_write_one_wrpxy(bank, &wrpxy[i]);
1114 if (ret != ERROR_OK)
1115 return ret;
1116 }
1117
1118 return ERROR_OK;
1119 }
1120
1121 static int stm32l4_protect_check(struct flash_bank *bank)
1122 {
1123 unsigned int n_wrp;
1124 struct stm32l4_wrp wrpxy[4];
1125
1126 int ret = stm32l4_get_all_wrpxy(bank, STM32_ALL_BANKS, wrpxy, &n_wrp);
1127 if (ret != ERROR_OK)
1128 return ret;
1129
1130 /* initialize all sectors as unprotected */
1131 for (unsigned int i = 0; i < bank->num_sectors; i++)
1132 bank->sectors[i].is_protected = 0;
1133
1134 /* now check WRPxy and mark the protected sectors */
1135 for (unsigned int i = 0; i < n_wrp; i++) {
1136 if (wrpxy[i].used) {
1137 for (int s = wrpxy[i].first; s <= wrpxy[i].last; s++)
1138 bank->sectors[s].is_protected = 1;
1139 }
1140 }
1141
1142 return ERROR_OK;
1143 }
1144
1145 static int stm32l4_erase(struct flash_bank *bank, unsigned int first,
1146 unsigned int last)
1147 {
1148 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1149 int retval, retval2;
1150
1151 assert((first <= last) && (last < bank->num_sectors));
1152
1153 if (stm32l4_is_otp(bank)) {
1154 LOG_ERROR("cannot erase OTP memory");
1155 return ERROR_FLASH_OPER_UNSUPPORTED;
1156 }
1157
1158 if (bank->target->state != TARGET_HALTED) {
1159 LOG_ERROR("Target not halted");
1160 return ERROR_TARGET_NOT_HALTED;
1161 }
1162
1163 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1164 /* set all FLASH pages as secure */
1165 retval = stm32l4_set_secbb(bank, FLASH_SECBB_SECURE);
1166 if (retval != ERROR_OK) {
1167 /* restore all FLASH pages as non-secure */
1168 stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
1169 return retval;
1170 }
1171 }
1172
1173 retval = stm32l4_unlock_reg(bank);
1174 if (retval != ERROR_OK)
1175 goto err_lock;
1176
1177 /*
1178 Sector Erase
1179 To erase a sector, follow the procedure below:
1180 1. Check that no Flash memory operation is ongoing by
1181 checking the BSY bit in the FLASH_SR register
1182 2. Set the PER bit and select the page and bank
1183 you wish to erase in the FLASH_CR register
1184 3. Set the STRT bit in the FLASH_CR register
1185 4. Wait for the BSY bit to be cleared
1186 */
1187
1188 for (unsigned int i = first; i <= last; i++) {
1189 uint32_t erase_flags;
1190 erase_flags = FLASH_PER | FLASH_STRT;
1191
1192 if (i >= stm32l4_info->bank1_sectors) {
1193 uint8_t snb;
1194 snb = i - stm32l4_info->bank1_sectors;
1195 erase_flags |= snb << FLASH_PAGE_SHIFT | stm32l4_info->cr_bker_mask;
1196 } else
1197 erase_flags |= i << FLASH_PAGE_SHIFT;
1198 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, erase_flags);
1199 if (retval != ERROR_OK)
1200 break;
1201
1202 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1203 if (retval != ERROR_OK)
1204 break;
1205 }
1206
1207 err_lock:
1208 retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank), FLASH_LOCK);
1209
1210 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1211 /* restore all FLASH pages as non-secure */
1212 int retval3 = stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE);
1213 if (retval3 != ERROR_OK)
1214 return retval3;
1215 }
1216
1217 if (retval != ERROR_OK)
1218 return retval;
1219
1220 return retval2;
1221 }
1222
1223 static int stm32l4_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
1224 {
1225 struct target *target = bank->target;
1226 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1227 int ret = ERROR_OK;
1228 unsigned int i;
1229
1230 if (stm32l4_is_otp(bank)) {
1231 LOG_ERROR("cannot protect/unprotect OTP memory");
1232 return ERROR_FLASH_OPER_UNSUPPORTED;
1233 }
1234
1235 if (target->state != TARGET_HALTED) {
1236 LOG_ERROR("Target not halted");
1237 return ERROR_TARGET_NOT_HALTED;
1238 }
1239
1240 /* the requested sectors could be located into bank1 and/or bank2 */
1241 bool use_bank2 = false;
1242 if (last >= stm32l4_info->bank1_sectors) {
1243 if (first < stm32l4_info->bank1_sectors) {
1244 /* the requested sectors for (un)protection are shared between
1245 * bank 1 and 2, then split the operation */
1246
1247 /* 1- deal with bank 1 sectors */
1248 LOG_DEBUG("The requested sectors for %s are shared between bank 1 and 2",
1249 set ? "protection" : "unprotection");
1250 ret = stm32l4_protect(bank, set, first, stm32l4_info->bank1_sectors - 1);
1251 if (ret != ERROR_OK)
1252 return ret;
1253
1254 /* 2- then continue with bank 2 sectors */
1255 first = stm32l4_info->bank1_sectors;
1256 }
1257
1258 use_bank2 = true;
1259 }
1260
1261 /* refresh the sectors' protection */
1262 ret = stm32l4_protect_check(bank);
1263 if (ret != ERROR_OK)
1264 return ret;
1265
1266 /* check if the desired protection is already configured */
1267 for (i = first; i <= last; i++) {
1268 if (bank->sectors[i].is_protected != set)
1269 break;
1270 else if (i == last) {
1271 LOG_INFO("The specified sectors are already %s", set ? "protected" : "unprotected");
1272 return ERROR_OK;
1273 }
1274 }
1275
1276 /* all sectors from first to last (or part of them) could have different
1277 * protection other than the requested */
1278 unsigned int n_wrp;
1279 struct stm32l4_wrp wrpxy[4];
1280
1281 ret = stm32l4_get_all_wrpxy(bank, use_bank2 ? STM32_BANK2 : STM32_BANK1, wrpxy, &n_wrp);
1282 if (ret != ERROR_OK)
1283 return ret;
1284
1285 /* use bitmap and range helpers to optimize the WRP usage */
1286 DECLARE_BITMAP(pages, bank->num_sectors);
1287 bitmap_zero(pages, bank->num_sectors);
1288
1289 for (i = 0; i < n_wrp; i++) {
1290 if (wrpxy[i].used) {
1291 for (int p = wrpxy[i].first; p <= wrpxy[i].last; p++)
1292 set_bit(p, pages);
1293 }
1294 }
1295
1296 /* we have at most 'n_wrp' WRP areas
1297 * add one range if the user is trying to protect a fifth range */
1298 struct range ranges[n_wrp + 1];
1299 unsigned int ranges_count = 0;
1300
1301 bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count);
1302
1303 /* pretty-print the currently protected ranges */
1304 if (ranges_count > 0) {
1305 char *ranges_str = range_print_alloc(ranges, ranges_count);
1306 LOG_DEBUG("current protected areas: %s", ranges_str);
1307 free(ranges_str);
1308 } else
1309 LOG_DEBUG("current protected areas: none");
1310
1311 if (set) { /* flash protect */
1312 for (i = first; i <= last; i++)
1313 set_bit(i, pages);
1314 } else { /* flash unprotect */
1315 for (i = first; i <= last; i++)
1316 clear_bit(i, pages);
1317 }
1318
1319 /* check the ranges_count after the user request */
1320 bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count);
1321
1322 /* pretty-print the requested areas for protection */
1323 if (ranges_count > 0) {
1324 char *ranges_str = range_print_alloc(ranges, ranges_count);
1325 LOG_DEBUG("requested areas for protection: %s", ranges_str);
1326 free(ranges_str);
1327 } else
1328 LOG_DEBUG("requested areas for protection: none");
1329
1330 if (ranges_count > n_wrp) {
1331 LOG_ERROR("cannot set the requested protection "
1332 "(only %u write protection areas are available)" , n_wrp);
1333 return ERROR_FAIL;
1334 }
1335
1336 /* re-init all WRPxy as disabled (first > last)*/
1337 for (i = 0; i < n_wrp; i++) {
1338 wrpxy[i].first = wrpxy[i].offset + 1;
1339 wrpxy[i].last = wrpxy[i].offset;
1340 }
1341
1342 /* then configure WRPxy areas */
1343 for (i = 0; i < ranges_count; i++) {
1344 wrpxy[i].first = ranges[i].start;
1345 wrpxy[i].last = ranges[i].end;
1346 }
1347
1348 /* finally write WRPxy registers */
1349 return stm32l4_write_all_wrpxy(bank, wrpxy, n_wrp);
1350 }
1351
1352 /* count is the size divided by stm32l4_info->data_width */
1353 static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
1354 uint32_t offset, uint32_t count)
1355 {
1356 struct target *target = bank->target;
1357 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1358 struct working_area *write_algorithm;
1359 struct working_area *source;
1360 uint32_t address = bank->base + offset;
1361 struct reg_param reg_params[5];
1362 struct armv7m_algorithm armv7m_info;
1363 int retval = ERROR_OK;
1364
1365 static const uint8_t stm32l4_flash_write_code[] = {
1366 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
1367 };
1368
1369 if (target_alloc_working_area(target, sizeof(stm32l4_flash_write_code),
1370 &write_algorithm) != ERROR_OK) {
1371 LOG_WARNING("no working area available, can't do block memory writes");
1372 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1373 }
1374
1375 retval = target_write_buffer(target, write_algorithm->address,
1376 sizeof(stm32l4_flash_write_code),
1377 stm32l4_flash_write_code);
1378 if (retval != ERROR_OK) {
1379 target_free_working_area(target, write_algorithm);
1380 return retval;
1381 }
1382
1383 /* data_width should be multiple of double-word */
1384 assert(stm32l4_info->data_width % 8 == 0);
1385 const size_t extra_size = sizeof(struct stm32l4_work_area);
1386 uint32_t buffer_size = target_get_working_area_avail(target) - extra_size;
1387 /* buffer_size should be multiple of stm32l4_info->data_width */
1388 buffer_size &= ~(stm32l4_info->data_width - 1);
1389
1390 if (buffer_size < 256) {
1391 LOG_WARNING("large enough working area not available, can't do block memory writes");
1392 target_free_working_area(target, write_algorithm);
1393 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1394 } else if (buffer_size > 16384) {
1395 /* probably won't benefit from more than 16k ... */
1396 buffer_size = 16384;
1397 }
1398
1399 if (target_alloc_working_area_try(target, buffer_size + extra_size, &source) != ERROR_OK) {
1400 LOG_ERROR("allocating working area failed");
1401 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1402 }
1403
1404 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
1405 armv7m_info.core_mode = ARM_MODE_THREAD;
1406
1407 /* contrib/loaders/flash/stm32/stm32l4x.c:write() arguments */
1408 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* stm32l4_work_area ptr , status (out) */
1409 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* buffer end */
1410 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* target address */
1411 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* count (of stm32l4_info->data_width) */
1412
1413 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1414 buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
1415 buf_set_u32(reg_params[2].value, 0, 32, address);
1416 buf_set_u32(reg_params[3].value, 0, 32, count);
1417
1418 /* write algo stack pointer */
1419 init_reg_param(&reg_params[4], "sp", 32, PARAM_OUT);
1420 buf_set_u32(reg_params[4].value, 0, 32, source->address +
1421 offsetof(struct stm32l4_work_area, stack) + LDR_STACK_SIZE);
1422
1423 struct stm32l4_loader_params loader_extra_params;
1424
1425 target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_sr_addr,
1426 stm32l4_get_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX));
1427 target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_cr_addr,
1428 stm32l4_get_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX));
1429 target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_word_size,
1430 stm32l4_info->data_width);
1431 target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_sr_bsy_mask,
1432 stm32l4_info->sr_bsy_mask);
1433
1434 retval = target_write_buffer(target, source->address, sizeof(loader_extra_params),
1435 (uint8_t *) &loader_extra_params);
1436 if (retval != ERROR_OK)
1437 return retval;
1438
1439 retval = target_run_flash_async_algorithm(target, buffer, count, stm32l4_info->data_width,
1440 0, NULL,
1441 ARRAY_SIZE(reg_params), reg_params,
1442 source->address + offsetof(struct stm32l4_work_area, fifo),
1443 source->size - offsetof(struct stm32l4_work_area, fifo),
1444 write_algorithm->address, 0,
1445 &armv7m_info);
1446
1447 if (retval == ERROR_FLASH_OPERATION_FAILED) {
1448 LOG_ERROR("error executing stm32l4 flash write algorithm");
1449
1450 uint32_t error;
1451 stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, &error);
1452 error &= FLASH_ERROR;
1453
1454 if (error & FLASH_WRPERR)
1455 LOG_ERROR("flash memory write protected");
1456
1457 if (error != 0) {
1458 LOG_ERROR("flash write failed = %08" PRIx32, error);
1459 /* Clear but report errors */
1460 stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, error);
1461 retval = ERROR_FAIL;
1462 }
1463 }
1464
1465 target_free_working_area(target, source);
1466 target_free_working_area(target, write_algorithm);
1467
1468 destroy_reg_param(&reg_params[0]);
1469 destroy_reg_param(&reg_params[1]);
1470 destroy_reg_param(&reg_params[2]);
1471 destroy_reg_param(&reg_params[3]);
1472 destroy_reg_param(&reg_params[4]);
1473
1474 return retval;
1475 }
1476
1477 /* count is the size divided by stm32l4_info->data_width */
1478 static int stm32l4_write_block_without_loader(struct flash_bank *bank, const uint8_t *buffer,
1479 uint32_t offset, uint32_t count)
1480 {
1481 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1482 struct target *target = bank->target;
1483 uint32_t address = bank->base + offset;
1484 int retval = ERROR_OK;
1485
1486 /* wait for BSY bit */
1487 retval = stm32l4_wait_status_busy(bank, FLASH_WRITE_TIMEOUT);
1488 if (retval != ERROR_OK)
1489 return retval;
1490
1491 /* set PG in FLASH_CR */
1492 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_PG);
1493 if (retval != ERROR_OK)
1494 return retval;
1495
1496
1497 /* write directly to flash memory */
1498 const uint8_t *src = buffer;
1499 const uint32_t data_width_in_words = stm32l4_info->data_width / 4;
1500 while (count--) {
1501 retval = target_write_memory(target, address, 4, data_width_in_words, src);
1502 if (retval != ERROR_OK)
1503 return retval;
1504
1505 /* wait for BSY bit */
1506 retval = stm32l4_wait_status_busy(bank, FLASH_WRITE_TIMEOUT);
1507 if (retval != ERROR_OK)
1508 return retval;
1509
1510 src += stm32l4_info->data_width;
1511 address += stm32l4_info->data_width;
1512 }
1513
1514 /* reset PG in FLASH_CR */
1515 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, 0);
1516 if (retval != ERROR_OK)
1517 return retval;
1518
1519 return retval;
1520 }
1521
1522 static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
1523 uint32_t offset, uint32_t count)
1524 {
1525 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1526 int retval = ERROR_OK, retval2;
1527
1528 if (stm32l4_is_otp(bank) && !stm32l4_otp_is_enabled(bank)) {
1529 LOG_ERROR("OTP memory is disabled for write commands");
1530 return ERROR_FAIL;
1531 }
1532
1533 if (bank->target->state != TARGET_HALTED) {
1534 LOG_ERROR("Target not halted");
1535 return ERROR_TARGET_NOT_HALTED;
1536 }
1537
1538 /* ensure that stm32l4_info->data_width is 'at least' a multiple of dword */
1539 assert(stm32l4_info->data_width % 8 == 0);
1540
1541 /* The flash write must be aligned to the 'stm32l4_info->data_width' boundary.
1542 * The flash infrastructure ensures it, do just a security check */
1543 assert(offset % stm32l4_info->data_width == 0);
1544 assert(count % stm32l4_info->data_width == 0);
1545
1546 /* STM32G4xxx Cat. 3 devices may have gaps between banks, check whether
1547 * data to be written does not go into a gap:
1548 * suppose buffer is fully contained in bank from sector 0 to sector
1549 * num->sectors - 1 and sectors are ordered according to offset
1550 */
1551 struct flash_sector *head = &bank->sectors[0];
1552 struct flash_sector *tail = &bank->sectors[bank->num_sectors - 1];
1553
1554 while ((head < tail) && (offset >= (head + 1)->offset)) {
1555 /* buffer does not intersect head nor gap behind head */
1556 head++;
1557 }
1558
1559 while ((head < tail) && (offset + count <= (tail - 1)->offset + (tail - 1)->size)) {
1560 /* buffer does not intersect tail nor gap before tail */
1561 --tail;
1562 }
1563
1564 LOG_DEBUG("data: 0x%08" PRIx32 " - 0x%08" PRIx32 ", sectors: 0x%08" PRIx32 " - 0x%08" PRIx32,
1565 offset, offset + count - 1, head->offset, tail->offset + tail->size - 1);
1566
1567 /* Now check that there is no gap from head to tail, this should work
1568 * even for multiple or non-symmetric gaps
1569 */
1570 while (head < tail) {
1571 if (head->offset + head->size != (head + 1)->offset) {
1572 LOG_ERROR("write into gap from " TARGET_ADDR_FMT " to " TARGET_ADDR_FMT,
1573 bank->base + head->offset + head->size,
1574 bank->base + (head + 1)->offset - 1);
1575 retval = ERROR_FLASH_DST_OUT_OF_BANK;
1576 }
1577 head++;
1578 }
1579
1580 if (retval != ERROR_OK)
1581 return retval;
1582
1583 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1584 /* set all FLASH pages as secure */
1585 retval = stm32l4_set_secbb(bank, FLASH_SECBB_SECURE);
1586 if (retval != ERROR_OK) {
1587 /* restore all FLASH pages as non-secure */
1588 stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
1589 return retval;
1590 }
1591 }
1592
1593 retval = stm32l4_unlock_reg(bank);
1594 if (retval != ERROR_OK)
1595 goto err_lock;
1596
1597
1598 /* For TrustZone enabled devices, when TZEN is set and RDP level is 0.5,
1599 * the debug is possible only in non-secure state.
1600 * Thus means the flashloader will run in non-secure mode,
1601 * and the workarea need to be in non-secure RAM */
1602 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0_5))
1603 LOG_WARNING("RDP = 0x55, the work-area should be in non-secure RAM (check SAU partitioning)");
1604
1605 /* first try to write using the loader, for better performance */
1606 retval = stm32l4_write_block(bank, buffer, offset,
1607 count / stm32l4_info->data_width);
1608
1609 /* if resources are not available write without a loader */
1610 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
1611 LOG_WARNING("falling back to programming without a flash loader (slower)");
1612 retval = stm32l4_write_block_without_loader(bank, buffer, offset,
1613 count / stm32l4_info->data_width);
1614 }
1615
1616 err_lock:
1617 retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank), FLASH_LOCK);
1618
1619 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1620 /* restore all FLASH pages as non-secure */
1621 int retval3 = stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE);
1622 if (retval3 != ERROR_OK)
1623 return retval3;
1624 }
1625
1626 if (retval != ERROR_OK) {
1627 LOG_ERROR("block write failed");
1628 return retval;
1629 }
1630 return retval2;
1631 }
1632
1633 static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
1634 {
1635 int retval;
1636
1637 /* try reading possible IDCODE registers, in the following order */
1638 uint32_t dbgmcu_idcode[] = {DBGMCU_IDCODE_L4_G4, DBGMCU_IDCODE_G0, DBGMCU_IDCODE_L5};
1639
1640 for (unsigned int i = 0; i < ARRAY_SIZE(dbgmcu_idcode); i++) {
1641 retval = target_read_u32(bank->target, dbgmcu_idcode[i], id);
1642 if ((retval == ERROR_OK) && ((*id & 0xfff) != 0) && ((*id & 0xfff) != 0xfff))
1643 return ERROR_OK;
1644 }
1645
1646 /* Workaround for STM32WL5x devices:
1647 * DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1,
1648 * to solve this read the UID64 (IEEE 64-bit unique device ID register) */
1649
1650 struct cortex_m_common *cortex_m = target_to_cm(bank->target);
1651
1652 /* CPU2 (Cortex-M0+) is supported only with non-hla adapters because it is on AP1.
1653 * Using HLA adapters armv7m.debug_ap is null, and checking ap_num triggers a segfault */
1654 if (cortex_m->core_info->partno == CORTEX_M0P_PARTNO &&
1655 cortex_m->armv7m.debug_ap && cortex_m->armv7m.debug_ap->ap_num == 1) {
1656 uint32_t uid64_ids;
1657
1658 /* UID64 is contains
1659 * - Bits 63:32 : DEVNUM (unique device number, different for each individual device)
1660 * - Bits 31:08 : STID (company ID) = 0x0080E1
1661 * - Bits 07:00 : DEVID (device ID) = 0x15
1662 *
1663 * read only the fixed values {STID,DEVID} from UID64_IDS to identify the device as STM32WLx
1664 */
1665 retval = target_read_u32(bank->target, UID64_IDS, &uid64_ids);
1666 if (retval == ERROR_OK && uid64_ids == UID64_IDS_STM32WL) {
1667 /* force the DEV_ID to DEVID_STM32WLE_WL5XX and the REV_ID to unknown */
1668 *id = DEVID_STM32WLE_WL5XX;
1669 return ERROR_OK;
1670 }
1671 }
1672
1673 LOG_ERROR("can't get the device id");
1674 return (retval == ERROR_OK) ? ERROR_FAIL : retval;
1675 }
1676
1677 static const char *get_stm32l4_rev_str(struct flash_bank *bank)
1678 {
1679 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1680 const struct stm32l4_part_info *part_info = stm32l4_info->part_info;
1681 assert(part_info);
1682
1683 const uint16_t rev_id = stm32l4_info->idcode >> 16;
1684 for (unsigned int i = 0; i < part_info->num_revs; i++) {
1685 if (rev_id == part_info->revs[i].rev)
1686 return part_info->revs[i].str;
1687 }
1688 return "'unknown'";
1689 }
1690
1691 static const char *get_stm32l4_bank_type_str(struct flash_bank *bank)
1692 {
1693 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1694 assert(stm32l4_info->part_info);
1695 return stm32l4_is_otp(bank) ? "OTP" :
1696 stm32l4_info->dual_bank_mode ? "Flash dual" :
1697 "Flash single";
1698 }
1699
1700 static int stm32l4_probe(struct flash_bank *bank)
1701 {
1702 struct target *target = bank->target;
1703 struct armv7m_common *armv7m = target_to_armv7m(target);
1704 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1705 const struct stm32l4_part_info *part_info;
1706 uint16_t flash_size_kb = 0xffff;
1707
1708 stm32l4_info->probed = false;
1709
1710 /* read stm32 device id registers */
1711 int retval = stm32l4_read_idcode(bank, &stm32l4_info->idcode);
1712 if (retval != ERROR_OK)
1713 return retval;
1714
1715 const uint32_t device_id = stm32l4_info->idcode & 0xFFF;
1716
1717 for (unsigned int n = 0; n < ARRAY_SIZE(stm32l4_parts); n++) {
1718 if (device_id == stm32l4_parts[n].id) {
1719 stm32l4_info->part_info = &stm32l4_parts[n];
1720 break;
1721 }
1722 }
1723
1724 if (!stm32l4_info->part_info) {
1725 LOG_WARNING("Cannot identify target as an %s family device.", device_families);
1726 return ERROR_FAIL;
1727 }
1728
1729 part_info = stm32l4_info->part_info;
1730 const char *rev_str = get_stm32l4_rev_str(bank);
1731 const uint16_t rev_id = stm32l4_info->idcode >> 16;
1732
1733 LOG_INFO("device idcode = 0x%08" PRIx32 " (%s - Rev %s : 0x%04x)",
1734 stm32l4_info->idcode, part_info->device_str, rev_str, rev_id);
1735
1736 stm32l4_info->flash_regs_base = stm32l4_info->part_info->flash_regs_base;
1737 stm32l4_info->data_width = (part_info->flags & F_QUAD_WORD_PROG) ? 16 : 8;
1738 stm32l4_info->cr_bker_mask = FLASH_BKER;
1739 stm32l4_info->sr_bsy_mask = FLASH_BSY;
1740
1741 /* Set flash write alignment boundaries.
1742 * Ask the flash infrastructure to ensure required alignment */
1743 bank->write_start_alignment = bank->write_end_alignment = stm32l4_info->data_width;
1744
1745 /* initialise the flash registers layout */
1746 if (part_info->flags & F_HAS_L5_FLASH_REGS)
1747 stm32l4_info->flash_regs = stm32l5_ns_flash_regs;
1748 else
1749 stm32l4_info->flash_regs = stm32l4_flash_regs;
1750
1751 /* read flash option register */
1752 retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &stm32l4_info->optr);
1753 if (retval != ERROR_OK)
1754 return retval;
1755
1756 stm32l4_sync_rdp_tzen(bank);
1757
1758 /* for devices with trustzone, use flash secure registers when TZEN=1 and RDP is LEVEL_0 */
1759 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1760 if (part_info->flags & F_HAS_L5_FLASH_REGS) {
1761 stm32l4_info->flash_regs_base |= STM32L5_REGS_SEC_OFFSET;
1762 stm32l4_info->flash_regs = stm32l5_s_flash_regs;
1763 } else {
1764 LOG_ERROR("BUG: device supported incomplete");
1765 return ERROR_NOT_IMPLEMENTED;
1766 }
1767 }
1768
1769 if (part_info->flags & F_HAS_TZ)
1770 LOG_INFO("TZEN = %d : TrustZone %s by option bytes",
1771 stm32l4_info->tzen,
1772 stm32l4_info->tzen ? "enabled" : "disabled");
1773
1774 LOG_INFO("RDP level %s (0x%02X)",
1775 stm32l4_info->rdp == RDP_LEVEL_0 ? "0" : stm32l4_info->rdp == RDP_LEVEL_0_5 ? "0.5" : "1",
1776 stm32l4_info->rdp);
1777
1778 if (stm32l4_is_otp(bank)) {
1779 bank->size = part_info->otp_size;
1780
1781 LOG_INFO("OTP size is %d bytes, base address is " TARGET_ADDR_FMT, bank->size, bank->base);
1782
1783 /* OTP memory is considered as one sector */
1784 free(bank->sectors);
1785 bank->num_sectors = 1;
1786 bank->sectors = alloc_block_array(0, part_info->otp_size, 1);
1787
1788 if (!bank->sectors) {
1789 LOG_ERROR("failed to allocate bank sectors");
1790 return ERROR_FAIL;
1791 }
1792
1793 stm32l4_info->probed = true;
1794 return ERROR_OK;
1795 } else if (bank->base != STM32_FLASH_BANK_BASE && bank->base != STM32_FLASH_S_BANK_BASE) {
1796 LOG_ERROR("invalid bank base address");
1797 return ERROR_FAIL;
1798 }
1799
1800 /* get flash size from target. */
1801 retval = target_read_u16(target, part_info->fsize_addr, &flash_size_kb);
1802
1803 /* failed reading flash size or flash size invalid (early silicon),
1804 * default to max target family */
1805 if (retval != ERROR_OK || flash_size_kb == 0xffff || flash_size_kb == 0
1806 || flash_size_kb > part_info->max_flash_size_kb) {
1807 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
1808 part_info->max_flash_size_kb);
1809 flash_size_kb = part_info->max_flash_size_kb;
1810 }
1811
1812 /* if the user sets the size manually then ignore the probed value
1813 * this allows us to work around devices that have a invalid flash size register value */
1814 if (stm32l4_info->user_bank_size) {
1815 LOG_WARNING("overriding size register by configured bank size - MAY CAUSE TROUBLE");
1816 flash_size_kb = stm32l4_info->user_bank_size / 1024;
1817 }
1818
1819 LOG_INFO("flash size = %dkbytes", flash_size_kb);
1820
1821 /* did we assign a flash size? */
1822 assert((flash_size_kb != 0xffff) && flash_size_kb);
1823
1824 const bool is_max_flash_size = flash_size_kb == stm32l4_info->part_info->max_flash_size_kb;
1825
1826 stm32l4_info->bank1_sectors = 0;
1827 stm32l4_info->hole_sectors = 0;
1828
1829 int num_pages = 0;
1830 int page_size_kb = 0;
1831
1832 stm32l4_info->dual_bank_mode = false;
1833
1834 switch (device_id) {
1835 case DEVID_STM32L47_L48XX:
1836 case DEVID_STM32L49_L4AXX:
1837 /* if flash size is max (1M) the device is always dual bank
1838 * STM32L47/L48xx: has variants with 512K
1839 * STM32L49/L4Axx: has variants with 512 and 256
1840 * for these variants:
1841 * if DUAL_BANK = 0 -> single bank
1842 * else -> dual bank without gap
1843 * note: the page size is invariant
1844 */
1845 page_size_kb = 2;
1846 num_pages = flash_size_kb / page_size_kb;
1847 stm32l4_info->bank1_sectors = num_pages;
1848
1849 /* check DUAL_BANK option bit if the flash is less than 1M */
1850 if (is_max_flash_size || (stm32l4_info->optr & FLASH_L4_DUAL_BANK)) {
1851 stm32l4_info->dual_bank_mode = true;
1852 stm32l4_info->bank1_sectors = num_pages / 2;
1853 }
1854 break;
1855 case DEVID_STM32L43_L44XX:
1856 case DEVID_STM32G05_G06XX:
1857 case DEVID_STM32G07_G08XX:
1858 case DEVID_STM32L45_L46XX:
1859 case DEVID_STM32L41_L42XX:
1860 case DEVID_STM32G03_G04XX:
1861 case DEVID_STM32G43_G44XX:
1862 case DEVID_STM32G49_G4AXX:
1863 case DEVID_STM32WB1XX:
1864 /* single bank flash */
1865 page_size_kb = 2;
1866 num_pages = flash_size_kb / page_size_kb;
1867 stm32l4_info->bank1_sectors = num_pages;
1868 break;
1869 case DEVID_STM32G0B_G0CXX:
1870 /* single/dual bank depending on DUAL_BANK option bit */
1871 page_size_kb = 2;
1872 num_pages = flash_size_kb / page_size_kb;
1873 stm32l4_info->bank1_sectors = num_pages;
1874 stm32l4_info->cr_bker_mask = FLASH_BKER_G0;
1875
1876 /* check DUAL_BANK bit */
1877 if (stm32l4_info->optr & FLASH_G0_DUAL_BANK) {
1878 stm32l4_info->sr_bsy_mask = FLASH_BSY | FLASH_BSY2;
1879 stm32l4_info->dual_bank_mode = true;
1880 stm32l4_info->bank1_sectors = num_pages / 2;
1881 }
1882 break;
1883 case DEVID_STM32G47_G48XX:
1884 /* STM32G47/8 can be single/dual bank:
1885 * if DUAL_BANK = 0 -> single bank
1886 * else -> dual bank WITH gap
1887 */
1888 page_size_kb = 4;
1889 num_pages = flash_size_kb / page_size_kb;
1890 stm32l4_info->bank1_sectors = num_pages;
1891 if (stm32l4_info->optr & FLASH_G4_DUAL_BANK) {
1892 stm32l4_info->dual_bank_mode = true;
1893 page_size_kb = 2;
1894 num_pages = flash_size_kb / page_size_kb;
1895 stm32l4_info->bank1_sectors = num_pages / 2;
1896
1897 /* for devices with trimmed flash, there is a gap between both banks */
1898 stm32l4_info->hole_sectors =
1899 (part_info->max_flash_size_kb - flash_size_kb) / (2 * page_size_kb);
1900 }
1901 break;
1902 case DEVID_STM32L4R_L4SXX:
1903 case DEVID_STM32L4P_L4QXX:
1904 /* STM32L4R/S can be single/dual bank:
1905 * if size = 2M check DBANK bit
1906 * if size = 1M check DB1M bit
1907 * STM32L4P/Q can be single/dual bank
1908 * if size = 1M check DBANK bit
1909 * if size = 512K check DB512K bit (same as DB1M bit)
1910 */
1911 page_size_kb = 8;
1912 num_pages = flash_size_kb / page_size_kb;
1913 stm32l4_info->bank1_sectors = num_pages;
1914 if ((is_max_flash_size && (stm32l4_info->optr & FLASH_L4R_DBANK)) ||
1915 (!is_max_flash_size && (stm32l4_info->optr & FLASH_LRR_DB1M))) {
1916 stm32l4_info->dual_bank_mode = true;
1917 page_size_kb = 4;
1918 num_pages = flash_size_kb / page_size_kb;
1919 stm32l4_info->bank1_sectors = num_pages / 2;
1920 }
1921 break;
1922 case DEVID_STM32L55_L56XX:
1923 /* STM32L55/L56xx can be single/dual bank:
1924 * if size = 512K check DBANK bit
1925 * if size = 256K check DB256K bit
1926 *
1927 * default page size is 4kb, if DBANK = 1, the page size is 2kb.
1928 */
1929
1930 page_size_kb = (stm32l4_info->optr & FLASH_L5_DBANK) ? 2 : 4;
1931 num_pages = flash_size_kb / page_size_kb;
1932 stm32l4_info->bank1_sectors = num_pages;
1933
1934 if ((is_max_flash_size && (stm32l4_info->optr & FLASH_L5_DBANK)) ||
1935 (!is_max_flash_size && (stm32l4_info->optr & FLASH_L5_DB256))) {
1936 stm32l4_info->dual_bank_mode = true;
1937 stm32l4_info->bank1_sectors = num_pages / 2;
1938 }
1939 break;
1940 case DEVID_STM32U57_U58XX:
1941 /* if flash size is max (2M) the device is always dual bank
1942 * otherwise check DUALBANK
1943 */
1944 page_size_kb = 8;
1945 num_pages = flash_size_kb / page_size_kb;
1946 stm32l4_info->bank1_sectors = num_pages;
1947 if (is_max_flash_size || (stm32l4_info->optr & FLASH_U5_DUALBANK)) {
1948 stm32l4_info->dual_bank_mode = true;
1949 stm32l4_info->bank1_sectors = num_pages / 2;
1950 }
1951 break;
1952 case DEVID_STM32WB5XX:
1953 case DEVID_STM32WB3XX:
1954 /* single bank flash */
1955 page_size_kb = 4;
1956 num_pages = flash_size_kb / page_size_kb;
1957 stm32l4_info->bank1_sectors = num_pages;
1958 break;
1959 case DEVID_STM32WLE_WL5XX:
1960 /* single bank flash */
1961 page_size_kb = 2;
1962 num_pages = flash_size_kb / page_size_kb;
1963 stm32l4_info->bank1_sectors = num_pages;
1964
1965 /* CPU2 (Cortex-M0+) is supported only with non-hla adapters because it is on AP1.
1966 * Using HLA adapters armv7m->debug_ap is null, and checking ap_num triggers a segfault */
1967 if (armv7m->debug_ap && armv7m->debug_ap->ap_num == 1)
1968 stm32l4_info->flash_regs = stm32wl_cpu2_flash_regs;
1969 break;
1970 default:
1971 LOG_ERROR("unsupported device");
1972 return ERROR_FAIL;
1973 }
1974
1975 LOG_INFO("flash mode : %s-bank", stm32l4_info->dual_bank_mode ? "dual" : "single");
1976
1977 const int gap_size_kb = stm32l4_info->hole_sectors * page_size_kb;
1978
1979 if (gap_size_kb != 0) {
1980 LOG_INFO("gap detected from 0x%08x to 0x%08x",
1981 STM32_FLASH_BANK_BASE + stm32l4_info->bank1_sectors
1982 * page_size_kb * 1024,
1983 STM32_FLASH_BANK_BASE + (stm32l4_info->bank1_sectors
1984 * page_size_kb + gap_size_kb) * 1024 - 1);
1985 }
1986
1987 /* number of significant bits in WRPxxR differs per device,
1988 * always right adjusted, on some devices non-implemented
1989 * bits read as '0', on others as '1' ...
1990 * notably G4 Cat. 2 implement only 6 bits, contradicting the RM
1991 */
1992
1993 /* use *max_flash_size* instead of actual size as the trimmed versions
1994 * certainly use the same number of bits
1995 */
1996 uint32_t max_pages = stm32l4_info->part_info->max_flash_size_kb / page_size_kb;
1997
1998 /* in dual bank mode number of pages is doubled, but extra bit is bank selection */
1999 stm32l4_info->wrpxxr_mask = ((max_pages >> (stm32l4_info->dual_bank_mode ? 1 : 0)) - 1);
2000 assert((stm32l4_info->wrpxxr_mask & 0xFFFF0000) == 0);
2001 LOG_DEBUG("WRPxxR mask 0x%04" PRIx16, (uint16_t)stm32l4_info->wrpxxr_mask);
2002
2003 free(bank->sectors);
2004
2005 bank->size = (flash_size_kb + gap_size_kb) * 1024;
2006 bank->num_sectors = num_pages;
2007 bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
2008 if (!bank->sectors) {
2009 LOG_ERROR("failed to allocate bank sectors");
2010 return ERROR_FAIL;
2011 }
2012
2013 for (unsigned int i = 0; i < bank->num_sectors; i++) {
2014 bank->sectors[i].offset = i * page_size_kb * 1024;
2015 /* in dual bank configuration, if there is a gap between banks
2016 * we fix up the sector offset to consider this gap */
2017 if (i >= stm32l4_info->bank1_sectors && stm32l4_info->hole_sectors)
2018 bank->sectors[i].offset += gap_size_kb * 1024;
2019 bank->sectors[i].size = page_size_kb * 1024;
2020 bank->sectors[i].is_erased = -1;
2021 bank->sectors[i].is_protected = 1;
2022 }
2023
2024 stm32l4_info->probed = true;
2025 return ERROR_OK;
2026 }
2027
2028 static int stm32l4_auto_probe(struct flash_bank *bank)
2029 {
2030 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2031 if (stm32l4_info->probed) {
2032 uint32_t optr_cur;
2033
2034 /* read flash option register and re-probe if optr value is changed */
2035 int retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &optr_cur);
2036 if (retval != ERROR_OK)
2037 return retval;
2038
2039 if (stm32l4_info->optr == optr_cur)
2040 return ERROR_OK;
2041 }
2042
2043 return stm32l4_probe(bank);
2044 }
2045
2046 static int get_stm32l4_info(struct flash_bank *bank, struct command_invocation *cmd)
2047 {
2048 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2049 const struct stm32l4_part_info *part_info = stm32l4_info->part_info;
2050
2051 if (part_info) {
2052 const uint16_t rev_id = stm32l4_info->idcode >> 16;
2053 command_print_sameline(cmd, "%s - Rev %s : 0x%04x", part_info->device_str,
2054 get_stm32l4_rev_str(bank), rev_id);
2055 if (stm32l4_info->probed)
2056 command_print_sameline(cmd, " - %s-bank", get_stm32l4_bank_type_str(bank));
2057 } else {
2058 command_print_sameline(cmd, "Cannot identify target as an %s device", device_families);
2059 }
2060
2061 return ERROR_OK;
2062 }
2063
2064 static int stm32l4_mass_erase(struct flash_bank *bank)
2065 {
2066 int retval, retval2;
2067 struct target *target = bank->target;
2068 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2069
2070 if (stm32l4_is_otp(bank)) {
2071 LOG_ERROR("cannot erase OTP memory");
2072 return ERROR_FLASH_OPER_UNSUPPORTED;
2073 }
2074
2075 uint32_t action = FLASH_MER1;
2076
2077 if (stm32l4_info->part_info->flags & F_HAS_DUAL_BANK)
2078 action |= FLASH_MER2;
2079
2080 if (target->state != TARGET_HALTED) {
2081 LOG_ERROR("Target not halted");
2082 return ERROR_TARGET_NOT_HALTED;
2083 }
2084
2085 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
2086 /* set all FLASH pages as secure */
2087 retval = stm32l4_set_secbb(bank, FLASH_SECBB_SECURE);
2088 if (retval != ERROR_OK) {
2089 /* restore all FLASH pages as non-secure */
2090 stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
2091 return retval;
2092 }
2093 }
2094
2095 retval = stm32l4_unlock_reg(bank);
2096 if (retval != ERROR_OK)
2097 goto err_lock;
2098
2099 /* mass erase flash memory */
2100 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT / 10);
2101 if (retval != ERROR_OK)
2102 goto err_lock;
2103
2104 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, action);
2105 if (retval != ERROR_OK)
2106 goto err_lock;
2107
2108 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, action | FLASH_STRT);
2109 if (retval != ERROR_OK)
2110 goto err_lock;
2111
2112 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
2113
2114 err_lock:
2115 retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank), FLASH_LOCK);
2116
2117 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
2118 /* restore all FLASH pages as non-secure */
2119 int retval3 = stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE);
2120 if (retval3 != ERROR_OK)
2121 return retval3;
2122 }
2123
2124 if (retval != ERROR_OK)
2125 return retval;
2126
2127 return retval2;
2128 }
2129
2130 COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
2131 {
2132 if (CMD_ARGC < 1) {
2133 command_print(CMD, "stm32l4x mass_erase <STM32L4 bank>");
2134 return ERROR_COMMAND_SYNTAX_ERROR;
2135 }
2136
2137 struct flash_bank *bank;
2138 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2139 if (retval != ERROR_OK)
2140 return retval;
2141
2142 retval = stm32l4_mass_erase(bank);
2143 if (retval == ERROR_OK)
2144 command_print(CMD, "stm32l4x mass erase complete");
2145 else
2146 command_print(CMD, "stm32l4x mass erase failed");
2147
2148 return retval;
2149 }
2150
2151 COMMAND_HANDLER(stm32l4_handle_option_read_command)
2152 {
2153 if (CMD_ARGC < 2) {
2154 command_print(CMD, "stm32l4x option_read <STM32L4 bank> <option_reg offset>");
2155 return ERROR_COMMAND_SYNTAX_ERROR;
2156 }
2157
2158 struct flash_bank *bank;
2159 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2160 if (retval != ERROR_OK)
2161 return retval;
2162
2163 uint32_t reg_offset, reg_addr;
2164 uint32_t value = 0;
2165
2166 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
2167 reg_addr = stm32l4_get_flash_reg(bank, reg_offset);
2168
2169 retval = stm32l4_read_flash_reg(bank, reg_offset, &value);
2170 if (retval != ERROR_OK)
2171 return retval;
2172
2173 command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "", reg_addr, value);
2174
2175 return retval;
2176 }
2177
2178 COMMAND_HANDLER(stm32l4_handle_option_write_command)
2179 {
2180 if (CMD_ARGC < 3) {
2181 command_print(CMD, "stm32l4x option_write <STM32L4 bank> <option_reg offset> <value> [mask]");
2182 return ERROR_COMMAND_SYNTAX_ERROR;
2183 }
2184
2185 struct flash_bank *bank;
2186 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2187 if (retval != ERROR_OK)
2188 return retval;
2189
2190 uint32_t reg_offset;
2191 uint32_t value = 0;
2192 uint32_t mask = 0xFFFFFFFF;
2193
2194 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
2195 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
2196
2197 if (CMD_ARGC > 3)
2198 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], mask);
2199
2200 command_print(CMD, "%s Option written.\n"
2201 "INFO: a reset or power cycle is required "
2202 "for the new settings to take effect.", bank->driver->name);
2203
2204 retval = stm32l4_write_option(bank, reg_offset, value, mask);
2205 return retval;
2206 }
2207
2208 COMMAND_HANDLER(stm32l4_handle_trustzone_command)
2209 {
2210 if (CMD_ARGC < 1 || CMD_ARGC > 2)
2211 return ERROR_COMMAND_SYNTAX_ERROR;
2212
2213 struct flash_bank *bank;
2214 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2215 if (retval != ERROR_OK)
2216 return retval;
2217
2218 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2219 if (!(stm32l4_info->part_info->flags & F_HAS_TZ)) {
2220 LOG_ERROR("This device does not have a TrustZone");
2221 return ERROR_FAIL;
2222 }
2223
2224 retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &stm32l4_info->optr);
2225 if (retval != ERROR_OK)
2226 return retval;
2227
2228 stm32l4_sync_rdp_tzen(bank);
2229
2230 if (CMD_ARGC == 1) {
2231 /* only display the TZEN value */
2232 LOG_INFO("Global TrustZone Security is %s", stm32l4_info->tzen ? "enabled" : "disabled");
2233 return ERROR_OK;
2234 }
2235
2236 bool new_tzen;
2237 COMMAND_PARSE_ENABLE(CMD_ARGV[1], new_tzen);
2238
2239 if (new_tzen == stm32l4_info->tzen) {
2240 LOG_INFO("The requested TZEN is already programmed");
2241 return ERROR_OK;
2242 }
2243
2244 if (new_tzen) {
2245 if (stm32l4_info->rdp != RDP_LEVEL_0) {
2246 LOG_ERROR("TZEN can be set only when RDP level is 0");
2247 return ERROR_FAIL;
2248 }
2249 retval = stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX],
2250 FLASH_TZEN, FLASH_TZEN);
2251 } else {
2252 /* Deactivation of TZEN (from 1 to 0) is only possible when the RDP is
2253 * changing to level 0 (from level 1 to level 0 or from level 0.5 to level 0). */
2254 if (stm32l4_info->rdp != RDP_LEVEL_1 && stm32l4_info->rdp != RDP_LEVEL_0_5) {
2255 LOG_ERROR("Deactivation of TZEN is only possible when the RDP is changing to level 0");
2256 return ERROR_FAIL;
2257 }
2258
2259 retval = stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX],
2260 RDP_LEVEL_0, FLASH_RDP_MASK | FLASH_TZEN);
2261 }
2262
2263 if (retval != ERROR_OK)
2264 return retval;
2265
2266 return stm32l4_perform_obl_launch(bank);
2267 }
2268
2269 COMMAND_HANDLER(stm32l4_handle_option_load_command)
2270 {
2271 if (CMD_ARGC != 1)
2272 return ERROR_COMMAND_SYNTAX_ERROR;
2273
2274 struct flash_bank *bank;
2275 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2276 if (retval != ERROR_OK)
2277 return retval;
2278
2279 retval = stm32l4_perform_obl_launch(bank);
2280 if (retval != ERROR_OK) {
2281 command_print(CMD, "stm32l4x option load failed");
2282 return retval;
2283 }
2284
2285
2286 command_print(CMD, "stm32l4x option load completed. Power-on reset might be required");
2287
2288 return ERROR_OK;
2289 }
2290
2291 COMMAND_HANDLER(stm32l4_handle_lock_command)
2292 {
2293 struct target *target = NULL;
2294
2295 if (CMD_ARGC < 1)
2296 return ERROR_COMMAND_SYNTAX_ERROR;
2297
2298 struct flash_bank *bank;
2299 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2300 if (retval != ERROR_OK)
2301 return retval;
2302
2303 if (stm32l4_is_otp(bank)) {
2304 LOG_ERROR("cannot lock/unlock OTP memory");
2305 return ERROR_FLASH_OPER_UNSUPPORTED;
2306 }
2307
2308 target = bank->target;
2309
2310 if (target->state != TARGET_HALTED) {
2311 LOG_ERROR("Target not halted");
2312 return ERROR_TARGET_NOT_HALTED;
2313 }
2314
2315 /* set readout protection level 1 by erasing the RDP option byte */
2316 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2317 if (stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX],
2318 RDP_LEVEL_1, FLASH_RDP_MASK) != ERROR_OK) {
2319 command_print(CMD, "%s failed to lock device", bank->driver->name);
2320 return ERROR_OK;
2321 }
2322
2323 return ERROR_OK;
2324 }
2325
2326 COMMAND_HANDLER(stm32l4_handle_unlock_command)
2327 {
2328 struct target *target = NULL;
2329
2330 if (CMD_ARGC < 1)
2331 return ERROR_COMMAND_SYNTAX_ERROR;
2332
2333 struct flash_bank *bank;
2334 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2335 if (retval != ERROR_OK)
2336 return retval;
2337
2338 if (stm32l4_is_otp(bank)) {
2339 LOG_ERROR("cannot lock/unlock OTP memory");
2340 return ERROR_FLASH_OPER_UNSUPPORTED;
2341 }
2342
2343 target = bank->target;
2344
2345 if (target->state != TARGET_HALTED) {
2346 LOG_ERROR("Target not halted");
2347 return ERROR_TARGET_NOT_HALTED;
2348 }
2349
2350 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2351 if (stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX],
2352 RDP_LEVEL_0, FLASH_RDP_MASK) != ERROR_OK) {
2353 command_print(CMD, "%s failed to unlock device", bank->driver->name);
2354 return ERROR_OK;
2355 }
2356
2357 return ERROR_OK;
2358 }
2359
2360 COMMAND_HANDLER(stm32l4_handle_wrp_info_command)
2361 {
2362 if (CMD_ARGC < 1 || CMD_ARGC > 2)
2363 return ERROR_COMMAND_SYNTAX_ERROR;
2364
2365 struct flash_bank *bank;
2366 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2367 if (retval != ERROR_OK)
2368 return retval;
2369
2370 if (stm32l4_is_otp(bank)) {
2371 LOG_ERROR("OTP memory does not have write protection areas");
2372 return ERROR_FLASH_OPER_UNSUPPORTED;
2373 }
2374
2375 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2376 enum stm32_bank_id dev_bank_id = STM32_ALL_BANKS;
2377 if (CMD_ARGC == 2) {
2378 if (strcmp(CMD_ARGV[1], "bank1") == 0)
2379 dev_bank_id = STM32_BANK1;
2380 else if (strcmp(CMD_ARGV[1], "bank2") == 0)
2381 dev_bank_id = STM32_BANK2;
2382 else
2383 return ERROR_COMMAND_ARGUMENT_INVALID;
2384 }
2385
2386 if (dev_bank_id == STM32_BANK2) {
2387 if (!(stm32l4_info->part_info->flags & F_HAS_DUAL_BANK)) {
2388 LOG_ERROR("this device has no second bank");
2389 return ERROR_FAIL;
2390 } else if (!stm32l4_info->dual_bank_mode) {
2391 LOG_ERROR("this device is configured in single bank mode");
2392 return ERROR_FAIL;
2393 }
2394 }
2395
2396 int ret;
2397 unsigned int n_wrp, i;
2398 struct stm32l4_wrp wrpxy[4];
2399
2400 ret = stm32l4_get_all_wrpxy(bank, dev_bank_id, wrpxy, &n_wrp);
2401 if (ret != ERROR_OK)
2402 return ret;
2403
2404 /* use bitmap and range helpers to better describe protected areas */
2405 DECLARE_BITMAP(pages, bank->num_sectors);
2406 bitmap_zero(pages, bank->num_sectors);
2407
2408 for (i = 0; i < n_wrp; i++) {
2409 if (wrpxy[i].used) {
2410 for (int p = wrpxy[i].first; p <= wrpxy[i].last; p++)
2411 set_bit(p, pages);
2412 }
2413 }
2414
2415 /* we have at most 'n_wrp' WRP areas */
2416 struct range ranges[n_wrp];
2417 unsigned int ranges_count = 0;
2418
2419 bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count);
2420
2421 if (ranges_count > 0) {
2422 /* pretty-print the protected ranges */
2423 char *ranges_str = range_print_alloc(ranges, ranges_count);
2424 command_print(CMD, "protected areas: %s", ranges_str);
2425 free(ranges_str);
2426 } else
2427 command_print(CMD, "no protected areas");
2428
2429 return ERROR_OK;
2430 }
2431
2432 COMMAND_HANDLER(stm32l4_handle_otp_command)
2433 {
2434 if (CMD_ARGC < 2)
2435 return ERROR_COMMAND_SYNTAX_ERROR;
2436
2437 struct flash_bank *bank;
2438 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2439 if (retval != ERROR_OK)
2440 return retval;
2441
2442 if (!stm32l4_is_otp(bank)) {
2443 command_print(CMD, "the specified bank is not an OTP memory");
2444 return ERROR_FAIL;
2445 }
2446 if (strcmp(CMD_ARGV[1], "enable") == 0)
2447 stm32l4_otp_enable(bank, true);
2448 else if (strcmp(CMD_ARGV[1], "disable") == 0)
2449 stm32l4_otp_enable(bank, false);
2450 else if (strcmp(CMD_ARGV[1], "show") == 0)
2451 command_print(CMD, "OTP memory bank #%d is %s for write commands.",
2452 bank->bank_number, stm32l4_otp_is_enabled(bank) ? "enabled" : "disabled");
2453 else
2454 return ERROR_COMMAND_SYNTAX_ERROR;
2455
2456 return ERROR_OK;
2457 }
2458
2459 static const struct command_registration stm32l4_exec_command_handlers[] = {
2460 {
2461 .name = "lock",
2462 .handler = stm32l4_handle_lock_command,
2463 .mode = COMMAND_EXEC,
2464 .usage = "bank_id",
2465 .help = "Lock entire flash device.",
2466 },
2467 {
2468 .name = "unlock",
2469 .handler = stm32l4_handle_unlock_command,
2470 .mode = COMMAND_EXEC,
2471 .usage = "bank_id",
2472 .help = "Unlock entire protected flash device.",
2473 },
2474 {
2475 .name = "mass_erase",
2476 .handler = stm32l4_handle_mass_erase_command,
2477 .mode = COMMAND_EXEC,
2478 .usage = "bank_id",
2479 .help = "Erase entire flash device.",
2480 },
2481 {
2482 .name = "option_read",
2483 .handler = stm32l4_handle_option_read_command,
2484 .mode = COMMAND_EXEC,
2485 .usage = "bank_id reg_offset",
2486 .help = "Read & Display device option bytes.",
2487 },
2488 {
2489 .name = "option_write",
2490 .handler = stm32l4_handle_option_write_command,
2491 .mode = COMMAND_EXEC,
2492 .usage = "bank_id reg_offset value mask",
2493 .help = "Write device option bit fields with provided value.",
2494 },
2495 {
2496 .name = "trustzone",
2497 .handler = stm32l4_handle_trustzone_command,
2498 .mode = COMMAND_EXEC,
2499 .usage = "<bank_id> [enable|disable]",
2500 .help = "Configure TrustZone security",
2501 },
2502 {
2503 .name = "wrp_info",
2504 .handler = stm32l4_handle_wrp_info_command,
2505 .mode = COMMAND_EXEC,
2506 .usage = "bank_id [bank1|bank2]",
2507 .help = "list the protected areas using WRP",
2508 },
2509 {
2510 .name = "option_load",
2511 .handler = stm32l4_handle_option_load_command,
2512 .mode = COMMAND_EXEC,
2513 .usage = "bank_id",
2514 .help = "Force re-load of device options (will cause device reset).",
2515 },
2516 {
2517 .name = "otp",
2518 .handler = stm32l4_handle_otp_command,
2519 .mode = COMMAND_EXEC,
2520 .usage = "<bank_id> <enable|disable|show>",
2521 .help = "OTP (One Time Programmable) memory write enable/disable",
2522 },
2523 COMMAND_REGISTRATION_DONE
2524 };
2525
2526 static const struct command_registration stm32l4_command_handlers[] = {
2527 {
2528 .name = "stm32l4x",
2529 .mode = COMMAND_ANY,
2530 .help = "stm32l4x flash command group",
2531 .usage = "",
2532 .chain = stm32l4_exec_command_handlers,
2533 },
2534 COMMAND_REGISTRATION_DONE
2535 };
2536
2537 const struct flash_driver stm32l4x_flash = {
2538 .name = "stm32l4x",
2539 .commands = stm32l4_command_handlers,
2540 .flash_bank_command = stm32l4_flash_bank_command,
2541 .erase = stm32l4_erase,
2542 .protect = stm32l4_protect,
2543 .write = stm32l4_write,
2544 .read = default_flash_read,
2545 .probe = stm32l4_probe,
2546 .auto_probe = stm32l4_auto_probe,
2547 .erase_check = default_flash_blank_check,
2548 .protect_check = stm32l4_protect_check,
2549 .info = get_stm32l4_info,
2550 .free_driver_priv = default_flash_free_driver_priv,
2551 };
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