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[openocd.git] / src / flash / nor / stm32l4x.c
1 /***************************************************************************
2 * Copyright (C) 2015 by Uwe Bonnes *
3 * bon@elektron.ikp.physik.tu-darmstadt.de *
4 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
18
19 #ifdef HAVE_CONFIG_H
20 #include "config.h"
21 #endif
22
23 #include "imp.h"
24 #include <helper/binarybuffer.h>
25 #include <target/algorithm.h>
26 #include <target/armv7m.h>
27
28 /* STM32L4xxx series for reference.
29 *
30 * RM0351 (STM32L4x5/STM32L4x6)
31 * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
32 *
33 * RM0394 (STM32L43x/44x/45x/46x)
34 * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
35 *
36 * STM32L476RG Datasheet (for erase timing)
37 * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
38 *
39 * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
40 * an option byte is available to map all sectors to the first bank.
41 * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
42 * handlers do!
43 *
44 * RM0394 devices have a single bank only.
45 *
46 */
47
48 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
49
50 #define FLASH_ERASE_TIMEOUT 250
51
52 #define STM32_FLASH_BASE 0x40022000
53 #define STM32_FLASH_ACR 0x40022000
54 #define STM32_FLASH_KEYR 0x40022008
55 #define STM32_FLASH_OPTKEYR 0x4002200c
56 #define STM32_FLASH_SR 0x40022010
57 #define STM32_FLASH_CR 0x40022014
58 #define STM32_FLASH_OPTR 0x40022020
59 #define STM32_FLASH_WRP1AR 0x4002202c
60 #define STM32_FLASH_WRP2AR 0x40022030
61 #define STM32_FLASH_WRP1BR 0x4002204c
62 #define STM32_FLASH_WRP2BR 0x40022050
63
64 /* FLASH_CR register bits */
65
66 #define FLASH_PG (1 << 0)
67 #define FLASH_PER (1 << 1)
68 #define FLASH_MER1 (1 << 2)
69 #define FLASH_PAGE_SHIFT 3
70 #define FLASH_CR_BKER (1 << 11)
71 #define FLASH_MER2 (1 << 15)
72 #define FLASH_STRT (1 << 16)
73 #define FLASH_EOPIE (1 << 24)
74 #define FLASH_ERRIE (1 << 25)
75 #define FLASH_OPTLOCK (1 << 30)
76 #define FLASH_LOCK (1 << 31)
77
78 /* FLASH_SR register bits */
79
80 #define FLASH_BSY (1 << 16)
81 /* Fast programming not used => related errors not used*/
82 #define FLASH_PGSERR (1 << 7) /* Programming sequence error */
83 #define FLASH_SIZERR (1 << 6) /* Size error */
84 #define FLASH_PGAERR (1 << 5) /* Programming alignment error */
85 #define FLASH_WRPERR (1 << 4) /* Write protection error */
86 #define FLASH_PROGERR (1 << 3) /* Programming error */
87 #define FLASH_OPERR (1 << 1) /* Operation error */
88 #define FLASH_EOP (1 << 0) /* End of operation */
89
90 #define FLASH_ERROR (FLASH_PGSERR | FLASH_PGSERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_OPERR)
91
92 /* STM32_FLASH_OBR bit definitions (reading) */
93
94 #define OPT_DUALBANK 21 /* dual flash bank only */
95
96 /* register unlock keys */
97
98 #define KEY1 0x45670123
99 #define KEY2 0xCDEF89AB
100
101 /* option register unlock key */
102 #define OPTKEY1 0x08192A3B
103 #define OPTKEY2 0x4C5D6E7F
104
105
106 /* other registers */
107 #define DBGMCU_IDCODE 0xE0042000
108 #define FLASH_SIZE_REG 0x1FFF75E0
109
110 struct stm32l4_options {
111 uint8_t RDP;
112 uint16_t bank_b_start;
113 uint8_t user_options;
114 uint8_t wpr1a_start;
115 uint8_t wpr1a_end;
116 uint8_t wpr1b_start;
117 uint8_t wpr1b_end;
118 uint8_t wpr2a_start;
119 uint8_t wpr2a_end;
120 uint8_t wpr2b_start;
121 uint8_t wpr2b_end;
122 /* Fixme: Handle PCROP */
123 };
124
125 struct stm32l4_flash_bank {
126 struct stm32l4_options option_bytes;
127 int probed;
128 };
129
130 /* flash bank stm32l4x <base> <size> 0 0 <target#>
131 */
132 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
133 {
134 struct stm32l4_flash_bank *stm32l4_info;
135
136 if (CMD_ARGC < 6)
137 return ERROR_COMMAND_SYNTAX_ERROR;
138
139 stm32l4_info = malloc(sizeof(struct stm32l4_flash_bank));
140 if (!stm32l4_info)
141 return ERROR_FAIL; /* Checkme: What better error to use?*/
142 bank->driver_priv = stm32l4_info;
143
144 stm32l4_info->probed = 0;
145
146 return ERROR_OK;
147 }
148
149 static inline int stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg)
150 {
151 return reg;
152 }
153
154 static inline int stm32l4_get_flash_status(struct flash_bank *bank, uint32_t *status)
155 {
156 struct target *target = bank->target;
157 return target_read_u32(
158 target, stm32l4_get_flash_reg(bank, STM32_FLASH_SR), status);
159 }
160
161 static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
162 {
163 struct target *target = bank->target;
164 uint32_t status;
165 int retval = ERROR_OK;
166
167 /* wait for busy to clear */
168 for (;;) {
169 retval = stm32l4_get_flash_status(bank, &status);
170 if (retval != ERROR_OK)
171 return retval;
172 LOG_DEBUG("status: 0x%" PRIx32 "", status);
173 if ((status & FLASH_BSY) == 0)
174 break;
175 if (timeout-- <= 0) {
176 LOG_ERROR("timed out waiting for flash");
177 return ERROR_FAIL;
178 }
179 alive_sleep(1);
180 }
181
182
183 if (status & FLASH_WRPERR) {
184 LOG_ERROR("stm32x device protected");
185 retval = ERROR_FAIL;
186 }
187
188 /* Clear but report errors */
189 if (status & FLASH_ERROR) {
190 /* If this operation fails, we ignore it and report the original
191 * retval
192 */
193 target_write_u32(target, stm32l4_get_flash_reg(bank, STM32_FLASH_SR),
194 status & FLASH_ERROR);
195 }
196 return retval;
197 }
198
199 static int stm32l4_unlock_reg(struct target *target)
200 {
201 uint32_t ctrl;
202
203 /* first check if not already unlocked
204 * otherwise writing on STM32_FLASH_KEYR will fail
205 */
206 int retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
207 if (retval != ERROR_OK)
208 return retval;
209
210 if ((ctrl & FLASH_LOCK) == 0)
211 return ERROR_OK;
212
213 /* unlock flash registers */
214 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
215 if (retval != ERROR_OK)
216 return retval;
217
218 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
219 if (retval != ERROR_OK)
220 return retval;
221
222 retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
223 if (retval != ERROR_OK)
224 return retval;
225
226 if (ctrl & FLASH_LOCK) {
227 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
228 return ERROR_TARGET_FAILURE;
229 }
230
231 return ERROR_OK;
232 }
233
234 static int stm32l4_unlock_option_reg(struct target *target)
235 {
236 uint32_t ctrl;
237
238 int retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
239 if (retval != ERROR_OK)
240 return retval;
241
242 if ((ctrl & FLASH_OPTLOCK) == 0)
243 return ERROR_OK;
244
245 /* unlock option registers */
246 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, OPTKEY1);
247 if (retval != ERROR_OK)
248 return retval;
249
250 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, OPTKEY2);
251 if (retval != ERROR_OK)
252 return retval;
253
254 retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
255 if (retval != ERROR_OK)
256 return retval;
257
258 if (ctrl & FLASH_OPTLOCK) {
259 LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
260 return ERROR_TARGET_FAILURE;
261 }
262
263 return ERROR_OK;
264 }
265
266 static int stm32l4_read_options(struct flash_bank *bank)
267 {
268 uint32_t optiondata;
269 struct stm32l4_flash_bank *stm32l4_info = NULL;
270 struct target *target = bank->target;
271
272 stm32l4_info = bank->driver_priv;
273
274 /* read current option bytes */
275 int retval = target_read_u32(target, STM32_FLASH_OPTR, &optiondata);
276 if (retval != ERROR_OK)
277 return retval;
278
279 stm32l4_info->option_bytes.user_options = (optiondata >> 8) & 0x3ffff;
280 stm32l4_info->option_bytes.RDP = optiondata & 0xff;
281
282 retval = target_read_u32(target, STM32_FLASH_WRP1AR, &optiondata);
283 if (retval != ERROR_OK)
284 return retval;
285 stm32l4_info->option_bytes.wpr1a_start = optiondata & 0xff;
286 stm32l4_info->option_bytes.wpr1a_end = (optiondata >> 16) & 0xff;
287
288 retval = target_read_u32(target, STM32_FLASH_WRP2AR, &optiondata);
289 if (retval != ERROR_OK)
290 return retval;
291 stm32l4_info->option_bytes.wpr2a_start = optiondata & 0xff;
292 stm32l4_info->option_bytes.wpr2a_end = (optiondata >> 16) & 0xff;
293
294 retval = target_read_u32(target, STM32_FLASH_WRP1BR, &optiondata);
295 if (retval != ERROR_OK)
296 return retval;
297 stm32l4_info->option_bytes.wpr1b_start = optiondata & 0xff;
298 stm32l4_info->option_bytes.wpr1b_end = (optiondata >> 16) & 0xff;
299
300 retval = target_read_u32(target, STM32_FLASH_WRP2BR, &optiondata);
301 if (retval != ERROR_OK)
302 return retval;
303 stm32l4_info->option_bytes.wpr2b_start = optiondata & 0xff;
304 stm32l4_info->option_bytes.wpr2b_end = (optiondata >> 16) & 0xff;
305
306 if (stm32l4_info->option_bytes.RDP != 0xAA)
307 LOG_INFO("Device Security Bit Set");
308
309 return ERROR_OK;
310 }
311
312 static int stm32l4_write_options(struct flash_bank *bank)
313 {
314 struct stm32l4_flash_bank *stm32l4_info = NULL;
315 struct target *target = bank->target;
316 uint32_t optiondata;
317
318 stm32l4_info = bank->driver_priv;
319
320 (void) optiondata;
321 (void) stm32l4_info;
322
323 int retval = stm32l4_unlock_option_reg(target);
324 if (retval != ERROR_OK)
325 return retval;
326 /* FIXME: Implement Option writing!*/
327 return ERROR_OK;
328 }
329
330 static int stm32l4_protect_check(struct flash_bank *bank)
331 {
332 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
333
334 /* read write protection settings */
335 int retval = stm32l4_read_options(bank);
336 if (retval != ERROR_OK) {
337 LOG_DEBUG("unable to read option bytes");
338 return retval;
339 }
340
341 for (int i = 0; i < bank->num_sectors; i++) {
342 if (i < stm32l4_info->option_bytes.bank_b_start) {
343 if (((i >= stm32l4_info->option_bytes.wpr1a_start) &&
344 (i <= stm32l4_info->option_bytes.wpr1a_end)) ||
345 ((i >= stm32l4_info->option_bytes.wpr2a_start) &&
346 (i <= stm32l4_info->option_bytes.wpr2a_end)))
347 bank->sectors[i].is_protected = 1;
348 else
349 bank->sectors[i].is_protected = 0;
350 } else {
351 uint8_t snb;
352 snb = i - stm32l4_info->option_bytes.bank_b_start + 256;
353 if (((snb >= stm32l4_info->option_bytes.wpr1b_start) &&
354 (snb <= stm32l4_info->option_bytes.wpr1b_end)) ||
355 ((snb >= stm32l4_info->option_bytes.wpr2b_start) &&
356 (snb <= stm32l4_info->option_bytes.wpr2b_end)))
357 bank->sectors[i].is_protected = 1;
358 else
359 bank->sectors[i].is_protected = 0;
360 }
361 }
362 return ERROR_OK;
363 }
364
365 static int stm32l4_erase(struct flash_bank *bank, int first, int last)
366 {
367 struct target *target = bank->target;
368 int i;
369
370 assert(first < bank->num_sectors);
371 assert(last < bank->num_sectors);
372
373 if (bank->target->state != TARGET_HALTED) {
374 LOG_ERROR("Target not halted");
375 return ERROR_TARGET_NOT_HALTED;
376 }
377
378 int retval;
379 retval = stm32l4_unlock_reg(target);
380 if (retval != ERROR_OK)
381 return retval;
382
383 /*
384 Sector Erase
385 To erase a sector, follow the procedure below:
386 1. Check that no Flash memory operation is ongoing by
387 checking the BSY bit in the FLASH_SR register
388 2. Set the PER bit and select the page and bank
389 you wish to erase in the FLASH_CR register
390 3. Set the STRT bit in the FLASH_CR register
391 4. Wait for the BSY bit to be cleared
392 */
393 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
394
395 for (i = first; i <= last; i++) {
396 uint32_t erase_flags;
397 erase_flags = FLASH_PER | FLASH_STRT;
398
399 if (i >= stm32l4_info->option_bytes.bank_b_start) {
400 uint8_t snb;
401 snb = (i - stm32l4_info->option_bytes.bank_b_start) + 256;
402 erase_flags |= snb << FLASH_PAGE_SHIFT | FLASH_CR_BKER;
403 } else
404 erase_flags |= i << FLASH_PAGE_SHIFT;
405 retval = target_write_u32(target,
406 stm32l4_get_flash_reg(bank, STM32_FLASH_CR), erase_flags);
407 if (retval != ERROR_OK)
408 return retval;
409
410 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
411 if (retval != ERROR_OK)
412 return retval;
413
414 bank->sectors[i].is_erased = 1;
415 }
416
417 retval = target_write_u32(
418 target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
419 if (retval != ERROR_OK)
420 return retval;
421
422 return ERROR_OK;
423 }
424
425 static int stm32l4_protect(struct flash_bank *bank, int set, int first, int last)
426 {
427 struct target *target = bank->target;
428 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
429
430 if (target->state != TARGET_HALTED) {
431 LOG_ERROR("Target not halted");
432 return ERROR_TARGET_NOT_HALTED;
433 }
434
435 /* read protection settings */
436 int retval = stm32l4_read_options(bank);
437 if (retval != ERROR_OK) {
438 LOG_DEBUG("unable to read option bytes");
439 return retval;
440 }
441
442 (void)stm32l4_info;
443 /* FIXME: Write First and last in a valid WRPxx_start/end combo*/
444 retval = stm32l4_write_options(bank);
445 if (retval != ERROR_OK)
446 return retval;
447
448 return ERROR_OK;
449 }
450
451 /* Count is in halfwords */
452 static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
453 uint32_t offset, uint32_t count)
454 {
455 struct target *target = bank->target;
456 uint32_t buffer_size = 16384;
457 struct working_area *write_algorithm;
458 struct working_area *source;
459 uint32_t address = bank->base + offset;
460 struct reg_param reg_params[5];
461 struct armv7m_algorithm armv7m_info;
462 int retval = ERROR_OK;
463
464 static const uint8_t stm32l4_flash_write_code[] = {
465 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
466 };
467
468 if (target_alloc_working_area(target, sizeof(stm32l4_flash_write_code),
469 &write_algorithm) != ERROR_OK) {
470 LOG_WARNING("no working area available, can't do block memory writes");
471 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
472 }
473
474 retval = target_write_buffer(target, write_algorithm->address,
475 sizeof(stm32l4_flash_write_code),
476 stm32l4_flash_write_code);
477 if (retval != ERROR_OK)
478 return retval;
479
480 /* memory buffer */
481 while (target_alloc_working_area_try(target, buffer_size, &source) !=
482 ERROR_OK) {
483 buffer_size /= 2;
484 if (buffer_size <= 256) {
485 /* we already allocated the writing code, but failed to get a
486 * buffer, free the algorithm */
487 target_free_working_area(target, write_algorithm);
488
489 LOG_WARNING("no large enough working area available, can't do block memory writes");
490 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
491 }
492 }
493
494 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
495 armv7m_info.core_mode = ARM_MODE_THREAD;
496
497 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
498 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* buffer end */
499 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* target address */
500 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* count (double word-64bit) */
501 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT); /* flash base */
502
503 buf_set_u32(reg_params[0].value, 0, 32, source->address);
504 buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
505 buf_set_u32(reg_params[2].value, 0, 32, address);
506 buf_set_u32(reg_params[3].value, 0, 32, count / 4);
507 buf_set_u32(reg_params[4].value, 0, 32, STM32_FLASH_BASE);
508
509 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
510 0, NULL,
511 5, reg_params,
512 source->address, source->size,
513 write_algorithm->address, 0,
514 &armv7m_info);
515
516 if (retval == ERROR_FLASH_OPERATION_FAILED) {
517 LOG_ERROR("error executing stm32l4 flash write algorithm");
518
519 uint32_t error = buf_get_u32(reg_params[0].value, 0, 32) & FLASH_ERROR;
520
521 if (error & FLASH_WRPERR)
522 LOG_ERROR("flash memory write protected");
523
524 if (error != 0) {
525 LOG_ERROR("flash write failed = %08" PRIx32, error);
526 /* Clear but report errors */
527 target_write_u32(target, STM32_FLASH_SR, error);
528 retval = ERROR_FAIL;
529 }
530 }
531
532 target_free_working_area(target, source);
533 target_free_working_area(target, write_algorithm);
534
535 destroy_reg_param(&reg_params[0]);
536 destroy_reg_param(&reg_params[1]);
537 destroy_reg_param(&reg_params[2]);
538 destroy_reg_param(&reg_params[3]);
539 destroy_reg_param(&reg_params[4]);
540
541 return retval;
542 }
543
544 static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
545 uint32_t offset, uint32_t count)
546 {
547 struct target *target = bank->target;
548 int retval;
549
550 if (bank->target->state != TARGET_HALTED) {
551 LOG_ERROR("Target not halted");
552 return ERROR_TARGET_NOT_HALTED;
553 }
554
555 if (offset & 0x7) {
556 LOG_WARNING("offset 0x%" PRIx32 " breaks required 8-byte alignment",
557 offset);
558 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
559 }
560
561 if (count & 0x7) {
562 LOG_WARNING("Padding %d bytes to keep 8-byte write size",
563 count & 7);
564 count = (count + 7) & ~7;
565 /* This pads the write chunk with random bytes by overrunning the
566 * write buffer. Padding with the erased pattern 0xff is purely
567 * cosmetical, as 8-byte flash words are ECC secured and the first
568 * write will program the ECC bits. A second write would need
569 * to reprogramm these ECC bits.
570 * But this can only be done after erase!
571 */
572 }
573
574 retval = stm32l4_unlock_reg(target);
575 if (retval != ERROR_OK)
576 return retval;
577
578 /* Only full double words (8-byte) can be programmed*/
579 retval = stm32l4_write_block(bank, buffer, offset, count / 2);
580 if (retval != ERROR_OK) {
581 LOG_WARNING("block write failed");
582 return retval;
583 }
584
585 LOG_WARNING("block write succeeded");
586 return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
587 }
588
589 static int stm32l4_probe(struct flash_bank *bank)
590 {
591 struct target *target = bank->target;
592 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
593 int i;
594 uint16_t flash_size_in_kb = 0xffff;
595 uint16_t max_flash_size_in_kb;
596 uint32_t device_id;
597 uint32_t options;
598 uint32_t base_address = 0x08000000;
599
600 stm32l4_info->probed = 0;
601
602 /* read stm32 device id register */
603 int retval = target_read_u32(target, DBGMCU_IDCODE, &device_id);
604 if (retval != ERROR_OK)
605 return retval;
606 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
607
608 /* set max flash size depending on family */
609 switch (device_id & 0xfff) {
610 case 0x461:
611 case 0x415:
612 max_flash_size_in_kb = 1024;
613 break;
614 case 0x462:
615 max_flash_size_in_kb = 512;
616 break;
617 case 0x435:
618 max_flash_size_in_kb = 256;
619 break;
620 default:
621 LOG_WARNING("Cannot identify target as a STM32L4 family.");
622 return ERROR_FAIL;
623 }
624
625 /* get flash size from target. */
626 retval = target_read_u16(target, FLASH_SIZE_REG, &flash_size_in_kb);
627
628 /* failed reading flash size or flash size invalid (early silicon),
629 * default to max target family */
630 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
631 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
632 max_flash_size_in_kb);
633 flash_size_in_kb = max_flash_size_in_kb;
634 }
635
636 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
637
638 /* did we assign flash size? */
639 assert(flash_size_in_kb != 0xffff);
640
641 /* get options to for DUAL BANK. */
642 retval = target_read_u32(target, STM32_FLASH_OPTR, &options);
643
644 if (retval != ERROR_OK)
645 return retval;
646
647 /* only devices with < 1024 kiB may be set to single bank dual banks */
648 if ((flash_size_in_kb == 1024) || !(options & OPT_DUALBANK))
649 stm32l4_info->option_bytes.bank_b_start = 256;
650 else
651 stm32l4_info->option_bytes.bank_b_start = flash_size_in_kb << 9;
652
653 /* did we assign flash size? */
654 assert((flash_size_in_kb != 0xffff) && flash_size_in_kb);
655
656 /* calculate numbers of pages */
657 int num_pages = flash_size_in_kb / 2;
658
659 /* check that calculation result makes sense */
660 assert(num_pages > 0);
661
662 if (bank->sectors) {
663 free(bank->sectors);
664 bank->sectors = NULL;
665 }
666
667 bank->base = base_address;
668 bank->size = num_pages * (1 << 11);
669 bank->num_sectors = num_pages;
670 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
671 if (!bank->sectors)
672 return ERROR_FAIL; /* Checkme: What better error to use?*/
673
674 for (i = 0; i < num_pages; i++) {
675 bank->sectors[i].offset = i << 11;
676 bank->sectors[i].size = 1 << 11;
677 bank->sectors[i].is_erased = -1;
678 bank->sectors[i].is_protected = 1;
679 }
680
681 stm32l4_info->probed = 1;
682
683 return ERROR_OK;
684 }
685
686 static int stm32l4_auto_probe(struct flash_bank *bank)
687 {
688 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
689 if (stm32l4_info->probed)
690 return ERROR_OK;
691 return stm32l4_probe(bank);
692 }
693
694 static int get_stm32l4_info(struct flash_bank *bank, char *buf, int buf_size)
695 {
696 struct target *target = bank->target;
697 uint32_t dbgmcu_idcode;
698
699 /* read stm32 device id register */
700 int retval = target_read_u32(target, DBGMCU_IDCODE, &dbgmcu_idcode);
701 if (retval != ERROR_OK)
702 return retval;
703
704 uint16_t device_id = dbgmcu_idcode & 0xfff;
705 uint8_t rev_id = dbgmcu_idcode >> 28;
706 uint8_t rev_minor = 0;
707 int i;
708
709 for (i = 16; i < 28; i++) {
710 if (dbgmcu_idcode & (1 << i))
711 rev_minor++;
712 else
713 break;
714 }
715
716 const char *device_str;
717
718 switch (device_id) {
719 case 0x461:
720 device_str = "STM32L496/4A6";
721 break;
722
723 case 0x415:
724 device_str = "STM32L475/476/486";
725 break;
726
727 case 0x462:
728 device_str = "STM32L45x/46x";
729 break;
730
731 case 0x435:
732 device_str = "STM32L43x/44x";
733 break;
734
735 default:
736 snprintf(buf, buf_size, "Cannot identify target as a STM32L4\n");
737 return ERROR_FAIL;
738 }
739
740 snprintf(buf, buf_size, "%s - Rev: %1d.%02d",
741 device_str, rev_id, rev_minor);
742
743 return ERROR_OK;
744 }
745
746 COMMAND_HANDLER(stm32l4_handle_lock_command)
747 {
748 struct target *target = NULL;
749 struct stm32l4_flash_bank *stm32l4_info = NULL;
750
751 if (CMD_ARGC < 1)
752 return ERROR_COMMAND_SYNTAX_ERROR;
753
754 struct flash_bank *bank;
755 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
756 if (ERROR_OK != retval)
757 return retval;
758
759 stm32l4_info = bank->driver_priv;
760 target = bank->target;
761
762 if (target->state != TARGET_HALTED) {
763 LOG_ERROR("Target not halted");
764 return ERROR_TARGET_NOT_HALTED;
765 }
766
767 if (stm32l4_read_options(bank) != ERROR_OK) {
768 command_print(CMD_CTX, "%s failed to read options",
769 bank->driver->name);
770 return ERROR_OK;
771 }
772
773 /* set readout protection */
774 stm32l4_info->option_bytes.RDP = 0;
775
776 if (stm32l4_write_options(bank) != ERROR_OK) {
777 command_print(CMD_CTX, "%s failed to lock device", bank->driver->name);
778 return ERROR_OK;
779 }
780
781 command_print(CMD_CTX, "%s locked", bank->driver->name);
782
783 return ERROR_OK;
784 }
785
786 COMMAND_HANDLER(stm32l4_handle_unlock_command)
787 {
788 struct target *target = NULL;
789 struct stm32l4_flash_bank *stm32l4_info = NULL;
790
791 if (CMD_ARGC < 1)
792 return ERROR_COMMAND_SYNTAX_ERROR;
793
794 struct flash_bank *bank;
795 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
796 if (ERROR_OK != retval)
797 return retval;
798
799 stm32l4_info = bank->driver_priv;
800 target = bank->target;
801
802 if (target->state != TARGET_HALTED) {
803 LOG_ERROR("Target not halted");
804 return ERROR_TARGET_NOT_HALTED;
805 }
806
807 if (stm32l4_read_options(bank) != ERROR_OK) {
808 command_print(CMD_CTX, "%s failed to read options", bank->driver->name);
809 return ERROR_OK;
810 }
811
812 /* clear readout protection and complementary option bytes
813 * this will also force a device unlock if set */
814 stm32l4_info->option_bytes.RDP = 0xAA;
815
816 if (stm32l4_write_options(bank) != ERROR_OK) {
817 command_print(CMD_CTX, "%s failed to unlock device",
818 bank->driver->name);
819 return ERROR_OK;
820 }
821
822 command_print(CMD_CTX, "%s unlocked.\n"
823 "INFO: a reset or power cycle is required "
824 "for the new settings to take effect.", bank->driver->name);
825
826 return ERROR_OK;
827 }
828
829 static int stm32l4_mass_erase(struct flash_bank *bank, uint32_t action)
830 {
831 int retval;
832 struct target *target = bank->target;
833
834 if (target->state != TARGET_HALTED) {
835 LOG_ERROR("Target not halted");
836 return ERROR_TARGET_NOT_HALTED;
837 }
838
839 retval = stm32l4_unlock_reg(target);
840 if (retval != ERROR_OK)
841 return retval;
842
843 /* mass erase flash memory */
844 retval = target_write_u32(
845 target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), action);
846 if (retval != ERROR_OK)
847 return retval;
848 retval = target_write_u32(
849 target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR),
850 action | FLASH_STRT);
851 if (retval != ERROR_OK)
852 return retval;
853
854 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
855 if (retval != ERROR_OK)
856 return retval;
857
858 retval = target_write_u32(
859 target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
860 if (retval != ERROR_OK)
861 return retval;
862
863 return ERROR_OK;
864 }
865
866 COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
867 {
868 int i;
869 uint32_t action;
870
871 if (CMD_ARGC < 1) {
872 command_print(CMD_CTX, "stm32x mass_erase <STM32L4 bank>");
873 return ERROR_COMMAND_SYNTAX_ERROR;
874 }
875
876 struct flash_bank *bank;
877 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
878 if (ERROR_OK != retval)
879 return retval;
880
881 action = FLASH_MER1 | FLASH_MER2;
882 retval = stm32l4_mass_erase(bank, action);
883 if (retval == ERROR_OK) {
884 /* set all sectors as erased */
885 for (i = 0; i < bank->num_sectors; i++)
886 bank->sectors[i].is_erased = 1;
887
888 command_print(CMD_CTX, "stm32x mass erase complete");
889 } else {
890 command_print(CMD_CTX, "stm32x mass erase failed");
891 }
892
893 return retval;
894 }
895
896 static const struct command_registration stm32l4_exec_command_handlers[] = {
897 {
898 .name = "lock",
899 .handler = stm32l4_handle_lock_command,
900 .mode = COMMAND_EXEC,
901 .usage = "bank_id",
902 .help = "Lock entire flash device.",
903 },
904 {
905 .name = "unlock",
906 .handler = stm32l4_handle_unlock_command,
907 .mode = COMMAND_EXEC,
908 .usage = "bank_id",
909 .help = "Unlock entire protected flash device.",
910 },
911 {
912 .name = "mass_erase",
913 .handler = stm32l4_handle_mass_erase_command,
914 .mode = COMMAND_EXEC,
915 .usage = "bank_id",
916 .help = "Erase entire flash device.",
917 },
918 COMMAND_REGISTRATION_DONE
919 };
920
921 static const struct command_registration stm32l4_command_handlers[] = {
922 {
923 .name = "stm32l4x",
924 .mode = COMMAND_ANY,
925 .help = "stm32l4x flash command group",
926 .usage = "",
927 .chain = stm32l4_exec_command_handlers,
928 },
929 COMMAND_REGISTRATION_DONE
930 };
931
932 struct flash_driver stm32l4x_flash = {
933 .name = "stm32l4x",
934 .commands = stm32l4_command_handlers,
935 .flash_bank_command = stm32l4_flash_bank_command,
936 .erase = stm32l4_erase,
937 .protect = stm32l4_protect,
938 .write = stm32l4_write,
939 .read = default_flash_read,
940 .probe = stm32l4_probe,
941 .auto_probe = stm32l4_auto_probe,
942 .erase_check = default_flash_blank_check,
943 .protect_check = stm32l4_protect_check,
944 .info = get_stm32l4_info,
945 .free_driver_priv = default_flash_free_driver_priv,
946 };
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