1 /***************************************************************************
2 * Copyright (C) 2015 by Uwe Bonnes *
3 * bon@elektron.ikp.physik.tu-darmstadt.de *
5 * Copyright (C) 2019 by Tarek Bochkati for STMicroelectronics *
6 * tarek.bouchkati@gmail.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
20 ***************************************************************************/
27 #include <helper/binarybuffer.h>
28 #include <target/algorithm.h>
29 #include <target/armv7m.h>
33 /* STM32L4xxx series for reference.
35 * RM0351 (STM32L4x5/STM32L4x6)
36 * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
38 * RM0394 (STM32L43x/44x/45x/46x)
39 * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
41 * RM0432 (STM32L4R/4Sxx)
42 * http://www.st.com/resource/en/reference_manual/dm00310109.pdf
44 * STM32L476RG Datasheet (for erase timing)
45 * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
47 * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
48 * an option byte is available to map all sectors to the first bank.
49 * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
52 * RM0394 devices have a single bank only.
54 * RM0432 devices have single and dual bank operating modes.
55 * - for STM32L4R/Sxx the FLASH size is 2Mbyte or 1Mbyte.
56 * - for STM32L4P/Q5x the FLASH size is 1Mbyte or 512Kbyte.
57 * Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
59 * Bank mode is controlled by two different bits in option bytes register.
61 * In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
62 * In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
64 * In 1M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
65 * In 512K FLASH devices bit 21 (DB512K) controls Dual Bank mode.
69 /* STM32WBxxx series for reference.
72 * http://www.st.com/resource/en/reference_manual/dm00318631.pdf
75 * http://www.st.com/resource/en/reference_manual/dm00622834.pdf
78 /* STM32WLxxx series for reference.
81 * http://www.st.com/resource/en/reference_manual/dm00530369.pdf
85 * STM32G0xxx series for reference.
88 * http://www.st.com/resource/en/reference_manual/dm00371828.pdf
91 * http://www.st.com/resource/en/reference_manual/dm00463896.pdf
95 * STM32G4xxx series for reference.
97 * RM0440 (STM32G43x/44x/47x/48x)
98 * http://www.st.com/resource/en/reference_manual/dm00355726.pdf
100 * Cat. 2 devices have single bank only, page size is 2kByte.
102 * Cat. 3 devices have single and dual bank operating modes,
103 * Page size is 2kByte (dual mode) or 4kByte (single mode).
105 * Bank mode is controlled by bit 22 (DBANK) in option bytes register.
106 * Both banks are treated as a single OpenOCD bank.
109 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
111 #define FLASH_ERASE_TIMEOUT 250
118 struct stm32l4_part_info
{
120 const char *device_str
;
121 const struct stm32l4_rev
*revs
;
122 const size_t num_revs
;
123 const uint16_t max_flash_size_kb
;
124 const bool has_dual_bank
;
125 const uint32_t flash_regs_base
;
126 const uint32_t fsize_addr
;
129 struct stm32l4_flash_bank
{
135 uint32_t user_bank_size
;
136 uint32_t wrpxxr_mask
;
137 const struct stm32l4_part_info
*part_info
;
140 /* human readable list of families this drivers supports */
141 static const char *device_families
= "STM32L4/L4+/WB/WL/G4/G0";
143 static const struct stm32l4_rev stm32_415_revs
[] = {
144 { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
147 static const struct stm32l4_rev stm32_435_revs
[] = {
148 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
151 static const struct stm32l4_rev stm32_460_revs
[] = {
152 { 0x1000, "A/Z" } /* A and Z, no typo in RM! */, { 0x2000, "B" },
155 static const struct stm32l4_rev stm32_461_revs
[] = {
156 { 0x1000, "A" }, { 0x2000, "B" },
159 static const struct stm32l4_rev stm32_462_revs
[] = {
160 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
163 static const struct stm32l4_rev stm32_464_revs
[] = {
164 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
167 static const struct stm32l4_rev stm32_466_revs
[] = {
168 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2000, "B" },
171 static const struct stm32l4_rev stm32_468_revs
[] = {
172 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
175 static const struct stm32l4_rev stm32_469_revs
[] = {
176 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
179 static const struct stm32l4_rev stm32_470_revs
[] = {
180 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" },
183 static const struct stm32l4_rev stm32_471_revs
[] = {
187 static const struct stm32l4_rev stm32_495_revs
[] = {
191 static const struct stm32l4_rev stm32_496_revs
[] = {
195 static const struct stm32l4_rev stm32_497_revs
[] = {
199 static const struct stm32l4_part_info stm32l4_parts
[] = {
202 .revs
= stm32_415_revs
,
203 .num_revs
= ARRAY_SIZE(stm32_415_revs
),
204 .device_str
= "STM32L47/L48xx",
205 .max_flash_size_kb
= 1024,
206 .has_dual_bank
= true,
207 .flash_regs_base
= 0x40022000,
208 .fsize_addr
= 0x1FFF75E0,
212 .revs
= stm32_435_revs
,
213 .num_revs
= ARRAY_SIZE(stm32_435_revs
),
214 .device_str
= "STM32L43/L44xx",
215 .max_flash_size_kb
= 256,
216 .has_dual_bank
= false,
217 .flash_regs_base
= 0x40022000,
218 .fsize_addr
= 0x1FFF75E0,
222 .revs
= stm32_460_revs
,
223 .num_revs
= ARRAY_SIZE(stm32_460_revs
),
224 .device_str
= "STM32G07/G08xx",
225 .max_flash_size_kb
= 128,
226 .has_dual_bank
= false,
227 .flash_regs_base
= 0x40022000,
228 .fsize_addr
= 0x1FFF75E0,
232 .revs
= stm32_461_revs
,
233 .num_revs
= ARRAY_SIZE(stm32_461_revs
),
234 .device_str
= "STM32L49/L4Axx",
235 .max_flash_size_kb
= 1024,
236 .has_dual_bank
= true,
237 .flash_regs_base
= 0x40022000,
238 .fsize_addr
= 0x1FFF75E0,
242 .revs
= stm32_462_revs
,
243 .num_revs
= ARRAY_SIZE(stm32_462_revs
),
244 .device_str
= "STM32L45/L46xx",
245 .max_flash_size_kb
= 512,
246 .has_dual_bank
= false,
247 .flash_regs_base
= 0x40022000,
248 .fsize_addr
= 0x1FFF75E0,
252 .revs
= stm32_464_revs
,
253 .num_revs
= ARRAY_SIZE(stm32_464_revs
),
254 .device_str
= "STM32L41/L42xx",
255 .max_flash_size_kb
= 128,
256 .has_dual_bank
= false,
257 .flash_regs_base
= 0x40022000,
258 .fsize_addr
= 0x1FFF75E0,
262 .revs
= stm32_466_revs
,
263 .num_revs
= ARRAY_SIZE(stm32_466_revs
),
264 .device_str
= "STM32G03/G04xx",
265 .max_flash_size_kb
= 64,
266 .has_dual_bank
= false,
267 .flash_regs_base
= 0x40022000,
268 .fsize_addr
= 0x1FFF75E0,
272 .revs
= stm32_468_revs
,
273 .num_revs
= ARRAY_SIZE(stm32_468_revs
),
274 .device_str
= "STM32G43/G44xx",
275 .max_flash_size_kb
= 128,
276 .has_dual_bank
= false,
277 .flash_regs_base
= 0x40022000,
278 .fsize_addr
= 0x1FFF75E0,
282 .revs
= stm32_469_revs
,
283 .num_revs
= ARRAY_SIZE(stm32_469_revs
),
284 .device_str
= "STM32G47/G48xx",
285 .max_flash_size_kb
= 512,
286 .has_dual_bank
= true,
287 .flash_regs_base
= 0x40022000,
288 .fsize_addr
= 0x1FFF75E0,
292 .revs
= stm32_470_revs
,
293 .num_revs
= ARRAY_SIZE(stm32_470_revs
),
294 .device_str
= "STM32L4R/L4Sxx",
295 .max_flash_size_kb
= 2048,
296 .has_dual_bank
= true,
297 .flash_regs_base
= 0x40022000,
298 .fsize_addr
= 0x1FFF75E0,
302 .revs
= stm32_471_revs
,
303 .num_revs
= ARRAY_SIZE(stm32_471_revs
),
304 .device_str
= "STM32L4P5/L4Q5x",
305 .max_flash_size_kb
= 1024,
306 .has_dual_bank
= true,
307 .flash_regs_base
= 0x40022000,
308 .fsize_addr
= 0x1FFF75E0,
312 .revs
= stm32_495_revs
,
313 .num_revs
= ARRAY_SIZE(stm32_495_revs
),
314 .device_str
= "STM32WB5x",
315 .max_flash_size_kb
= 1024,
316 .has_dual_bank
= false,
317 .flash_regs_base
= 0x58004000,
318 .fsize_addr
= 0x1FFF75E0,
322 .revs
= stm32_496_revs
,
323 .num_revs
= ARRAY_SIZE(stm32_496_revs
),
324 .device_str
= "STM32WB3x",
325 .max_flash_size_kb
= 512,
326 .has_dual_bank
= false,
327 .flash_regs_base
= 0x58004000,
328 .fsize_addr
= 0x1FFF75E0,
332 .revs
= stm32_497_revs
,
333 .num_revs
= ARRAY_SIZE(stm32_497_revs
),
334 .device_str
= "STM32WLEx",
335 .max_flash_size_kb
= 256,
336 .has_dual_bank
= false,
337 .flash_regs_base
= 0x58004000,
338 .fsize_addr
= 0x1FFF75E0,
342 /* flash bank stm32l4x <base> <size> 0 0 <target#> */
343 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command
)
345 struct stm32l4_flash_bank
*stm32l4_info
;
348 return ERROR_COMMAND_SYNTAX_ERROR
;
350 stm32l4_info
= malloc(sizeof(struct stm32l4_flash_bank
));
352 return ERROR_FAIL
; /* Checkme: What better error to use?*/
353 bank
->driver_priv
= stm32l4_info
;
355 /* The flash write must be aligned to a double word (8-bytes) boundary.
356 * Ask the flash infrastructure to ensure required alignment */
357 bank
->write_start_alignment
= bank
->write_end_alignment
= 8;
359 stm32l4_info
->probed
= false;
360 stm32l4_info
->user_bank_size
= bank
->size
;
365 static inline uint32_t stm32l4_get_flash_reg(struct flash_bank
*bank
, uint32_t reg_offset
)
367 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
368 return stm32l4_info
->part_info
->flash_regs_base
+ reg_offset
;
371 static inline int stm32l4_read_flash_reg(struct flash_bank
*bank
, uint32_t reg_offset
, uint32_t *value
)
373 return target_read_u32(bank
->target
, stm32l4_get_flash_reg(bank
, reg_offset
), value
);
376 static inline int stm32l4_write_flash_reg(struct flash_bank
*bank
, uint32_t reg_offset
, uint32_t value
)
378 return target_write_u32(bank
->target
, stm32l4_get_flash_reg(bank
, reg_offset
), value
);
381 static int stm32l4_wait_status_busy(struct flash_bank
*bank
, int timeout
)
384 int retval
= ERROR_OK
;
386 /* wait for busy to clear */
388 retval
= stm32l4_read_flash_reg(bank
, STM32_FLASH_SR
, &status
);
389 if (retval
!= ERROR_OK
)
391 LOG_DEBUG("status: 0x%" PRIx32
"", status
);
392 if ((status
& FLASH_BSY
) == 0)
394 if (timeout
-- <= 0) {
395 LOG_ERROR("timed out waiting for flash");
402 if (status
& FLASH_WRPERR
) {
403 LOG_ERROR("stm32x device protected");
407 /* Clear but report errors */
408 if (status
& FLASH_ERROR
) {
409 if (retval
== ERROR_OK
)
411 /* If this operation fails, we ignore it and report the original
414 stm32l4_write_flash_reg(bank
, STM32_FLASH_SR
, status
& FLASH_ERROR
);
420 static int stm32l4_unlock_reg(struct flash_bank
*bank
)
424 /* first check if not already unlocked
425 * otherwise writing on STM32_FLASH_KEYR will fail
427 int retval
= stm32l4_read_flash_reg(bank
, STM32_FLASH_CR
, &ctrl
);
428 if (retval
!= ERROR_OK
)
431 if ((ctrl
& FLASH_LOCK
) == 0)
434 /* unlock flash registers */
435 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_KEYR
, KEY1
);
436 if (retval
!= ERROR_OK
)
439 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_KEYR
, KEY2
);
440 if (retval
!= ERROR_OK
)
443 retval
= stm32l4_read_flash_reg(bank
, STM32_FLASH_CR
, &ctrl
);
444 if (retval
!= ERROR_OK
)
447 if (ctrl
& FLASH_LOCK
) {
448 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32
, ctrl
);
449 return ERROR_TARGET_FAILURE
;
455 static int stm32l4_unlock_option_reg(struct flash_bank
*bank
)
459 int retval
= stm32l4_read_flash_reg(bank
, STM32_FLASH_CR
, &ctrl
);
460 if (retval
!= ERROR_OK
)
463 if ((ctrl
& FLASH_OPTLOCK
) == 0)
466 /* unlock option registers */
467 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_OPTKEYR
, OPTKEY1
);
468 if (retval
!= ERROR_OK
)
471 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_OPTKEYR
, OPTKEY2
);
472 if (retval
!= ERROR_OK
)
475 retval
= stm32l4_read_flash_reg(bank
, STM32_FLASH_CR
, &ctrl
);
476 if (retval
!= ERROR_OK
)
479 if (ctrl
& FLASH_OPTLOCK
) {
480 LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32
, ctrl
);
481 return ERROR_TARGET_FAILURE
;
487 static int stm32l4_write_option(struct flash_bank
*bank
, uint32_t reg_offset
,
488 uint32_t value
, uint32_t mask
)
493 retval
= stm32l4_read_flash_reg(bank
, reg_offset
, &optiondata
);
494 if (retval
!= ERROR_OK
)
497 retval
= stm32l4_unlock_reg(bank
);
498 if (retval
!= ERROR_OK
)
501 retval
= stm32l4_unlock_option_reg(bank
);
502 if (retval
!= ERROR_OK
)
505 optiondata
= (optiondata
& ~mask
) | (value
& mask
);
507 retval
= stm32l4_write_flash_reg(bank
, reg_offset
, optiondata
);
508 if (retval
!= ERROR_OK
)
511 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, FLASH_OPTSTRT
);
512 if (retval
!= ERROR_OK
)
515 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
518 retval2
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, FLASH_LOCK
| FLASH_OPTLOCK
);
520 if (retval
!= ERROR_OK
)
526 static int stm32l4_protect_check(struct flash_bank
*bank
)
528 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
530 uint32_t wrp1ar
, wrp1br
, wrp2ar
, wrp2br
;
531 stm32l4_read_flash_reg(bank
, STM32_FLASH_WRP1AR
, &wrp1ar
);
532 stm32l4_read_flash_reg(bank
, STM32_FLASH_WRP1BR
, &wrp1br
);
533 if (stm32l4_info
->part_info
->has_dual_bank
) {
534 stm32l4_read_flash_reg(bank
, STM32_FLASH_WRP2AR
, &wrp2ar
);
535 stm32l4_read_flash_reg(bank
, STM32_FLASH_WRP2BR
, &wrp2br
);
537 /* prevent unintialized errors */
542 const uint8_t wrp1a_start
= wrp1ar
& stm32l4_info
->wrpxxr_mask
;
543 const uint8_t wrp1a_end
= (wrp1ar
>> 16) & stm32l4_info
->wrpxxr_mask
;
544 const uint8_t wrp1b_start
= wrp1br
& stm32l4_info
->wrpxxr_mask
;
545 const uint8_t wrp1b_end
= (wrp1br
>> 16) & stm32l4_info
->wrpxxr_mask
;
546 const uint8_t wrp2a_start
= wrp2ar
& stm32l4_info
->wrpxxr_mask
;
547 const uint8_t wrp2a_end
= (wrp2ar
>> 16) & stm32l4_info
->wrpxxr_mask
;
548 const uint8_t wrp2b_start
= wrp2br
& stm32l4_info
->wrpxxr_mask
;
549 const uint8_t wrp2b_end
= (wrp2br
>> 16) & stm32l4_info
->wrpxxr_mask
;
551 for (int i
= 0; i
< bank
->num_sectors
; i
++) {
552 if (i
< stm32l4_info
->bank1_sectors
) {
553 if (((i
>= wrp1a_start
) &&
555 ((i
>= wrp1b_start
) &&
557 bank
->sectors
[i
].is_protected
= 1;
559 bank
->sectors
[i
].is_protected
= 0;
561 assert(stm32l4_info
->part_info
->has_dual_bank
== true);
563 snb
= i
- stm32l4_info
->bank1_sectors
;
564 if (((snb
>= wrp2a_start
) &&
565 (snb
<= wrp2a_end
)) ||
566 ((snb
>= wrp2b_start
) &&
568 bank
->sectors
[i
].is_protected
= 1;
570 bank
->sectors
[i
].is_protected
= 0;
576 static int stm32l4_erase(struct flash_bank
*bank
, int first
, int last
)
578 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
582 assert((0 <= first
) && (first
<= last
) && (last
< bank
->num_sectors
));
584 if (bank
->target
->state
!= TARGET_HALTED
) {
585 LOG_ERROR("Target not halted");
586 return ERROR_TARGET_NOT_HALTED
;
589 retval
= stm32l4_unlock_reg(bank
);
590 if (retval
!= ERROR_OK
)
595 To erase a sector, follow the procedure below:
596 1. Check that no Flash memory operation is ongoing by
597 checking the BSY bit in the FLASH_SR register
598 2. Set the PER bit and select the page and bank
599 you wish to erase in the FLASH_CR register
600 3. Set the STRT bit in the FLASH_CR register
601 4. Wait for the BSY bit to be cleared
604 for (i
= first
; i
<= last
; i
++) {
605 uint32_t erase_flags
;
606 erase_flags
= FLASH_PER
| FLASH_STRT
;
608 if (i
>= stm32l4_info
->bank1_sectors
) {
610 snb
= i
- stm32l4_info
->bank1_sectors
;
611 erase_flags
|= snb
<< FLASH_PAGE_SHIFT
| FLASH_CR_BKER
;
613 erase_flags
|= i
<< FLASH_PAGE_SHIFT
;
614 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, erase_flags
);
615 if (retval
!= ERROR_OK
)
618 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
619 if (retval
!= ERROR_OK
)
622 bank
->sectors
[i
].is_erased
= 1;
626 retval2
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, FLASH_LOCK
);
628 if (retval
!= ERROR_OK
)
634 static int stm32l4_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
636 struct target
*target
= bank
->target
;
637 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
639 if (target
->state
!= TARGET_HALTED
) {
640 LOG_ERROR("Target not halted");
641 return ERROR_TARGET_NOT_HALTED
;
646 uint32_t reg_value
= 0xFF; /* Default to bank un-protected */
647 if (last
>= stm32l4_info
->bank1_sectors
) {
649 uint8_t begin
= first
> stm32l4_info
->bank1_sectors
? first
: 0x00;
650 reg_value
= ((last
& 0xFF) << 16) | begin
;
653 ret
= stm32l4_write_option(bank
, STM32_FLASH_WRP2AR
, reg_value
, 0xffffffff);
656 reg_value
= 0xFF; /* Default to bank un-protected */
657 if (first
< stm32l4_info
->bank1_sectors
) {
659 uint8_t end
= last
>= stm32l4_info
->bank1_sectors
? 0xFF : last
;
660 reg_value
= (end
<< 16) | (first
& 0xFF);
663 ret
= stm32l4_write_option(bank
, STM32_FLASH_WRP1AR
, reg_value
, 0xffffffff);
669 /* Count is in double-words */
670 static int stm32l4_write_block(struct flash_bank
*bank
, const uint8_t *buffer
,
671 uint32_t offset
, uint32_t count
)
673 struct target
*target
= bank
->target
;
674 uint32_t buffer_size
;
675 struct working_area
*write_algorithm
;
676 struct working_area
*source
;
677 uint32_t address
= bank
->base
+ offset
;
678 struct reg_param reg_params
[6];
679 struct armv7m_algorithm armv7m_info
;
680 int retval
= ERROR_OK
;
682 static const uint8_t stm32l4_flash_write_code
[] = {
683 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
686 if (target_alloc_working_area(target
, sizeof(stm32l4_flash_write_code
),
687 &write_algorithm
) != ERROR_OK
) {
688 LOG_WARNING("no working area available, can't do block memory writes");
689 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
692 retval
= target_write_buffer(target
, write_algorithm
->address
,
693 sizeof(stm32l4_flash_write_code
),
694 stm32l4_flash_write_code
);
695 if (retval
!= ERROR_OK
) {
696 target_free_working_area(target
, write_algorithm
);
700 /* memory buffer, size *must* be multiple of dword plus one dword for rp and one for wp */
701 buffer_size
= target_get_working_area_avail(target
) & ~(2 * sizeof(uint32_t) - 1);
702 if (buffer_size
< 256) {
703 LOG_WARNING("large enough working area not available, can't do block memory writes");
704 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
705 } else if (buffer_size
> 16384) {
706 /* probably won't benefit from more than 16k ... */
710 if (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
) {
711 LOG_ERROR("allocating working area failed");
712 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
715 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
716 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
718 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* buffer start, status (out) */
719 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* buffer end */
720 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* target address */
721 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
); /* count (double word-64bit) */
722 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
); /* flash status register */
723 init_reg_param(®_params
[5], "r5", 32, PARAM_OUT
); /* flash control register */
725 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
726 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
+ source
->size
);
727 buf_set_u32(reg_params
[2].value
, 0, 32, address
);
728 buf_set_u32(reg_params
[3].value
, 0, 32, count
);
729 buf_set_u32(reg_params
[4].value
, 0, 32, stm32l4_get_flash_reg(bank
, STM32_FLASH_SR
));
730 buf_set_u32(reg_params
[5].value
, 0, 32, stm32l4_get_flash_reg(bank
, STM32_FLASH_CR
));
732 retval
= target_run_flash_async_algorithm(target
, buffer
, count
, 8,
734 ARRAY_SIZE(reg_params
), reg_params
,
735 source
->address
, source
->size
,
736 write_algorithm
->address
, 0,
739 if (retval
== ERROR_FLASH_OPERATION_FAILED
) {
740 LOG_ERROR("error executing stm32l4 flash write algorithm");
742 uint32_t error
= buf_get_u32(reg_params
[0].value
, 0, 32) & FLASH_ERROR
;
744 if (error
& FLASH_WRPERR
)
745 LOG_ERROR("flash memory write protected");
748 LOG_ERROR("flash write failed = %08" PRIx32
, error
);
749 /* Clear but report errors */
750 stm32l4_write_flash_reg(bank
, STM32_FLASH_SR
, error
);
755 target_free_working_area(target
, source
);
756 target_free_working_area(target
, write_algorithm
);
758 destroy_reg_param(®_params
[0]);
759 destroy_reg_param(®_params
[1]);
760 destroy_reg_param(®_params
[2]);
761 destroy_reg_param(®_params
[3]);
762 destroy_reg_param(®_params
[4]);
763 destroy_reg_param(®_params
[5]);
768 static int stm32l4_write(struct flash_bank
*bank
, const uint8_t *buffer
,
769 uint32_t offset
, uint32_t count
)
771 int retval
= ERROR_OK
, retval2
;
773 if (bank
->target
->state
!= TARGET_HALTED
) {
774 LOG_ERROR("Target not halted");
775 return ERROR_TARGET_NOT_HALTED
;
778 /* The flash write must be aligned to a double word (8-bytes) boundary.
779 * The flash infrastructure ensures it, do just a security check */
780 assert(offset
% 8 == 0);
781 assert(count
% 8 == 0);
783 /* STM32G4xxx Cat. 3 devices may have gaps between banks, check whether
784 * data to be written does not go into a gap:
785 * suppose buffer is fully contained in bank from sector 0 to sector
786 * num->sectors - 1 and sectors are ordered according to offset
788 struct flash_sector
*head
= &bank
->sectors
[0];
789 struct flash_sector
*tail
= &bank
->sectors
[bank
->num_sectors
- 1];
791 while ((head
< tail
) && (offset
>= (head
+ 1)->offset
)) {
792 /* buffer does not intersect head nor gap behind head */
796 while ((head
< tail
) && (offset
+ count
<= (tail
- 1)->offset
+ (tail
- 1)->size
)) {
797 /* buffer does not intersect tail nor gap before tail */
801 LOG_DEBUG("data: 0x%08" PRIx32
" - 0x%08" PRIx32
", sectors: 0x%08" PRIx32
" - 0x%08" PRIx32
,
802 offset
, offset
+ count
- 1, head
->offset
, tail
->offset
+ tail
->size
- 1);
804 /* Now check that there is no gap from head to tail, this should work
805 * even for multiple or non-symmetric gaps
807 while (head
< tail
) {
808 if (head
->offset
+ head
->size
!= (head
+ 1)->offset
) {
809 LOG_ERROR("write into gap from " TARGET_ADDR_FMT
" to " TARGET_ADDR_FMT
,
810 bank
->base
+ head
->offset
+ head
->size
,
811 bank
->base
+ (head
+ 1)->offset
- 1);
812 retval
= ERROR_FLASH_DST_OUT_OF_BANK
;
817 if (retval
!= ERROR_OK
)
820 retval
= stm32l4_unlock_reg(bank
);
821 if (retval
!= ERROR_OK
)
824 retval
= stm32l4_write_block(bank
, buffer
, offset
, count
/ 8);
827 retval2
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, FLASH_LOCK
);
829 if (retval
!= ERROR_OK
) {
830 LOG_ERROR("block write failed");
836 static int stm32l4_read_idcode(struct flash_bank
*bank
, uint32_t *id
)
840 /* try stm32l4/l4+/wb/g4 id register first, then stm32g0 id register */
841 retval
= target_read_u32(bank
->target
, DBGMCU_IDCODE_L4_G4
, id
);
842 if ((retval
!= ERROR_OK
) || ((*id
& 0xfff) == 0) || ((*id
& 0xfff) == 0xfff)) {
843 retval
= target_read_u32(bank
->target
, DBGMCU_IDCODE_G0
, id
);
844 if ((retval
!= ERROR_OK
) || ((*id
& 0xfff) == 0) || ((*id
& 0xfff) == 0xfff)) {
845 LOG_ERROR("can't get device id");
846 return (retval
== ERROR_OK
) ? ERROR_FAIL
: retval
;
853 static int stm32l4_probe(struct flash_bank
*bank
)
855 struct target
*target
= bank
->target
;
856 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
857 const struct stm32l4_part_info
*part_info
;
858 uint16_t flash_size_kb
= 0xffff;
862 stm32l4_info
->probed
= false;
864 /* read stm32 device id registers */
865 int retval
= stm32l4_read_idcode(bank
, &stm32l4_info
->idcode
);
866 if (retval
!= ERROR_OK
)
869 device_id
= stm32l4_info
->idcode
& 0xFFF;
871 for (unsigned int n
= 0; n
< ARRAY_SIZE(stm32l4_parts
); n
++) {
872 if (device_id
== stm32l4_parts
[n
].id
)
873 stm32l4_info
->part_info
= &stm32l4_parts
[n
];
876 if (!stm32l4_info
->part_info
) {
877 LOG_WARNING("Cannot identify target as an %s family device.", device_families
);
881 part_info
= stm32l4_info
->part_info
;
883 char device_info
[1024];
884 retval
= bank
->driver
->info(bank
, device_info
, sizeof(device_info
));
885 if (retval
!= ERROR_OK
)
888 LOG_INFO("device idcode = 0x%08" PRIx32
" (%s)", stm32l4_info
->idcode
, device_info
);
890 /* get flash size from target. */
891 retval
= target_read_u16(target
, part_info
->fsize_addr
, &flash_size_kb
);
893 /* failed reading flash size or flash size invalid (early silicon),
894 * default to max target family */
895 if (retval
!= ERROR_OK
|| flash_size_kb
== 0xffff || flash_size_kb
== 0
896 || flash_size_kb
> part_info
->max_flash_size_kb
) {
897 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
898 part_info
->max_flash_size_kb
);
899 flash_size_kb
= part_info
->max_flash_size_kb
;
902 /* if the user sets the size manually then ignore the probed value
903 * this allows us to work around devices that have a invalid flash size register value */
904 if (stm32l4_info
->user_bank_size
) {
905 LOG_WARNING("overriding size register by configured bank size - MAY CAUSE TROUBLE");
906 flash_size_kb
= stm32l4_info
->user_bank_size
/ 1024;
909 LOG_INFO("flash size = %dkbytes", flash_size_kb
);
911 /* did we assign a flash size? */
912 assert((flash_size_kb
!= 0xffff) && flash_size_kb
);
914 /* read flash option register */
915 retval
= stm32l4_read_flash_reg(bank
, STM32_FLASH_OPTR
, &options
);
916 if (retval
!= ERROR_OK
)
919 stm32l4_info
->bank1_sectors
= 0;
920 stm32l4_info
->hole_sectors
= 0;
923 int page_size_kb
= 0;
925 stm32l4_info
->dual_bank_mode
= false;
928 case 0x415: /* STM32L47/L48xx */
929 case 0x461: /* STM32L49/L4Axx */
930 /* if flash size is max (1M) the device is always dual bank
931 * 0x415: has variants with 512K
932 * 0x461: has variants with 512 and 256
933 * for these variants:
934 * if DUAL_BANK = 0 -> single bank
935 * else -> dual bank without gap
936 * note: the page size is invariant
939 num_pages
= flash_size_kb
/ page_size_kb
;
940 stm32l4_info
->bank1_sectors
= num_pages
;
942 /* check DUAL_BANK bit[21] if the flash is less than 1M */
943 if (flash_size_kb
== 1024 || (options
& BIT(21))) {
944 stm32l4_info
->dual_bank_mode
= true;
945 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
948 case 0x435: /* STM32L43/L44xx */
949 case 0x460: /* STM32G07/G08xx */
950 case 0x462: /* STM32L45/L46xx */
951 case 0x464: /* STM32L41/L42xx */
952 case 0x466: /* STM32G03/G04xx */
953 case 0x468: /* STM32G43/G44xx */
954 case 0x497: /* STM32WLEx */
955 /* single bank flash */
957 num_pages
= flash_size_kb
/ page_size_kb
;
958 stm32l4_info
->bank1_sectors
= num_pages
;
960 case 0x469: /* STM32G47/G48xx */
961 /* STM32G47/8 can be single/dual bank:
962 * if DUAL_BANK = 0 -> single bank
963 * else -> dual bank WITH gap
966 num_pages
= flash_size_kb
/ page_size_kb
;
967 stm32l4_info
->bank1_sectors
= num_pages
;
968 if (options
& BIT(22)) {
969 stm32l4_info
->dual_bank_mode
= true;
971 num_pages
= flash_size_kb
/ page_size_kb
;
972 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
974 /* for devices with trimmed flash, there is a gap between both banks */
975 stm32l4_info
->hole_sectors
=
976 (part_info
->max_flash_size_kb
- flash_size_kb
) / (2 * page_size_kb
);
979 case 0x470: /* STM32L4R/L4Sxx */
980 case 0x471: /* STM32L4P5/L4Q5x */
981 /* STM32L4R/S can be single/dual bank:
982 * if size = 2M check DBANK bit(22)
983 * if size = 1M check DB1M bit(21)
984 * STM32L4P/Q can be single/dual bank
985 * if size = 1M check DBANK bit(22)
986 * if size = 512K check DB512K bit(21)
989 num_pages
= flash_size_kb
/ page_size_kb
;
990 stm32l4_info
->bank1_sectors
= num_pages
;
991 const bool use_dbank_bit
= flash_size_kb
== part_info
->max_flash_size_kb
;
992 if ((use_dbank_bit
&& (options
& BIT(22))) ||
993 (!use_dbank_bit
&& (options
& BIT(21)))) {
994 stm32l4_info
->dual_bank_mode
= true;
996 num_pages
= flash_size_kb
/ page_size_kb
;
997 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
1000 case 0x495: /* STM32WB5x */
1001 case 0x496: /* STM32WB3x */
1002 /* single bank flash */
1004 num_pages
= flash_size_kb
/ page_size_kb
;
1005 stm32l4_info
->bank1_sectors
= num_pages
;
1008 LOG_ERROR("unsupported device");
1012 LOG_INFO("flash mode : %s-bank", stm32l4_info
->dual_bank_mode
? "dual" : "single");
1014 const int gap_size_kb
= stm32l4_info
->hole_sectors
* page_size_kb
;
1016 if (gap_size_kb
!= 0) {
1017 LOG_INFO("gap detected from 0x%08" PRIx32
" to 0x%08" PRIx32
,
1018 STM32_FLASH_BANK_BASE
+ stm32l4_info
->bank1_sectors
1019 * page_size_kb
* 1024,
1020 STM32_FLASH_BANK_BASE
+ (stm32l4_info
->bank1_sectors
1021 * page_size_kb
+ gap_size_kb
) * 1024 - 1);
1024 /* number of significant bits in WRPxxR differs per device,
1025 * always right adjusted, on some devices non-implemented
1026 * bits read as '0', on others as '1' ...
1027 * notably G4 Cat. 2 implement only 6 bits, contradicting the RM
1030 /* use *max_flash_size* instead of actual size as the trimmed versions
1031 * certainly use the same number of bits
1032 * max_flash_size is always power of two, so max_pages too
1034 uint32_t max_pages
= stm32l4_info
->part_info
->max_flash_size_kb
/ page_size_kb
;
1035 assert((max_pages
& (max_pages
- 1)) == 0);
1037 /* in dual bank mode number of pages is doubled, but extra bit is bank selection */
1038 stm32l4_info
->wrpxxr_mask
= ((max_pages
>> (stm32l4_info
->dual_bank_mode
? 1 : 0)) - 1);
1039 assert((stm32l4_info
->wrpxxr_mask
& 0xFFFF0000) == 0);
1040 LOG_DEBUG("WRPxxR mask 0x%04" PRIx16
, (uint16_t)stm32l4_info
->wrpxxr_mask
);
1042 if (bank
->sectors
) {
1043 free(bank
->sectors
);
1044 bank
->sectors
= NULL
;
1047 bank
->size
= (flash_size_kb
+ gap_size_kb
) * 1024;
1048 bank
->base
= STM32_FLASH_BANK_BASE
;
1049 bank
->num_sectors
= num_pages
;
1050 bank
->sectors
= malloc(sizeof(struct flash_sector
) * bank
->num_sectors
);
1051 if (bank
->sectors
== NULL
) {
1052 LOG_ERROR("failed to allocate bank sectors");
1056 for (int i
= 0; i
< bank
->num_sectors
; i
++) {
1057 bank
->sectors
[i
].offset
= i
* page_size_kb
* 1024;
1058 /* in dual bank configuration, if there is a gap between banks
1059 * we fix up the sector offset to consider this gap */
1060 if (i
>= stm32l4_info
->bank1_sectors
&& stm32l4_info
->hole_sectors
)
1061 bank
->sectors
[i
].offset
+= gap_size_kb
* 1024;
1062 bank
->sectors
[i
].size
= page_size_kb
* 1024;
1063 bank
->sectors
[i
].is_erased
= -1;
1064 bank
->sectors
[i
].is_protected
= 1;
1067 stm32l4_info
->probed
= true;
1071 static int stm32l4_auto_probe(struct flash_bank
*bank
)
1073 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1074 if (stm32l4_info
->probed
)
1077 return stm32l4_probe(bank
);
1080 static int get_stm32l4_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
1082 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1083 const struct stm32l4_part_info
*part_info
= stm32l4_info
->part_info
;
1086 const char *rev_str
= NULL
;
1087 uint16_t rev_id
= stm32l4_info
->idcode
>> 16;
1088 for (unsigned int i
= 0; i
< part_info
->num_revs
; i
++) {
1089 if (rev_id
== part_info
->revs
[i
].rev
) {
1090 rev_str
= part_info
->revs
[i
].str
;
1092 if (rev_str
!= NULL
) {
1093 snprintf(buf
, buf_size
, "%s - Rev: %s%s",
1094 part_info
->device_str
, rev_str
, stm32l4_info
->probed
?
1095 (stm32l4_info
->dual_bank_mode
? " dual-bank" : " single-bank") : "");
1101 snprintf(buf
, buf_size
, "%s - Rev: unknown (0x%04x)%s",
1102 part_info
->device_str
, rev_id
, stm32l4_info
->probed
?
1103 (stm32l4_info
->dual_bank_mode
? " dual-bank" : " single-bank") : "");
1106 snprintf(buf
, buf_size
, "Cannot identify target as an %s device", device_families
);
1113 static int stm32l4_mass_erase(struct flash_bank
*bank
)
1115 int retval
, retval2
;
1116 struct target
*target
= bank
->target
;
1117 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1119 uint32_t action
= FLASH_MER1
;
1121 if (stm32l4_info
->part_info
->has_dual_bank
)
1122 action
|= FLASH_MER2
;
1124 if (target
->state
!= TARGET_HALTED
) {
1125 LOG_ERROR("Target not halted");
1126 return ERROR_TARGET_NOT_HALTED
;
1129 retval
= stm32l4_unlock_reg(bank
);
1130 if (retval
!= ERROR_OK
)
1133 /* mass erase flash memory */
1134 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
/ 10);
1135 if (retval
!= ERROR_OK
)
1138 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, action
);
1139 if (retval
!= ERROR_OK
)
1142 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, action
| FLASH_STRT
);
1143 if (retval
!= ERROR_OK
)
1146 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
1149 retval2
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, FLASH_LOCK
);
1151 if (retval
!= ERROR_OK
)
1157 COMMAND_HANDLER(stm32l4_handle_mass_erase_command
)
1160 command_print(CMD
, "stm32l4x mass_erase <STM32L4 bank>");
1161 return ERROR_COMMAND_SYNTAX_ERROR
;
1164 struct flash_bank
*bank
;
1165 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1166 if (ERROR_OK
!= retval
)
1169 retval
= stm32l4_mass_erase(bank
);
1170 if (retval
== ERROR_OK
) {
1171 /* set all sectors as erased */
1172 for (int i
= 0; i
< bank
->num_sectors
; i
++)
1173 bank
->sectors
[i
].is_erased
= 1;
1175 command_print(CMD
, "stm32l4x mass erase complete");
1177 command_print(CMD
, "stm32l4x mass erase failed");
1183 COMMAND_HANDLER(stm32l4_handle_option_read_command
)
1186 command_print(CMD
, "stm32l4x option_read <STM32L4 bank> <option_reg offset>");
1187 return ERROR_COMMAND_SYNTAX_ERROR
;
1190 struct flash_bank
*bank
;
1191 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1192 if (ERROR_OK
!= retval
)
1195 uint32_t reg_offset
, reg_addr
;
1198 reg_offset
= strtoul(CMD_ARGV
[1], NULL
, 16);
1199 reg_addr
= stm32l4_get_flash_reg(bank
, reg_offset
);
1201 retval
= stm32l4_read_flash_reg(bank
, reg_offset
, &value
);
1202 if (ERROR_OK
!= retval
)
1205 command_print(CMD
, "Option Register: <0x%" PRIx32
"> = 0x%" PRIx32
"", reg_addr
, value
);
1210 COMMAND_HANDLER(stm32l4_handle_option_write_command
)
1213 command_print(CMD
, "stm32l4x option_write <STM32L4 bank> <option_reg offset> <value> [mask]");
1214 return ERROR_COMMAND_SYNTAX_ERROR
;
1217 struct flash_bank
*bank
;
1218 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1219 if (ERROR_OK
!= retval
)
1222 uint32_t reg_offset
;
1224 uint32_t mask
= 0xFFFFFFFF;
1226 reg_offset
= strtoul(CMD_ARGV
[1], NULL
, 16);
1227 value
= strtoul(CMD_ARGV
[2], NULL
, 16);
1229 mask
= strtoul(CMD_ARGV
[3], NULL
, 16);
1231 command_print(CMD
, "%s Option written.\n"
1232 "INFO: a reset or power cycle is required "
1233 "for the new settings to take effect.", bank
->driver
->name
);
1235 retval
= stm32l4_write_option(bank
, reg_offset
, value
, mask
);
1239 COMMAND_HANDLER(stm32l4_handle_option_load_command
)
1242 return ERROR_COMMAND_SYNTAX_ERROR
;
1244 struct flash_bank
*bank
;
1245 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1246 if (ERROR_OK
!= retval
)
1249 retval
= stm32l4_unlock_reg(bank
);
1250 if (ERROR_OK
!= retval
)
1253 retval
= stm32l4_unlock_option_reg(bank
);
1254 if (ERROR_OK
!= retval
)
1257 /* Set OBL_LAUNCH bit in CR -> system reset and option bytes reload,
1258 * but the RMs explicitly do *NOT* list this as power-on reset cause, and:
1259 * "Note: If the read protection is set while the debugger is still
1260 * connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset."
1262 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, FLASH_OBL_LAUNCH
);
1264 command_print(CMD
, "stm32l4x option load completed. Power-on reset might be required");
1266 /* Need to re-probe after change */
1267 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1268 stm32l4_info
->probed
= false;
1273 COMMAND_HANDLER(stm32l4_handle_lock_command
)
1275 struct target
*target
= NULL
;
1278 return ERROR_COMMAND_SYNTAX_ERROR
;
1280 struct flash_bank
*bank
;
1281 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1282 if (ERROR_OK
!= retval
)
1285 target
= bank
->target
;
1287 if (target
->state
!= TARGET_HALTED
) {
1288 LOG_ERROR("Target not halted");
1289 return ERROR_TARGET_NOT_HALTED
;
1292 /* set readout protection level 1 by erasing the RDP option byte */
1293 if (stm32l4_write_option(bank
, STM32_FLASH_OPTR
, 0, 0x000000FF) != ERROR_OK
) {
1294 command_print(CMD
, "%s failed to lock device", bank
->driver
->name
);
1301 COMMAND_HANDLER(stm32l4_handle_unlock_command
)
1303 struct target
*target
= NULL
;
1306 return ERROR_COMMAND_SYNTAX_ERROR
;
1308 struct flash_bank
*bank
;
1309 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1310 if (ERROR_OK
!= retval
)
1313 target
= bank
->target
;
1315 if (target
->state
!= TARGET_HALTED
) {
1316 LOG_ERROR("Target not halted");
1317 return ERROR_TARGET_NOT_HALTED
;
1320 if (stm32l4_write_option(bank
, STM32_FLASH_OPTR
, RDP_LEVEL_0
, 0x000000FF) != ERROR_OK
) {
1321 command_print(CMD
, "%s failed to unlock device", bank
->driver
->name
);
1328 static const struct command_registration stm32l4_exec_command_handlers
[] = {
1331 .handler
= stm32l4_handle_lock_command
,
1332 .mode
= COMMAND_EXEC
,
1334 .help
= "Lock entire flash device.",
1338 .handler
= stm32l4_handle_unlock_command
,
1339 .mode
= COMMAND_EXEC
,
1341 .help
= "Unlock entire protected flash device.",
1344 .name
= "mass_erase",
1345 .handler
= stm32l4_handle_mass_erase_command
,
1346 .mode
= COMMAND_EXEC
,
1348 .help
= "Erase entire flash device.",
1351 .name
= "option_read",
1352 .handler
= stm32l4_handle_option_read_command
,
1353 .mode
= COMMAND_EXEC
,
1354 .usage
= "bank_id reg_offset",
1355 .help
= "Read & Display device option bytes.",
1358 .name
= "option_write",
1359 .handler
= stm32l4_handle_option_write_command
,
1360 .mode
= COMMAND_EXEC
,
1361 .usage
= "bank_id reg_offset value mask",
1362 .help
= "Write device option bit fields with provided value.",
1365 .name
= "option_load",
1366 .handler
= stm32l4_handle_option_load_command
,
1367 .mode
= COMMAND_EXEC
,
1369 .help
= "Force re-load of device options (will cause device reset).",
1371 COMMAND_REGISTRATION_DONE
1374 static const struct command_registration stm32l4_command_handlers
[] = {
1377 .mode
= COMMAND_ANY
,
1378 .help
= "stm32l4x flash command group",
1380 .chain
= stm32l4_exec_command_handlers
,
1382 COMMAND_REGISTRATION_DONE
1385 const struct flash_driver stm32l4x_flash
= {
1387 .commands
= stm32l4_command_handlers
,
1388 .flash_bank_command
= stm32l4_flash_bank_command
,
1389 .erase
= stm32l4_erase
,
1390 .protect
= stm32l4_protect
,
1391 .write
= stm32l4_write
,
1392 .read
= default_flash_read
,
1393 .probe
= stm32l4_probe
,
1394 .auto_probe
= stm32l4_auto_probe
,
1395 .erase_check
= default_flash_blank_check
,
1396 .protect_check
= stm32l4_protect_check
,
1397 .info
= get_stm32l4_info
,
1398 .free_driver_priv
= default_flash_free_driver_priv
,
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