1 /***************************************************************************
2 * Copyright (C) 2015 by Uwe Bonnes *
3 * bon@elektron.ikp.physik.tu-darmstadt.de *
5 * Copyright (C) 2019 by Tarek Bochkati for STMicroelectronics *
6 * tarek.bouchkati@gmail.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
20 ***************************************************************************/
27 #include <helper/align.h>
28 #include <helper/binarybuffer.h>
29 #include <target/algorithm.h>
30 #include <target/armv7m.h>
34 /* STM32L4xxx series for reference.
36 * RM0351 (STM32L4x5/STM32L4x6)
37 * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
39 * RM0394 (STM32L43x/44x/45x/46x)
40 * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
42 * RM0432 (STM32L4R/4Sxx)
43 * http://www.st.com/resource/en/reference_manual/dm00310109.pdf
45 * STM32L476RG Datasheet (for erase timing)
46 * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
48 * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
49 * an option byte is available to map all sectors to the first bank.
50 * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
53 * RM0394 devices have a single bank only.
55 * RM0432 devices have single and dual bank operating modes.
56 * - for STM32L4R/Sxx the FLASH size is 2Mbyte or 1Mbyte.
57 * - for STM32L4P/Q5x the FLASH size is 1Mbyte or 512Kbyte.
58 * Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
60 * Bank mode is controlled by two different bits in option bytes register.
62 * In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
63 * In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
65 * In 1M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
66 * In 512K FLASH devices bit 21 (DB512K) controls Dual Bank mode.
70 /* STM32WBxxx series for reference.
73 * http://www.st.com/resource/en/reference_manual/dm00318631.pdf
76 * http://www.st.com/resource/en/reference_manual/dm00622834.pdf
79 /* STM32WLxxx series for reference.
82 * http://www.st.com/resource/en/reference_manual/dm00530369.pdf
85 /* STM32G0xxx series for reference.
88 * http://www.st.com/resource/en/reference_manual/dm00371828.pdf
91 * http://www.st.com/resource/en/reference_manual/dm00463896.pdf
94 /* STM32G4xxx series for reference.
96 * RM0440 (STM32G43x/44x/47x/48x/49x/4Ax)
97 * http://www.st.com/resource/en/reference_manual/dm00355726.pdf
99 * Cat. 2 devices have single bank only, page size is 2kByte.
101 * Cat. 3 devices have single and dual bank operating modes,
102 * Page size is 2kByte (dual mode) or 4kByte (single mode).
104 * Bank mode is controlled by bit 22 (DBANK) in option bytes register.
105 * Both banks are treated as a single OpenOCD bank.
107 * Cat. 4 devices have single bank only, page size is 2kByte.
110 /* STM32L5xxx series for reference.
112 * RM0428 (STM32L552xx/STM32L562xx)
113 * http://www.st.com/resource/en/reference_manual/dm00346336.pdf
116 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
118 #define FLASH_ERASE_TIMEOUT 250
121 /* relevant STM32L4 flags ****************************************************/
123 /* this flag indicates if the device flash is with dual bank architecture */
124 #define F_HAS_DUAL_BANK BIT(0)
125 /* this flags is used for dual bank devices only, it indicates if the
126 * 4 WRPxx are usable if the device is configured in single-bank mode */
127 #define F_USE_ALL_WRPXX BIT(1)
128 /* this flag indicates if the device embeds a TrustZone security feature */
129 #define F_HAS_TZ BIT(2)
130 /* this flag indicates if the device has the same flash registers as STM32L5 */
131 #define F_HAS_L5_FLASH_REGS BIT(3)
132 /* end of STM32L4 flags ******************************************************/
135 enum stm32l4_flash_reg_index
{
136 STM32_FLASH_ACR_INDEX
,
137 STM32_FLASH_KEYR_INDEX
,
138 STM32_FLASH_OPTKEYR_INDEX
,
139 STM32_FLASH_SR_INDEX
,
140 STM32_FLASH_CR_INDEX
,
141 STM32_FLASH_OPTR_INDEX
,
142 STM32_FLASH_WRP1AR_INDEX
,
143 STM32_FLASH_WRP1BR_INDEX
,
144 STM32_FLASH_WRP2AR_INDEX
,
145 STM32_FLASH_WRP2BR_INDEX
,
146 STM32_FLASH_REG_INDEX_NUM
,
151 RDP_LEVEL_0_5
= 0x55, /* for devices with TrustZone enabled */
156 static const uint32_t stm32l4_flash_regs
[STM32_FLASH_REG_INDEX_NUM
] = {
157 [STM32_FLASH_ACR_INDEX
] = 0x000,
158 [STM32_FLASH_KEYR_INDEX
] = 0x008,
159 [STM32_FLASH_OPTKEYR_INDEX
] = 0x00C,
160 [STM32_FLASH_SR_INDEX
] = 0x010,
161 [STM32_FLASH_CR_INDEX
] = 0x014,
162 [STM32_FLASH_OPTR_INDEX
] = 0x020,
163 [STM32_FLASH_WRP1AR_INDEX
] = 0x02C,
164 [STM32_FLASH_WRP1BR_INDEX
] = 0x030,
165 [STM32_FLASH_WRP2AR_INDEX
] = 0x04C,
166 [STM32_FLASH_WRP2BR_INDEX
] = 0x050,
169 static const uint32_t stm32l5_ns_flash_regs
[STM32_FLASH_REG_INDEX_NUM
] = {
170 [STM32_FLASH_ACR_INDEX
] = 0x000,
171 [STM32_FLASH_KEYR_INDEX
] = 0x008, /* NSKEYR */
172 [STM32_FLASH_OPTKEYR_INDEX
] = 0x010,
173 [STM32_FLASH_SR_INDEX
] = 0x020, /* NSSR */
174 [STM32_FLASH_CR_INDEX
] = 0x028, /* NSCR */
175 [STM32_FLASH_OPTR_INDEX
] = 0x040,
176 [STM32_FLASH_WRP1AR_INDEX
] = 0x058,
177 [STM32_FLASH_WRP1BR_INDEX
] = 0x05C,
178 [STM32_FLASH_WRP2AR_INDEX
] = 0x068,
179 [STM32_FLASH_WRP2BR_INDEX
] = 0x06C,
182 static const uint32_t stm32l5_s_flash_regs
[STM32_FLASH_REG_INDEX_NUM
] = {
183 [STM32_FLASH_ACR_INDEX
] = 0x000,
184 [STM32_FLASH_KEYR_INDEX
] = 0x00C, /* SECKEYR */
185 [STM32_FLASH_OPTKEYR_INDEX
] = 0x010,
186 [STM32_FLASH_SR_INDEX
] = 0x024, /* SECSR */
187 [STM32_FLASH_CR_INDEX
] = 0x02C, /* SECCR */
188 [STM32_FLASH_OPTR_INDEX
] = 0x040,
189 [STM32_FLASH_WRP1AR_INDEX
] = 0x058,
190 [STM32_FLASH_WRP1BR_INDEX
] = 0x05C,
191 [STM32_FLASH_WRP2AR_INDEX
] = 0x068,
192 [STM32_FLASH_WRP2BR_INDEX
] = 0x06C,
200 struct stm32l4_part_info
{
202 const char *device_str
;
203 const struct stm32l4_rev
*revs
;
204 const size_t num_revs
;
205 const uint16_t max_flash_size_kb
;
206 const uint32_t flags
; /* one bit per feature, see STM32L4 flags: macros F_XXX */
207 const uint32_t flash_regs_base
;
208 const uint32_t *default_flash_regs
;
209 const uint32_t fsize_addr
;
210 const uint32_t otp_base
;
211 const uint32_t otp_size
;
214 struct stm32l4_flash_bank
{
217 unsigned int bank1_sectors
;
220 uint32_t user_bank_size
;
221 uint32_t wrpxxr_mask
;
222 const struct stm32l4_part_info
*part_info
;
223 uint32_t flash_regs_base
;
224 const uint32_t *flash_regs
;
226 enum stm32l4_rdp rdp
;
238 enum stm32l4_flash_reg_index reg_idx
;
246 /* human readable list of families this drivers supports (sorted alphabetically) */
247 static const char *device_families
= "STM32G0/G4/L4/L4+/L5/WB/WL";
249 static const struct stm32l4_rev stm32_415_revs
[] = {
250 { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
253 static const struct stm32l4_rev stm32_435_revs
[] = {
254 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
257 static const struct stm32l4_rev stm32_460_revs
[] = {
258 { 0x1000, "A/Z" } /* A and Z, no typo in RM! */, { 0x2000, "B" },
261 static const struct stm32l4_rev stm32_461_revs
[] = {
262 { 0x1000, "A" }, { 0x2000, "B" },
265 static const struct stm32l4_rev stm32_462_revs
[] = {
266 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
269 static const struct stm32l4_rev stm32_464_revs
[] = {
270 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
273 static const struct stm32l4_rev stm32_466_revs
[] = {
274 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2000, "B" },
277 static const struct stm32l4_rev stm32_468_revs
[] = {
278 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
281 static const struct stm32l4_rev stm32_469_revs
[] = {
282 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
285 static const struct stm32l4_rev stm32_470_revs
[] = {
286 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" },
289 static const struct stm32l4_rev stm32_471_revs
[] = {
293 static const struct stm32l4_rev stm32_472_revs
[] = {
294 { 0x1000, "A" }, { 0x2000, "B" },
297 static const struct stm32l4_rev stm32_479_revs
[] = {
301 static const struct stm32l4_rev stm32_495_revs
[] = {
305 static const struct stm32l4_rev stm32_496_revs
[] = {
309 static const struct stm32l4_rev stm32_497_revs
[] = {
313 static const struct stm32l4_part_info stm32l4_parts
[] = {
316 .revs
= stm32_415_revs
,
317 .num_revs
= ARRAY_SIZE(stm32_415_revs
),
318 .device_str
= "STM32L47/L48xx",
319 .max_flash_size_kb
= 1024,
320 .flags
= F_HAS_DUAL_BANK
,
321 .flash_regs_base
= 0x40022000,
322 .default_flash_regs
= stm32l4_flash_regs
,
323 .fsize_addr
= 0x1FFF75E0,
324 .otp_base
= 0x1FFF7000,
329 .revs
= stm32_435_revs
,
330 .num_revs
= ARRAY_SIZE(stm32_435_revs
),
331 .device_str
= "STM32L43/L44xx",
332 .max_flash_size_kb
= 256,
334 .flash_regs_base
= 0x40022000,
335 .default_flash_regs
= stm32l4_flash_regs
,
336 .fsize_addr
= 0x1FFF75E0,
337 .otp_base
= 0x1FFF7000,
342 .revs
= stm32_460_revs
,
343 .num_revs
= ARRAY_SIZE(stm32_460_revs
),
344 .device_str
= "STM32G07/G08xx",
345 .max_flash_size_kb
= 128,
347 .flash_regs_base
= 0x40022000,
348 .default_flash_regs
= stm32l4_flash_regs
,
349 .fsize_addr
= 0x1FFF75E0,
350 .otp_base
= 0x1FFF7000,
355 .revs
= stm32_461_revs
,
356 .num_revs
= ARRAY_SIZE(stm32_461_revs
),
357 .device_str
= "STM32L49/L4Axx",
358 .max_flash_size_kb
= 1024,
359 .flags
= F_HAS_DUAL_BANK
,
360 .flash_regs_base
= 0x40022000,
361 .default_flash_regs
= stm32l4_flash_regs
,
362 .fsize_addr
= 0x1FFF75E0,
363 .otp_base
= 0x1FFF7000,
368 .revs
= stm32_462_revs
,
369 .num_revs
= ARRAY_SIZE(stm32_462_revs
),
370 .device_str
= "STM32L45/L46xx",
371 .max_flash_size_kb
= 512,
373 .flash_regs_base
= 0x40022000,
374 .default_flash_regs
= stm32l4_flash_regs
,
375 .fsize_addr
= 0x1FFF75E0,
376 .otp_base
= 0x1FFF7000,
381 .revs
= stm32_464_revs
,
382 .num_revs
= ARRAY_SIZE(stm32_464_revs
),
383 .device_str
= "STM32L41/L42xx",
384 .max_flash_size_kb
= 128,
386 .flash_regs_base
= 0x40022000,
387 .default_flash_regs
= stm32l4_flash_regs
,
388 .fsize_addr
= 0x1FFF75E0,
389 .otp_base
= 0x1FFF7000,
394 .revs
= stm32_466_revs
,
395 .num_revs
= ARRAY_SIZE(stm32_466_revs
),
396 .device_str
= "STM32G03/G04xx",
397 .max_flash_size_kb
= 64,
399 .flash_regs_base
= 0x40022000,
400 .default_flash_regs
= stm32l4_flash_regs
,
401 .fsize_addr
= 0x1FFF75E0,
402 .otp_base
= 0x1FFF7000,
407 .revs
= stm32_468_revs
,
408 .num_revs
= ARRAY_SIZE(stm32_468_revs
),
409 .device_str
= "STM32G43/G44xx",
410 .max_flash_size_kb
= 128,
412 .flash_regs_base
= 0x40022000,
413 .default_flash_regs
= stm32l4_flash_regs
,
414 .fsize_addr
= 0x1FFF75E0,
415 .otp_base
= 0x1FFF7000,
420 .revs
= stm32_469_revs
,
421 .num_revs
= ARRAY_SIZE(stm32_469_revs
),
422 .device_str
= "STM32G47/G48xx",
423 .max_flash_size_kb
= 512,
424 .flags
= F_HAS_DUAL_BANK
| F_USE_ALL_WRPXX
,
425 .flash_regs_base
= 0x40022000,
426 .default_flash_regs
= stm32l4_flash_regs
,
427 .fsize_addr
= 0x1FFF75E0,
428 .otp_base
= 0x1FFF7000,
433 .revs
= stm32_470_revs
,
434 .num_revs
= ARRAY_SIZE(stm32_470_revs
),
435 .device_str
= "STM32L4R/L4Sxx",
436 .max_flash_size_kb
= 2048,
437 .flags
= F_HAS_DUAL_BANK
| F_USE_ALL_WRPXX
,
438 .flash_regs_base
= 0x40022000,
439 .default_flash_regs
= stm32l4_flash_regs
,
440 .fsize_addr
= 0x1FFF75E0,
441 .otp_base
= 0x1FFF7000,
446 .revs
= stm32_471_revs
,
447 .num_revs
= ARRAY_SIZE(stm32_471_revs
),
448 .device_str
= "STM32L4P5/L4Q5x",
449 .max_flash_size_kb
= 1024,
450 .flags
= F_HAS_DUAL_BANK
| F_USE_ALL_WRPXX
,
451 .flash_regs_base
= 0x40022000,
452 .default_flash_regs
= stm32l4_flash_regs
,
453 .fsize_addr
= 0x1FFF75E0,
454 .otp_base
= 0x1FFF7000,
459 .revs
= stm32_472_revs
,
460 .num_revs
= ARRAY_SIZE(stm32_472_revs
),
461 .device_str
= "STM32L55/L56xx",
462 .max_flash_size_kb
= 512,
463 .flags
= F_HAS_DUAL_BANK
| F_USE_ALL_WRPXX
| F_HAS_TZ
| F_HAS_L5_FLASH_REGS
,
464 .flash_regs_base
= 0x40022000,
465 .default_flash_regs
= stm32l5_ns_flash_regs
,
466 .fsize_addr
= 0x0BFA05E0,
467 .otp_base
= 0x0BFA0000,
472 .revs
= stm32_479_revs
,
473 .num_revs
= ARRAY_SIZE(stm32_479_revs
),
474 .device_str
= "STM32G49/G4Axx",
475 .max_flash_size_kb
= 512,
477 .flash_regs_base
= 0x40022000,
478 .default_flash_regs
= stm32l4_flash_regs
,
479 .fsize_addr
= 0x1FFF75E0,
480 .otp_base
= 0x1FFF7000,
485 .revs
= stm32_495_revs
,
486 .num_revs
= ARRAY_SIZE(stm32_495_revs
),
487 .device_str
= "STM32WB5x",
488 .max_flash_size_kb
= 1024,
490 .flash_regs_base
= 0x58004000,
491 .default_flash_regs
= stm32l4_flash_regs
,
492 .fsize_addr
= 0x1FFF75E0,
493 .otp_base
= 0x1FFF7000,
498 .revs
= stm32_496_revs
,
499 .num_revs
= ARRAY_SIZE(stm32_496_revs
),
500 .device_str
= "STM32WB3x",
501 .max_flash_size_kb
= 512,
503 .flash_regs_base
= 0x58004000,
504 .default_flash_regs
= stm32l4_flash_regs
,
505 .fsize_addr
= 0x1FFF75E0,
506 .otp_base
= 0x1FFF7000,
511 .revs
= stm32_497_revs
,
512 .num_revs
= ARRAY_SIZE(stm32_497_revs
),
513 .device_str
= "STM32WLEx",
514 .max_flash_size_kb
= 256,
516 .flash_regs_base
= 0x58004000,
517 .default_flash_regs
= stm32l4_flash_regs
,
518 .fsize_addr
= 0x1FFF75E0,
519 .otp_base
= 0x1FFF7000,
524 /* flash bank stm32l4x <base> <size> 0 0 <target#> */
525 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command
)
527 struct stm32l4_flash_bank
*stm32l4_info
;
530 return ERROR_COMMAND_SYNTAX_ERROR
;
532 /* fix-up bank base address: 0 is used for normal flash memory */
534 bank
->base
= STM32_FLASH_BANK_BASE
;
536 stm32l4_info
= calloc(1, sizeof(struct stm32l4_flash_bank
));
538 return ERROR_FAIL
; /* Checkme: What better error to use?*/
539 bank
->driver_priv
= stm32l4_info
;
541 /* The flash write must be aligned to a double word (8-bytes) boundary.
542 * Ask the flash infrastructure to ensure required alignment */
543 bank
->write_start_alignment
= bank
->write_end_alignment
= 8;
545 stm32l4_info
->probed
= false;
546 stm32l4_info
->otp_enabled
= false;
547 stm32l4_info
->user_bank_size
= bank
->size
;
552 /* bitmap helper extension */
558 static void bitmap_to_ranges(unsigned long *bitmap
, unsigned int nbits
,
559 struct range
*ranges
, unsigned int *ranges_count
) {
561 bool last_bit
= 0, cur_bit
;
562 for (unsigned int i
= 0; i
< nbits
; i
++) {
563 cur_bit
= test_bit(i
, bitmap
);
565 if (cur_bit
&& !last_bit
) {
567 ranges
[*ranges_count
- 1].start
= i
;
568 ranges
[*ranges_count
- 1].end
= i
;
569 } else if (cur_bit
&& last_bit
) {
570 /* update (increment) the end this range */
571 ranges
[*ranges_count
- 1].end
= i
;
578 static inline int range_print_one(struct range
*range
, char *str
)
580 if (range
->start
== range
->end
)
581 return sprintf(str
, "[%d]", range
->start
);
583 return sprintf(str
, "[%d,%d]", range
->start
, range
->end
);
586 static char *range_print_alloc(struct range
*ranges
, unsigned int ranges_count
)
588 /* each range will be printed like the following: [start,end]
589 * start and end, both are unsigned int, an unsigned int takes 10 characters max
590 * plus 3 characters for '[', ',' and ']'
591 * thus means each range can take maximum 23 character
592 * after each range we add a ' ' as separator and finally we need the '\0'
593 * if the ranges_count is zero we reserve one char for '\0' to return an empty string */
594 char *str
= calloc(1, ranges_count
* (24 * sizeof(char)) + 1);
597 for (unsigned int i
= 0; i
< ranges_count
; i
++) {
598 ptr
+= range_print_one(&(ranges
[i
]), ptr
);
600 if (i
< ranges_count
- 1)
607 /* end of bitmap helper extension */
609 static inline bool stm32l4_is_otp(struct flash_bank
*bank
)
611 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
612 return bank
->base
== stm32l4_info
->part_info
->otp_base
;
615 static int stm32l4_otp_enable(struct flash_bank
*bank
, bool enable
)
617 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
619 if (!stm32l4_is_otp(bank
))
622 char *op_str
= enable
? "enabled" : "disabled";
624 LOG_INFO("OTP memory (bank #%d) is %s%s for write commands",
626 stm32l4_info
->otp_enabled
== enable
? "already " : "",
629 stm32l4_info
->otp_enabled
= enable
;
634 static inline bool stm32l4_otp_is_enabled(struct flash_bank
*bank
)
636 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
637 return stm32l4_info
->otp_enabled
;
640 static void stm32l4_sync_rdp_tzen(struct flash_bank
*bank
)
642 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
646 if (stm32l4_info
->part_info
->flags
& F_HAS_TZ
)
647 tzen
= (stm32l4_info
->optr
& FLASH_TZEN
) != 0;
649 uint32_t rdp
= stm32l4_info
->optr
& FLASH_RDP_MASK
;
651 /* for devices without TrustZone:
652 * RDP level 0 and 2 values are to 0xAA and 0xCC
653 * Any other value corresponds to RDP level 1
654 * for devices with TrusZone:
655 * RDP level 0 and 2 values are 0xAA and 0xCC
656 * RDP level 0.5 value is 0x55 only if TZEN = 1
657 * Any other value corresponds to RDP level 1, including 0x55 if TZEN = 0
660 if (rdp
!= RDP_LEVEL_0
&& rdp
!= RDP_LEVEL_2
) {
661 if (!tzen
|| (tzen
&& rdp
!= RDP_LEVEL_0_5
))
665 stm32l4_info
->tzen
= tzen
;
666 stm32l4_info
->rdp
= rdp
;
669 static inline uint32_t stm32l4_get_flash_reg(struct flash_bank
*bank
, uint32_t reg_offset
)
671 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
672 return stm32l4_info
->flash_regs_base
+ reg_offset
;
675 static inline uint32_t stm32l4_get_flash_reg_by_index(struct flash_bank
*bank
,
676 enum stm32l4_flash_reg_index reg_index
)
678 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
679 return stm32l4_get_flash_reg(bank
, stm32l4_info
->flash_regs
[reg_index
]);
682 static inline int stm32l4_read_flash_reg(struct flash_bank
*bank
, uint32_t reg_offset
, uint32_t *value
)
684 return target_read_u32(bank
->target
, stm32l4_get_flash_reg(bank
, reg_offset
), value
);
687 static inline int stm32l4_read_flash_reg_by_index(struct flash_bank
*bank
,
688 enum stm32l4_flash_reg_index reg_index
, uint32_t *value
)
690 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
691 return stm32l4_read_flash_reg(bank
, stm32l4_info
->flash_regs
[reg_index
], value
);
694 static inline int stm32l4_write_flash_reg(struct flash_bank
*bank
, uint32_t reg_offset
, uint32_t value
)
696 return target_write_u32(bank
->target
, stm32l4_get_flash_reg(bank
, reg_offset
), value
);
699 static inline int stm32l4_write_flash_reg_by_index(struct flash_bank
*bank
,
700 enum stm32l4_flash_reg_index reg_index
, uint32_t value
)
702 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
703 return stm32l4_write_flash_reg(bank
, stm32l4_info
->flash_regs
[reg_index
], value
);
706 static int stm32l4_wait_status_busy(struct flash_bank
*bank
, int timeout
)
709 int retval
= ERROR_OK
;
711 /* wait for busy to clear */
713 retval
= stm32l4_read_flash_reg_by_index(bank
, STM32_FLASH_SR_INDEX
, &status
);
714 if (retval
!= ERROR_OK
)
716 LOG_DEBUG("status: 0x%" PRIx32
"", status
);
717 if ((status
& FLASH_BSY
) == 0)
719 if (timeout
-- <= 0) {
720 LOG_ERROR("timed out waiting for flash");
726 if (status
& FLASH_WRPERR
) {
727 LOG_ERROR("stm32x device protected");
731 /* Clear but report errors */
732 if (status
& FLASH_ERROR
) {
733 if (retval
== ERROR_OK
)
735 /* If this operation fails, we ignore it and report the original
738 stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_SR_INDEX
, status
& FLASH_ERROR
);
744 /** set all FLASH_SECBB registers to the same value */
745 static int stm32l4_set_secbb(struct flash_bank
*bank
, uint32_t value
)
747 /* This function should be used only with device with TrustZone, do just a security check */
748 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
749 assert(stm32l4_info
->part_info
->flags
& F_HAS_TZ
);
751 /* based on RM0438 Rev6 for STM32L5x devices:
752 * to modify a page block-based security attribution, it is recommended to
753 * 1- check that no flash operation is ongoing on the related page
754 * 2- add ISB instruction after modifying the page security attribute in SECBBxRy
755 * this step is not need in case of JTAG direct access
757 int retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
758 if (retval
!= ERROR_OK
)
761 /* write SECBBxRy registers */
762 LOG_DEBUG("setting secure block-based areas registers (SECBBxRy) to 0x%08x", value
);
764 const uint8_t secbb_regs
[] = {
765 FLASH_SECBB1(1), FLASH_SECBB1(2), FLASH_SECBB1(3), FLASH_SECBB1(4), /* bank 1 SECBB register offsets */
766 FLASH_SECBB2(1), FLASH_SECBB2(2), FLASH_SECBB2(3), FLASH_SECBB2(4) /* bank 2 SECBB register offsets */
770 unsigned int num_secbb_regs
= ARRAY_SIZE(secbb_regs
);
772 /* in single bank mode, it's useless to modify FLASH_SECBB2Rx registers
773 * then consider only the first half of secbb_regs
775 if (!stm32l4_info
->dual_bank_mode
)
778 for (unsigned int i
= 0; i
< num_secbb_regs
; i
++) {
779 retval
= stm32l4_write_flash_reg(bank
, secbb_regs
[i
], value
);
780 if (retval
!= ERROR_OK
)
787 static int stm32l4_unlock_reg(struct flash_bank
*bank
)
791 /* first check if not already unlocked
792 * otherwise writing on STM32_FLASH_KEYR will fail
794 int retval
= stm32l4_read_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, &ctrl
);
795 if (retval
!= ERROR_OK
)
798 if ((ctrl
& FLASH_LOCK
) == 0)
801 /* unlock flash registers */
802 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_KEYR_INDEX
, KEY1
);
803 if (retval
!= ERROR_OK
)
806 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_KEYR_INDEX
, KEY2
);
807 if (retval
!= ERROR_OK
)
810 retval
= stm32l4_read_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, &ctrl
);
811 if (retval
!= ERROR_OK
)
814 if (ctrl
& FLASH_LOCK
) {
815 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32
, ctrl
);
816 return ERROR_TARGET_FAILURE
;
822 static int stm32l4_unlock_option_reg(struct flash_bank
*bank
)
826 int retval
= stm32l4_read_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, &ctrl
);
827 if (retval
!= ERROR_OK
)
830 if ((ctrl
& FLASH_OPTLOCK
) == 0)
833 /* unlock option registers */
834 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_OPTKEYR_INDEX
, OPTKEY1
);
835 if (retval
!= ERROR_OK
)
838 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_OPTKEYR_INDEX
, OPTKEY2
);
839 if (retval
!= ERROR_OK
)
842 retval
= stm32l4_read_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, &ctrl
);
843 if (retval
!= ERROR_OK
)
846 if (ctrl
& FLASH_OPTLOCK
) {
847 LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32
, ctrl
);
848 return ERROR_TARGET_FAILURE
;
854 static int stm32l4_perform_obl_launch(struct flash_bank
*bank
)
858 retval
= stm32l4_unlock_reg(bank
);
859 if (retval
!= ERROR_OK
)
862 retval
= stm32l4_unlock_option_reg(bank
);
863 if (retval
!= ERROR_OK
)
866 /* Set OBL_LAUNCH bit in CR -> system reset and option bytes reload,
867 * but the RMs explicitly do *NOT* list this as power-on reset cause, and:
868 * "Note: If the read protection is set while the debugger is still
869 * connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset."
872 /* "Setting OBL_LAUNCH generates a reset so the option byte loading is performed under system reset" */
873 /* Due to this reset ST-Link reports an SWD_DP_ERROR, despite the write was successful,
874 * then just ignore the returned value */
875 stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, FLASH_OBL_LAUNCH
);
877 /* Need to re-probe after change */
878 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
879 stm32l4_info
->probed
= false;
882 retval2
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, FLASH_LOCK
| FLASH_OPTLOCK
);
884 if (retval
!= ERROR_OK
)
890 static int stm32l4_write_option(struct flash_bank
*bank
, uint32_t reg_offset
,
891 uint32_t value
, uint32_t mask
)
893 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
897 retval
= stm32l4_read_flash_reg(bank
, reg_offset
, &optiondata
);
898 if (retval
!= ERROR_OK
)
901 /* for STM32L5 and similar devices, use always non-secure
902 * registers for option bytes programming */
903 const uint32_t *saved_flash_regs
= stm32l4_info
->flash_regs
;
904 if (stm32l4_info
->part_info
->flags
& F_HAS_L5_FLASH_REGS
)
905 stm32l4_info
->flash_regs
= stm32l5_ns_flash_regs
;
907 retval
= stm32l4_unlock_reg(bank
);
908 if (retval
!= ERROR_OK
)
911 retval
= stm32l4_unlock_option_reg(bank
);
912 if (retval
!= ERROR_OK
)
915 optiondata
= (optiondata
& ~mask
) | (value
& mask
);
917 retval
= stm32l4_write_flash_reg(bank
, reg_offset
, optiondata
);
918 if (retval
!= ERROR_OK
)
921 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, FLASH_OPTSTRT
);
922 if (retval
!= ERROR_OK
)
925 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
928 retval2
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, FLASH_LOCK
| FLASH_OPTLOCK
);
929 stm32l4_info
->flash_regs
= saved_flash_regs
;
931 if (retval
!= ERROR_OK
)
937 static int stm32l4_get_one_wrpxy(struct flash_bank
*bank
, struct stm32l4_wrp
*wrpxy
,
938 enum stm32l4_flash_reg_index reg_idx
, int offset
)
940 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
943 wrpxy
->reg_idx
= reg_idx
;
944 wrpxy
->offset
= offset
;
946 ret
= stm32l4_read_flash_reg_by_index(bank
, wrpxy
->reg_idx
, &wrpxy
->value
);
950 wrpxy
->first
= (wrpxy
->value
& stm32l4_info
->wrpxxr_mask
) + wrpxy
->offset
;
951 wrpxy
->last
= ((wrpxy
->value
>> 16) & stm32l4_info
->wrpxxr_mask
) + wrpxy
->offset
;
952 wrpxy
->used
= wrpxy
->first
<= wrpxy
->last
;
957 static int stm32l4_get_all_wrpxy(struct flash_bank
*bank
, enum stm32_bank_id dev_bank_id
,
958 struct stm32l4_wrp
*wrpxy
, unsigned int *n_wrp
)
960 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
965 /* for single bank devices there is 2 WRP regions.
966 * for dual bank devices there is 2 WRP regions per bank,
967 * if configured as single bank only 2 WRP are usable
968 * except for STM32L4R/S/P/Q, G4 cat3, L5 ... all 4 WRP are usable
969 * note: this should be revised, if a device will have the SWAP banks option
972 int wrp2y_sectors_offset
= -1; /* -1 : unused */
974 /* if bank_id is BANK1 or ALL_BANKS */
975 if (dev_bank_id
!= STM32_BANK2
) {
976 /* get FLASH_WRP1AR */
977 ret
= stm32l4_get_one_wrpxy(bank
, &wrpxy
[(*n_wrp
)++], STM32_FLASH_WRP1AR_INDEX
, 0);
982 ret
= stm32l4_get_one_wrpxy(bank
, &wrpxy
[(*n_wrp
)++], STM32_FLASH_WRP1BR_INDEX
, 0);
986 /* for some devices (like STM32L4R/S) in single-bank mode, the 4 WRPxx are usable */
987 if ((stm32l4_info
->part_info
->flags
& F_USE_ALL_WRPXX
) && !stm32l4_info
->dual_bank_mode
)
988 wrp2y_sectors_offset
= 0;
991 /* if bank_id is BANK2 or ALL_BANKS */
992 if (dev_bank_id
!= STM32_BANK1
&& stm32l4_info
->dual_bank_mode
)
993 wrp2y_sectors_offset
= stm32l4_info
->bank1_sectors
;
995 if (wrp2y_sectors_offset
> -1) {
997 ret
= stm32l4_get_one_wrpxy(bank
, &wrpxy
[(*n_wrp
)++], STM32_FLASH_WRP2AR_INDEX
, wrp2y_sectors_offset
);
1002 ret
= stm32l4_get_one_wrpxy(bank
, &wrpxy
[(*n_wrp
)++], STM32_FLASH_WRP2BR_INDEX
, wrp2y_sectors_offset
);
1003 if (ret
!= ERROR_OK
)
1010 static int stm32l4_write_one_wrpxy(struct flash_bank
*bank
, struct stm32l4_wrp
*wrpxy
)
1012 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1014 int wrp_start
= wrpxy
->first
- wrpxy
->offset
;
1015 int wrp_end
= wrpxy
->last
- wrpxy
->offset
;
1017 uint32_t wrp_value
= (wrp_start
& stm32l4_info
->wrpxxr_mask
) | ((wrp_end
& stm32l4_info
->wrpxxr_mask
) << 16);
1019 return stm32l4_write_option(bank
, stm32l4_info
->flash_regs
[wrpxy
->reg_idx
], wrp_value
, 0xffffffff);
1022 static int stm32l4_write_all_wrpxy(struct flash_bank
*bank
, struct stm32l4_wrp
*wrpxy
, unsigned int n_wrp
)
1026 for (unsigned int i
= 0; i
< n_wrp
; i
++) {
1027 ret
= stm32l4_write_one_wrpxy(bank
, &wrpxy
[i
]);
1028 if (ret
!= ERROR_OK
)
1035 static int stm32l4_protect_check(struct flash_bank
*bank
)
1038 struct stm32l4_wrp wrpxy
[4];
1040 int ret
= stm32l4_get_all_wrpxy(bank
, STM32_ALL_BANKS
, wrpxy
, &n_wrp
);
1041 if (ret
!= ERROR_OK
)
1044 /* initialize all sectors as unprotected */
1045 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++)
1046 bank
->sectors
[i
].is_protected
= 0;
1048 /* now check WRPxy and mark the protected sectors */
1049 for (unsigned int i
= 0; i
< n_wrp
; i
++) {
1050 if (wrpxy
[i
].used
) {
1051 for (int s
= wrpxy
[i
].first
; s
<= wrpxy
[i
].last
; s
++)
1052 bank
->sectors
[s
].is_protected
= 1;
1059 static int stm32l4_erase(struct flash_bank
*bank
, unsigned int first
,
1062 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1063 int retval
, retval2
;
1065 assert((first
<= last
) && (last
< bank
->num_sectors
));
1067 if (stm32l4_is_otp(bank
)) {
1068 LOG_ERROR("cannot erase OTP memory");
1069 return ERROR_FLASH_OPER_UNSUPPORTED
;
1072 if (bank
->target
->state
!= TARGET_HALTED
) {
1073 LOG_ERROR("Target not halted");
1074 return ERROR_TARGET_NOT_HALTED
;
1077 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0
)) {
1078 /* set all FLASH pages as secure */
1079 retval
= stm32l4_set_secbb(bank
, FLASH_SECBB_SECURE
);
1080 if (retval
!= ERROR_OK
) {
1081 /* restore all FLASH pages as non-secure */
1082 stm32l4_set_secbb(bank
, FLASH_SECBB_NON_SECURE
); /* ignore the return value */
1087 retval
= stm32l4_unlock_reg(bank
);
1088 if (retval
!= ERROR_OK
)
1093 To erase a sector, follow the procedure below:
1094 1. Check that no Flash memory operation is ongoing by
1095 checking the BSY bit in the FLASH_SR register
1096 2. Set the PER bit and select the page and bank
1097 you wish to erase in the FLASH_CR register
1098 3. Set the STRT bit in the FLASH_CR register
1099 4. Wait for the BSY bit to be cleared
1102 for (unsigned int i
= first
; i
<= last
; i
++) {
1103 uint32_t erase_flags
;
1104 erase_flags
= FLASH_PER
| FLASH_STRT
;
1106 if (i
>= stm32l4_info
->bank1_sectors
) {
1108 snb
= i
- stm32l4_info
->bank1_sectors
;
1109 erase_flags
|= snb
<< FLASH_PAGE_SHIFT
| FLASH_CR_BKER
;
1111 erase_flags
|= i
<< FLASH_PAGE_SHIFT
;
1112 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, erase_flags
);
1113 if (retval
!= ERROR_OK
)
1116 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
1117 if (retval
!= ERROR_OK
)
1122 retval2
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, FLASH_LOCK
);
1124 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0
)) {
1125 /* restore all FLASH pages as non-secure */
1126 int retval3
= stm32l4_set_secbb(bank
, FLASH_SECBB_NON_SECURE
);
1127 if (retval3
!= ERROR_OK
)
1131 if (retval
!= ERROR_OK
)
1137 static int stm32l4_protect(struct flash_bank
*bank
, int set
, unsigned int first
, unsigned int last
)
1139 struct target
*target
= bank
->target
;
1140 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1144 if (stm32l4_is_otp(bank
)) {
1145 LOG_ERROR("cannot protect/unprotect OTP memory");
1146 return ERROR_FLASH_OPER_UNSUPPORTED
;
1149 if (target
->state
!= TARGET_HALTED
) {
1150 LOG_ERROR("Target not halted");
1151 return ERROR_TARGET_NOT_HALTED
;
1154 /* the requested sectors could be located into bank1 and/or bank2 */
1155 bool use_bank2
= false;
1156 if (last
>= stm32l4_info
->bank1_sectors
) {
1157 if (first
< stm32l4_info
->bank1_sectors
) {
1158 /* the requested sectors for (un)protection are shared between
1159 * bank 1 and 2, then split the operation */
1161 /* 1- deal with bank 1 sectors */
1162 LOG_DEBUG("The requested sectors for %s are shared between bank 1 and 2",
1163 set
? "protection" : "unprotection");
1164 ret
= stm32l4_protect(bank
, set
, first
, stm32l4_info
->bank1_sectors
- 1);
1165 if (ret
!= ERROR_OK
)
1168 /* 2- then continue with bank 2 sectors */
1169 first
= stm32l4_info
->bank1_sectors
;
1175 /* refresh the sectors' protection */
1176 ret
= stm32l4_protect_check(bank
);
1177 if (ret
!= ERROR_OK
)
1180 /* check if the desired protection is already configured */
1181 for (i
= first
; i
<= last
; i
++) {
1182 if (bank
->sectors
[i
].is_protected
!= set
)
1184 else if (i
== last
) {
1185 LOG_INFO("The specified sectors are already %s", set
? "protected" : "unprotected");
1190 /* all sectors from first to last (or part of them) could have different
1191 * protection other than the requested */
1193 struct stm32l4_wrp wrpxy
[4];
1195 ret
= stm32l4_get_all_wrpxy(bank
, use_bank2
? STM32_BANK2
: STM32_BANK1
, wrpxy
, &n_wrp
);
1196 if (ret
!= ERROR_OK
)
1199 /* use bitmap and range helpers to optimize the WRP usage */
1200 DECLARE_BITMAP(pages
, bank
->num_sectors
);
1201 bitmap_zero(pages
, bank
->num_sectors
);
1203 for (i
= 0; i
< n_wrp
; i
++) {
1204 if (wrpxy
[i
].used
) {
1205 for (int p
= wrpxy
[i
].first
; p
<= wrpxy
[i
].last
; p
++)
1210 /* we have at most 'n_wrp' WRP areas
1211 * add one range if the user is trying to protect a fifth range */
1212 struct range ranges
[n_wrp
+ 1];
1213 unsigned int ranges_count
= 0;
1215 bitmap_to_ranges(pages
, bank
->num_sectors
, ranges
, &ranges_count
);
1217 /* pretty-print the currently protected ranges */
1218 if (ranges_count
> 0) {
1219 char *ranges_str
= range_print_alloc(ranges
, ranges_count
);
1220 LOG_DEBUG("current protected areas: %s", ranges_str
);
1223 LOG_DEBUG("current protected areas: none");
1225 if (set
) { /* flash protect */
1226 for (i
= first
; i
<= last
; i
++)
1228 } else { /* flash unprotect */
1229 for (i
= first
; i
<= last
; i
++)
1230 clear_bit(i
, pages
);
1233 /* check the ranges_count after the user request */
1234 bitmap_to_ranges(pages
, bank
->num_sectors
, ranges
, &ranges_count
);
1236 /* pretty-print the requested areas for protection */
1237 if (ranges_count
> 0) {
1238 char *ranges_str
= range_print_alloc(ranges
, ranges_count
);
1239 LOG_DEBUG("requested areas for protection: %s", ranges_str
);
1242 LOG_DEBUG("requested areas for protection: none");
1244 if (ranges_count
> n_wrp
) {
1245 LOG_ERROR("cannot set the requested protection "
1246 "(only %u write protection areas are available)" , n_wrp
);
1250 /* re-init all WRPxy as disabled (first > last)*/
1251 for (i
= 0; i
< n_wrp
; i
++) {
1252 wrpxy
[i
].first
= wrpxy
[i
].offset
+ 1;
1253 wrpxy
[i
].last
= wrpxy
[i
].offset
;
1256 /* then configure WRPxy areas */
1257 for (i
= 0; i
< ranges_count
; i
++) {
1258 wrpxy
[i
].first
= ranges
[i
].start
;
1259 wrpxy
[i
].last
= ranges
[i
].end
;
1262 /* finally write WRPxy registers */
1263 return stm32l4_write_all_wrpxy(bank
, wrpxy
, n_wrp
);
1266 /* Count is in double-words */
1267 static int stm32l4_write_block(struct flash_bank
*bank
, const uint8_t *buffer
,
1268 uint32_t offset
, uint32_t count
)
1270 struct target
*target
= bank
->target
;
1271 uint32_t buffer_size
;
1272 struct working_area
*write_algorithm
;
1273 struct working_area
*source
;
1274 uint32_t address
= bank
->base
+ offset
;
1275 struct reg_param reg_params
[6];
1276 struct armv7m_algorithm armv7m_info
;
1277 int retval
= ERROR_OK
;
1279 static const uint8_t stm32l4_flash_write_code
[] = {
1280 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
1283 if (target_alloc_working_area(target
, sizeof(stm32l4_flash_write_code
),
1284 &write_algorithm
) != ERROR_OK
) {
1285 LOG_WARNING("no working area available, can't do block memory writes");
1286 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1289 retval
= target_write_buffer(target
, write_algorithm
->address
,
1290 sizeof(stm32l4_flash_write_code
),
1291 stm32l4_flash_write_code
);
1292 if (retval
!= ERROR_OK
) {
1293 target_free_working_area(target
, write_algorithm
);
1297 /* memory buffer, size *must* be multiple of dword plus one dword for rp and one for wp */
1298 buffer_size
= target_get_working_area_avail(target
) & ~(2 * sizeof(uint32_t) - 1);
1299 if (buffer_size
< 256) {
1300 LOG_WARNING("large enough working area not available, can't do block memory writes");
1301 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1302 } else if (buffer_size
> 16384) {
1303 /* probably won't benefit from more than 16k ... */
1304 buffer_size
= 16384;
1307 if (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
) {
1308 LOG_ERROR("allocating working area failed");
1309 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1312 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
1313 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
1315 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* buffer start, status (out) */
1316 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* buffer end */
1317 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* target address */
1318 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
); /* count (double word-64bit) */
1319 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
); /* flash status register */
1320 init_reg_param(®_params
[5], "r5", 32, PARAM_OUT
); /* flash control register */
1322 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1323 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
+ source
->size
);
1324 buf_set_u32(reg_params
[2].value
, 0, 32, address
);
1325 buf_set_u32(reg_params
[3].value
, 0, 32, count
);
1326 buf_set_u32(reg_params
[4].value
, 0, 32, stm32l4_get_flash_reg_by_index(bank
, STM32_FLASH_SR_INDEX
));
1327 buf_set_u32(reg_params
[5].value
, 0, 32, stm32l4_get_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
));
1329 retval
= target_run_flash_async_algorithm(target
, buffer
, count
, 8,
1331 ARRAY_SIZE(reg_params
), reg_params
,
1332 source
->address
, source
->size
,
1333 write_algorithm
->address
, 0,
1336 if (retval
== ERROR_FLASH_OPERATION_FAILED
) {
1337 LOG_ERROR("error executing stm32l4 flash write algorithm");
1339 uint32_t error
= buf_get_u32(reg_params
[0].value
, 0, 32) & FLASH_ERROR
;
1341 if (error
& FLASH_WRPERR
)
1342 LOG_ERROR("flash memory write protected");
1345 LOG_ERROR("flash write failed = %08" PRIx32
, error
);
1346 /* Clear but report errors */
1347 stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_SR_INDEX
, error
);
1348 retval
= ERROR_FAIL
;
1352 target_free_working_area(target
, source
);
1353 target_free_working_area(target
, write_algorithm
);
1355 destroy_reg_param(®_params
[0]);
1356 destroy_reg_param(®_params
[1]);
1357 destroy_reg_param(®_params
[2]);
1358 destroy_reg_param(®_params
[3]);
1359 destroy_reg_param(®_params
[4]);
1360 destroy_reg_param(®_params
[5]);
1365 static int stm32l4_write(struct flash_bank
*bank
, const uint8_t *buffer
,
1366 uint32_t offset
, uint32_t count
)
1368 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1369 int retval
= ERROR_OK
, retval2
;
1371 if (stm32l4_is_otp(bank
) && !stm32l4_otp_is_enabled(bank
)) {
1372 LOG_ERROR("OTP memory is disabled for write commands");
1376 if (bank
->target
->state
!= TARGET_HALTED
) {
1377 LOG_ERROR("Target not halted");
1378 return ERROR_TARGET_NOT_HALTED
;
1381 /* The flash write must be aligned to a double word (8-bytes) boundary.
1382 * The flash infrastructure ensures it, do just a security check */
1383 assert(offset
% 8 == 0);
1384 assert(count
% 8 == 0);
1386 /* STM32G4xxx Cat. 3 devices may have gaps between banks, check whether
1387 * data to be written does not go into a gap:
1388 * suppose buffer is fully contained in bank from sector 0 to sector
1389 * num->sectors - 1 and sectors are ordered according to offset
1391 struct flash_sector
*head
= &bank
->sectors
[0];
1392 struct flash_sector
*tail
= &bank
->sectors
[bank
->num_sectors
- 1];
1394 while ((head
< tail
) && (offset
>= (head
+ 1)->offset
)) {
1395 /* buffer does not intersect head nor gap behind head */
1399 while ((head
< tail
) && (offset
+ count
<= (tail
- 1)->offset
+ (tail
- 1)->size
)) {
1400 /* buffer does not intersect tail nor gap before tail */
1404 LOG_DEBUG("data: 0x%08" PRIx32
" - 0x%08" PRIx32
", sectors: 0x%08" PRIx32
" - 0x%08" PRIx32
,
1405 offset
, offset
+ count
- 1, head
->offset
, tail
->offset
+ tail
->size
- 1);
1407 /* Now check that there is no gap from head to tail, this should work
1408 * even for multiple or non-symmetric gaps
1410 while (head
< tail
) {
1411 if (head
->offset
+ head
->size
!= (head
+ 1)->offset
) {
1412 LOG_ERROR("write into gap from " TARGET_ADDR_FMT
" to " TARGET_ADDR_FMT
,
1413 bank
->base
+ head
->offset
+ head
->size
,
1414 bank
->base
+ (head
+ 1)->offset
- 1);
1415 retval
= ERROR_FLASH_DST_OUT_OF_BANK
;
1420 if (retval
!= ERROR_OK
)
1423 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0
)) {
1424 /* set all FLASH pages as secure */
1425 retval
= stm32l4_set_secbb(bank
, FLASH_SECBB_SECURE
);
1426 if (retval
!= ERROR_OK
) {
1427 /* restore all FLASH pages as non-secure */
1428 stm32l4_set_secbb(bank
, FLASH_SECBB_NON_SECURE
); /* ignore the return value */
1433 retval
= stm32l4_unlock_reg(bank
);
1434 if (retval
!= ERROR_OK
)
1437 /* For TrustZone enabled devices, when TZEN is set and RDP level is 0.5,
1438 * the debug is possible only in non-secure state.
1439 * Thus means the flashloader will run in non-secure mode,
1440 * and the workarea need to be in non-secure RAM */
1441 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0_5
))
1442 LOG_INFO("RDP level is 0.5, the work-area should reside in non-secure RAM");
1444 retval
= stm32l4_write_block(bank
, buffer
, offset
, count
/ 8);
1447 retval2
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, FLASH_LOCK
);
1449 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0
)) {
1450 /* restore all FLASH pages as non-secure */
1451 int retval3
= stm32l4_set_secbb(bank
, FLASH_SECBB_NON_SECURE
);
1452 if (retval3
!= ERROR_OK
)
1456 if (retval
!= ERROR_OK
) {
1457 LOG_ERROR("block write failed");
1463 static int stm32l4_read_idcode(struct flash_bank
*bank
, uint32_t *id
)
1467 /* try reading possible IDCODE registers, in the following order */
1468 uint32_t dbgmcu_idcode
[] = {DBGMCU_IDCODE_L4_G4
, DBGMCU_IDCODE_G0
, DBGMCU_IDCODE_L5
};
1470 for (unsigned int i
= 0; i
< ARRAY_SIZE(dbgmcu_idcode
); i
++) {
1471 retval
= target_read_u32(bank
->target
, dbgmcu_idcode
[i
], id
);
1472 if ((retval
== ERROR_OK
) && ((*id
& 0xfff) != 0) && ((*id
& 0xfff) != 0xfff))
1476 LOG_ERROR("can't get the device id");
1477 return (retval
== ERROR_OK
) ? ERROR_FAIL
: retval
;
1480 static const char *get_stm32l4_rev_str(struct flash_bank
*bank
)
1482 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1483 const struct stm32l4_part_info
*part_info
= stm32l4_info
->part_info
;
1486 const uint16_t rev_id
= stm32l4_info
->idcode
>> 16;
1487 for (unsigned int i
= 0; i
< part_info
->num_revs
; i
++) {
1488 if (rev_id
== part_info
->revs
[i
].rev
)
1489 return part_info
->revs
[i
].str
;
1494 static const char *get_stm32l4_bank_type_str(struct flash_bank
*bank
)
1496 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1497 assert(stm32l4_info
->part_info
);
1498 return stm32l4_is_otp(bank
) ? "OTP" :
1499 stm32l4_info
->dual_bank_mode
? "Flash dual" :
1503 static int stm32l4_probe(struct flash_bank
*bank
)
1505 struct target
*target
= bank
->target
;
1506 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1507 const struct stm32l4_part_info
*part_info
;
1508 uint16_t flash_size_kb
= 0xffff;
1510 stm32l4_info
->probed
= false;
1512 /* read stm32 device id registers */
1513 int retval
= stm32l4_read_idcode(bank
, &stm32l4_info
->idcode
);
1514 if (retval
!= ERROR_OK
)
1517 const uint32_t device_id
= stm32l4_info
->idcode
& 0xFFF;
1519 for (unsigned int n
= 0; n
< ARRAY_SIZE(stm32l4_parts
); n
++) {
1520 if (device_id
== stm32l4_parts
[n
].id
) {
1521 stm32l4_info
->part_info
= &stm32l4_parts
[n
];
1526 if (!stm32l4_info
->part_info
) {
1527 LOG_WARNING("Cannot identify target as an %s family device.", device_families
);
1531 part_info
= stm32l4_info
->part_info
;
1532 const char *rev_str
= get_stm32l4_rev_str(bank
);
1533 const uint16_t rev_id
= stm32l4_info
->idcode
>> 16;
1535 LOG_INFO("device idcode = 0x%08" PRIx32
" (%s - Rev %s : 0x%04x)",
1536 stm32l4_info
->idcode
, part_info
->device_str
, rev_str
, rev_id
);
1538 stm32l4_info
->flash_regs_base
= stm32l4_info
->part_info
->flash_regs_base
;
1539 stm32l4_info
->flash_regs
= stm32l4_info
->part_info
->default_flash_regs
;
1541 /* read flash option register */
1542 retval
= stm32l4_read_flash_reg_by_index(bank
, STM32_FLASH_OPTR_INDEX
, &stm32l4_info
->optr
);
1543 if (retval
!= ERROR_OK
)
1546 stm32l4_sync_rdp_tzen(bank
);
1548 if (part_info
->flags
& F_HAS_TZ
)
1549 LOG_INFO("TZEN = %d : TrustZone %s by option bytes",
1551 stm32l4_info
->tzen
? "enabled" : "disabled");
1553 LOG_INFO("RDP level %s (0x%02X)",
1554 stm32l4_info
->rdp
== RDP_LEVEL_0
? "0" : stm32l4_info
->rdp
== RDP_LEVEL_0_5
? "0.5" : "1",
1557 if (stm32l4_is_otp(bank
)) {
1558 bank
->size
= part_info
->otp_size
;
1560 LOG_INFO("OTP size is %d bytes, base address is " TARGET_ADDR_FMT
, bank
->size
, bank
->base
);
1562 /* OTP memory is considered as one sector */
1563 free(bank
->sectors
);
1564 bank
->num_sectors
= 1;
1565 bank
->sectors
= alloc_block_array(0, part_info
->otp_size
, 1);
1567 if (!bank
->sectors
) {
1568 LOG_ERROR("failed to allocate bank sectors");
1572 stm32l4_info
->probed
= true;
1574 } else if (bank
->base
!= STM32_FLASH_BANK_BASE
&& bank
->base
!= STM32_FLASH_S_BANK_BASE
) {
1575 LOG_ERROR("invalid bank base address");
1579 /* get flash size from target. */
1580 retval
= target_read_u16(target
, part_info
->fsize_addr
, &flash_size_kb
);
1582 /* failed reading flash size or flash size invalid (early silicon),
1583 * default to max target family */
1584 if (retval
!= ERROR_OK
|| flash_size_kb
== 0xffff || flash_size_kb
== 0
1585 || flash_size_kb
> part_info
->max_flash_size_kb
) {
1586 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
1587 part_info
->max_flash_size_kb
);
1588 flash_size_kb
= part_info
->max_flash_size_kb
;
1591 /* if the user sets the size manually then ignore the probed value
1592 * this allows us to work around devices that have a invalid flash size register value */
1593 if (stm32l4_info
->user_bank_size
) {
1594 LOG_WARNING("overriding size register by configured bank size - MAY CAUSE TROUBLE");
1595 flash_size_kb
= stm32l4_info
->user_bank_size
/ 1024;
1598 LOG_INFO("flash size = %dkbytes", flash_size_kb
);
1600 /* did we assign a flash size? */
1601 assert((flash_size_kb
!= 0xffff) && flash_size_kb
);
1603 stm32l4_info
->bank1_sectors
= 0;
1604 stm32l4_info
->hole_sectors
= 0;
1607 int page_size_kb
= 0;
1609 stm32l4_info
->dual_bank_mode
= false;
1610 bool use_dbank_bit
= false;
1612 switch (device_id
) {
1613 case 0x415: /* STM32L47/L48xx */
1614 case 0x461: /* STM32L49/L4Axx */
1615 /* if flash size is max (1M) the device is always dual bank
1616 * 0x415: has variants with 512K
1617 * 0x461: has variants with 512 and 256
1618 * for these variants:
1619 * if DUAL_BANK = 0 -> single bank
1620 * else -> dual bank without gap
1621 * note: the page size is invariant
1624 num_pages
= flash_size_kb
/ page_size_kb
;
1625 stm32l4_info
->bank1_sectors
= num_pages
;
1627 /* check DUAL_BANK bit[21] if the flash is less than 1M */
1628 if (flash_size_kb
== 1024 || (stm32l4_info
->optr
& BIT(21))) {
1629 stm32l4_info
->dual_bank_mode
= true;
1630 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
1633 case 0x435: /* STM32L43/L44xx */
1634 case 0x460: /* STM32G07/G08xx */
1635 case 0x462: /* STM32L45/L46xx */
1636 case 0x464: /* STM32L41/L42xx */
1637 case 0x466: /* STM32G03/G04xx */
1638 case 0x468: /* STM32G43/G44xx */
1639 case 0x479: /* STM32G49/G4Axx */
1640 case 0x497: /* STM32WLEx */
1641 /* single bank flash */
1643 num_pages
= flash_size_kb
/ page_size_kb
;
1644 stm32l4_info
->bank1_sectors
= num_pages
;
1646 case 0x469: /* STM32G47/G48xx */
1647 /* STM32G47/8 can be single/dual bank:
1648 * if DUAL_BANK = 0 -> single bank
1649 * else -> dual bank WITH gap
1652 num_pages
= flash_size_kb
/ page_size_kb
;
1653 stm32l4_info
->bank1_sectors
= num_pages
;
1654 if (stm32l4_info
->optr
& BIT(22)) {
1655 stm32l4_info
->dual_bank_mode
= true;
1657 num_pages
= flash_size_kb
/ page_size_kb
;
1658 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
1660 /* for devices with trimmed flash, there is a gap between both banks */
1661 stm32l4_info
->hole_sectors
=
1662 (part_info
->max_flash_size_kb
- flash_size_kb
) / (2 * page_size_kb
);
1665 case 0x470: /* STM32L4R/L4Sxx */
1666 case 0x471: /* STM32L4P5/L4Q5x */
1667 /* STM32L4R/S can be single/dual bank:
1668 * if size = 2M check DBANK bit(22)
1669 * if size = 1M check DB1M bit(21)
1670 * STM32L4P/Q can be single/dual bank
1671 * if size = 1M check DBANK bit(22)
1672 * if size = 512K check DB512K bit(21)
1675 num_pages
= flash_size_kb
/ page_size_kb
;
1676 stm32l4_info
->bank1_sectors
= num_pages
;
1677 use_dbank_bit
= flash_size_kb
== part_info
->max_flash_size_kb
;
1678 if ((use_dbank_bit
&& (stm32l4_info
->optr
& BIT(22))) ||
1679 (!use_dbank_bit
&& (stm32l4_info
->optr
& BIT(21)))) {
1680 stm32l4_info
->dual_bank_mode
= true;
1682 num_pages
= flash_size_kb
/ page_size_kb
;
1683 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
1686 case 0x472: /* STM32L55/L56xx */
1687 /* STM32L55/L56xx can be single/dual bank:
1688 * if size = 512K check DBANK bit(22)
1689 * if size = 256K check DB256K bit(21)
1692 num_pages
= flash_size_kb
/ page_size_kb
;
1693 stm32l4_info
->bank1_sectors
= num_pages
;
1694 use_dbank_bit
= flash_size_kb
== part_info
->max_flash_size_kb
;
1695 if ((use_dbank_bit
&& (stm32l4_info
->optr
& BIT(22))) ||
1696 (!use_dbank_bit
&& (stm32l4_info
->optr
& BIT(21)))) {
1697 stm32l4_info
->dual_bank_mode
= true;
1699 num_pages
= flash_size_kb
/ page_size_kb
;
1700 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
1704 * by default use the non-secure registers,
1705 * switch secure registers if TZ is enabled and RDP is LEVEL_0
1707 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0
)) {
1708 stm32l4_info
->flash_regs_base
|= 0x10000000;
1709 stm32l4_info
->flash_regs
= stm32l5_s_flash_regs
;
1712 case 0x495: /* STM32WB5x */
1713 case 0x496: /* STM32WB3x */
1714 /* single bank flash */
1716 num_pages
= flash_size_kb
/ page_size_kb
;
1717 stm32l4_info
->bank1_sectors
= num_pages
;
1720 LOG_ERROR("unsupported device");
1724 LOG_INFO("flash mode : %s-bank", stm32l4_info
->dual_bank_mode
? "dual" : "single");
1726 const int gap_size_kb
= stm32l4_info
->hole_sectors
* page_size_kb
;
1728 if (gap_size_kb
!= 0) {
1729 LOG_INFO("gap detected from 0x%08x to 0x%08x",
1730 STM32_FLASH_BANK_BASE
+ stm32l4_info
->bank1_sectors
1731 * page_size_kb
* 1024,
1732 STM32_FLASH_BANK_BASE
+ (stm32l4_info
->bank1_sectors
1733 * page_size_kb
+ gap_size_kb
) * 1024 - 1);
1736 /* number of significant bits in WRPxxR differs per device,
1737 * always right adjusted, on some devices non-implemented
1738 * bits read as '0', on others as '1' ...
1739 * notably G4 Cat. 2 implement only 6 bits, contradicting the RM
1742 /* use *max_flash_size* instead of actual size as the trimmed versions
1743 * certainly use the same number of bits
1744 * max_flash_size is always power of two, so max_pages too
1746 uint32_t max_pages
= stm32l4_info
->part_info
->max_flash_size_kb
/ page_size_kb
;
1747 assert(IS_PWR_OF_2(max_pages
));
1749 /* in dual bank mode number of pages is doubled, but extra bit is bank selection */
1750 stm32l4_info
->wrpxxr_mask
= ((max_pages
>> (stm32l4_info
->dual_bank_mode
? 1 : 0)) - 1);
1751 assert((stm32l4_info
->wrpxxr_mask
& 0xFFFF0000) == 0);
1752 LOG_DEBUG("WRPxxR mask 0x%04" PRIx16
, (uint16_t)stm32l4_info
->wrpxxr_mask
);
1754 free(bank
->sectors
);
1756 bank
->size
= (flash_size_kb
+ gap_size_kb
) * 1024;
1757 bank
->num_sectors
= num_pages
;
1758 bank
->sectors
= malloc(sizeof(struct flash_sector
) * bank
->num_sectors
);
1759 if (!bank
->sectors
) {
1760 LOG_ERROR("failed to allocate bank sectors");
1764 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++) {
1765 bank
->sectors
[i
].offset
= i
* page_size_kb
* 1024;
1766 /* in dual bank configuration, if there is a gap between banks
1767 * we fix up the sector offset to consider this gap */
1768 if (i
>= stm32l4_info
->bank1_sectors
&& stm32l4_info
->hole_sectors
)
1769 bank
->sectors
[i
].offset
+= gap_size_kb
* 1024;
1770 bank
->sectors
[i
].size
= page_size_kb
* 1024;
1771 bank
->sectors
[i
].is_erased
= -1;
1772 bank
->sectors
[i
].is_protected
= 1;
1775 stm32l4_info
->probed
= true;
1779 static int stm32l4_auto_probe(struct flash_bank
*bank
)
1781 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1782 if (stm32l4_info
->probed
) {
1785 /* read flash option register and re-probe if optr value is changed */
1786 int retval
= stm32l4_read_flash_reg_by_index(bank
, STM32_FLASH_OPTR_INDEX
, &optr_cur
);
1787 if (retval
!= ERROR_OK
)
1790 if (stm32l4_info
->optr
== optr_cur
)
1794 return stm32l4_probe(bank
);
1797 static int get_stm32l4_info(struct flash_bank
*bank
, struct command_invocation
*cmd
)
1799 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1800 const struct stm32l4_part_info
*part_info
= stm32l4_info
->part_info
;
1803 const uint16_t rev_id
= stm32l4_info
->idcode
>> 16;
1804 command_print_sameline(cmd
, "%s - Rev %s : 0x%04x", part_info
->device_str
,
1805 get_stm32l4_rev_str(bank
), rev_id
);
1806 if (stm32l4_info
->probed
)
1807 command_print_sameline(cmd
, " - %s-bank", get_stm32l4_bank_type_str(bank
));
1809 command_print_sameline(cmd
, "Cannot identify target as an %s device", device_families
);
1815 static int stm32l4_mass_erase(struct flash_bank
*bank
)
1817 int retval
, retval2
;
1818 struct target
*target
= bank
->target
;
1819 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1821 if (stm32l4_is_otp(bank
)) {
1822 LOG_ERROR("cannot erase OTP memory");
1823 return ERROR_FLASH_OPER_UNSUPPORTED
;
1826 uint32_t action
= FLASH_MER1
;
1828 if (stm32l4_info
->part_info
->flags
& F_HAS_DUAL_BANK
)
1829 action
|= FLASH_MER2
;
1831 if (target
->state
!= TARGET_HALTED
) {
1832 LOG_ERROR("Target not halted");
1833 return ERROR_TARGET_NOT_HALTED
;
1836 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0
)) {
1837 /* set all FLASH pages as secure */
1838 retval
= stm32l4_set_secbb(bank
, FLASH_SECBB_SECURE
);
1839 if (retval
!= ERROR_OK
) {
1840 /* restore all FLASH pages as non-secure */
1841 stm32l4_set_secbb(bank
, FLASH_SECBB_NON_SECURE
); /* ignore the return value */
1846 retval
= stm32l4_unlock_reg(bank
);
1847 if (retval
!= ERROR_OK
)
1850 /* mass erase flash memory */
1851 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
/ 10);
1852 if (retval
!= ERROR_OK
)
1855 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, action
);
1856 if (retval
!= ERROR_OK
)
1859 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, action
| FLASH_STRT
);
1860 if (retval
!= ERROR_OK
)
1863 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
1866 retval2
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, FLASH_LOCK
);
1868 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0
)) {
1869 /* restore all FLASH pages as non-secure */
1870 int retval3
= stm32l4_set_secbb(bank
, FLASH_SECBB_NON_SECURE
);
1871 if (retval3
!= ERROR_OK
)
1875 if (retval
!= ERROR_OK
)
1881 COMMAND_HANDLER(stm32l4_handle_mass_erase_command
)
1884 command_print(CMD
, "stm32l4x mass_erase <STM32L4 bank>");
1885 return ERROR_COMMAND_SYNTAX_ERROR
;
1888 struct flash_bank
*bank
;
1889 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1890 if (retval
!= ERROR_OK
)
1893 retval
= stm32l4_mass_erase(bank
);
1894 if (retval
== ERROR_OK
)
1895 command_print(CMD
, "stm32l4x mass erase complete");
1897 command_print(CMD
, "stm32l4x mass erase failed");
1902 COMMAND_HANDLER(stm32l4_handle_option_read_command
)
1905 command_print(CMD
, "stm32l4x option_read <STM32L4 bank> <option_reg offset>");
1906 return ERROR_COMMAND_SYNTAX_ERROR
;
1909 struct flash_bank
*bank
;
1910 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1911 if (retval
!= ERROR_OK
)
1914 uint32_t reg_offset
, reg_addr
;
1917 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], reg_offset
);
1918 reg_addr
= stm32l4_get_flash_reg(bank
, reg_offset
);
1920 retval
= stm32l4_read_flash_reg(bank
, reg_offset
, &value
);
1921 if (retval
!= ERROR_OK
)
1924 command_print(CMD
, "Option Register: <0x%" PRIx32
"> = 0x%" PRIx32
"", reg_addr
, value
);
1929 COMMAND_HANDLER(stm32l4_handle_option_write_command
)
1932 command_print(CMD
, "stm32l4x option_write <STM32L4 bank> <option_reg offset> <value> [mask]");
1933 return ERROR_COMMAND_SYNTAX_ERROR
;
1936 struct flash_bank
*bank
;
1937 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1938 if (retval
!= ERROR_OK
)
1941 uint32_t reg_offset
;
1943 uint32_t mask
= 0xFFFFFFFF;
1945 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], reg_offset
);
1946 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], value
);
1949 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[3], mask
);
1951 command_print(CMD
, "%s Option written.\n"
1952 "INFO: a reset or power cycle is required "
1953 "for the new settings to take effect.", bank
->driver
->name
);
1955 retval
= stm32l4_write_option(bank
, reg_offset
, value
, mask
);
1959 COMMAND_HANDLER(stm32l4_handle_trustzone_command
)
1961 if (CMD_ARGC
< 1 || CMD_ARGC
> 2)
1962 return ERROR_COMMAND_SYNTAX_ERROR
;
1964 struct flash_bank
*bank
;
1965 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1966 if (retval
!= ERROR_OK
)
1969 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1970 if (!(stm32l4_info
->part_info
->flags
& F_HAS_TZ
)) {
1971 LOG_ERROR("This device does not have a TrustZone");
1975 retval
= stm32l4_read_flash_reg_by_index(bank
, STM32_FLASH_OPTR_INDEX
, &stm32l4_info
->optr
);
1976 if (retval
!= ERROR_OK
)
1979 stm32l4_sync_rdp_tzen(bank
);
1981 if (CMD_ARGC
== 1) {
1982 /* only display the TZEN value */
1983 LOG_INFO("Global TrustZone Security is %s", stm32l4_info
->tzen
? "enabled" : "disabled");
1988 COMMAND_PARSE_ENABLE(CMD_ARGV
[1], new_tzen
);
1990 if (new_tzen
== stm32l4_info
->tzen
) {
1991 LOG_INFO("The requested TZEN is already programmed");
1996 if (stm32l4_info
->rdp
!= RDP_LEVEL_0
) {
1997 LOG_ERROR("TZEN can be set only when RDP level is 0");
2000 retval
= stm32l4_write_option(bank
, stm32l4_info
->flash_regs
[STM32_FLASH_OPTR_INDEX
],
2001 FLASH_TZEN
, FLASH_TZEN
);
2003 /* Deactivation of TZEN (from 1 to 0) is only possible when the RDP is
2004 * changing to level 0 (from level 1 to level 0 or from level 0.5 to level 0). */
2005 if (stm32l4_info
->rdp
!= RDP_LEVEL_1
&& stm32l4_info
->rdp
!= RDP_LEVEL_0_5
) {
2006 LOG_ERROR("Deactivation of TZEN is only possible when the RDP is changing to level 0");
2010 retval
= stm32l4_write_option(bank
, stm32l4_info
->flash_regs
[STM32_FLASH_OPTR_INDEX
],
2011 RDP_LEVEL_0
, FLASH_RDP_MASK
| FLASH_TZEN
);
2014 if (retval
!= ERROR_OK
)
2017 return stm32l4_perform_obl_launch(bank
);
2020 COMMAND_HANDLER(stm32l4_handle_option_load_command
)
2023 return ERROR_COMMAND_SYNTAX_ERROR
;
2025 struct flash_bank
*bank
;
2026 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2027 if (retval
!= ERROR_OK
)
2030 retval
= stm32l4_perform_obl_launch(bank
);
2031 if (retval
!= ERROR_OK
) {
2032 command_print(CMD
, "stm32l4x option load failed");
2037 command_print(CMD
, "stm32l4x option load completed. Power-on reset might be required");
2042 COMMAND_HANDLER(stm32l4_handle_lock_command
)
2044 struct target
*target
= NULL
;
2047 return ERROR_COMMAND_SYNTAX_ERROR
;
2049 struct flash_bank
*bank
;
2050 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2051 if (retval
!= ERROR_OK
)
2054 if (stm32l4_is_otp(bank
)) {
2055 LOG_ERROR("cannot lock/unlock OTP memory");
2056 return ERROR_FLASH_OPER_UNSUPPORTED
;
2059 target
= bank
->target
;
2061 if (target
->state
!= TARGET_HALTED
) {
2062 LOG_ERROR("Target not halted");
2063 return ERROR_TARGET_NOT_HALTED
;
2066 /* set readout protection level 1 by erasing the RDP option byte */
2067 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
2068 if (stm32l4_write_option(bank
, stm32l4_info
->flash_regs
[STM32_FLASH_OPTR_INDEX
],
2069 RDP_LEVEL_1
, FLASH_RDP_MASK
) != ERROR_OK
) {
2070 command_print(CMD
, "%s failed to lock device", bank
->driver
->name
);
2077 COMMAND_HANDLER(stm32l4_handle_unlock_command
)
2079 struct target
*target
= NULL
;
2082 return ERROR_COMMAND_SYNTAX_ERROR
;
2084 struct flash_bank
*bank
;
2085 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2086 if (retval
!= ERROR_OK
)
2089 if (stm32l4_is_otp(bank
)) {
2090 LOG_ERROR("cannot lock/unlock OTP memory");
2091 return ERROR_FLASH_OPER_UNSUPPORTED
;
2094 target
= bank
->target
;
2096 if (target
->state
!= TARGET_HALTED
) {
2097 LOG_ERROR("Target not halted");
2098 return ERROR_TARGET_NOT_HALTED
;
2101 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
2102 if (stm32l4_write_option(bank
, stm32l4_info
->flash_regs
[STM32_FLASH_OPTR_INDEX
],
2103 RDP_LEVEL_0
, FLASH_RDP_MASK
) != ERROR_OK
) {
2104 command_print(CMD
, "%s failed to unlock device", bank
->driver
->name
);
2111 COMMAND_HANDLER(stm32l4_handle_wrp_info_command
)
2113 if (CMD_ARGC
< 1 || CMD_ARGC
> 2)
2114 return ERROR_COMMAND_SYNTAX_ERROR
;
2116 struct flash_bank
*bank
;
2117 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2118 if (retval
!= ERROR_OK
)
2121 if (stm32l4_is_otp(bank
)) {
2122 LOG_ERROR("OTP memory does not have write protection areas");
2123 return ERROR_FLASH_OPER_UNSUPPORTED
;
2126 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
2127 enum stm32_bank_id dev_bank_id
= STM32_ALL_BANKS
;
2128 if (CMD_ARGC
== 2) {
2129 if (strcmp(CMD_ARGV
[1], "bank1") == 0)
2130 dev_bank_id
= STM32_BANK1
;
2131 else if (strcmp(CMD_ARGV
[1], "bank2") == 0)
2132 dev_bank_id
= STM32_BANK2
;
2134 return ERROR_COMMAND_ARGUMENT_INVALID
;
2137 if (dev_bank_id
== STM32_BANK2
) {
2138 if (!(stm32l4_info
->part_info
->flags
& F_HAS_DUAL_BANK
)) {
2139 LOG_ERROR("this device has no second bank");
2141 } else if (!stm32l4_info
->dual_bank_mode
) {
2142 LOG_ERROR("this device is configured in single bank mode");
2148 unsigned int n_wrp
, i
;
2149 struct stm32l4_wrp wrpxy
[4];
2151 ret
= stm32l4_get_all_wrpxy(bank
, dev_bank_id
, wrpxy
, &n_wrp
);
2152 if (ret
!= ERROR_OK
)
2155 /* use bitmap and range helpers to better describe protected areas */
2156 DECLARE_BITMAP(pages
, bank
->num_sectors
);
2157 bitmap_zero(pages
, bank
->num_sectors
);
2159 for (i
= 0; i
< n_wrp
; i
++) {
2160 if (wrpxy
[i
].used
) {
2161 for (int p
= wrpxy
[i
].first
; p
<= wrpxy
[i
].last
; p
++)
2166 /* we have at most 'n_wrp' WRP areas */
2167 struct range ranges
[n_wrp
];
2168 unsigned int ranges_count
= 0;
2170 bitmap_to_ranges(pages
, bank
->num_sectors
, ranges
, &ranges_count
);
2172 if (ranges_count
> 0) {
2173 /* pretty-print the protected ranges */
2174 char *ranges_str
= range_print_alloc(ranges
, ranges_count
);
2175 command_print(CMD
, "protected areas: %s", ranges_str
);
2178 command_print(CMD
, "no protected areas");
2183 COMMAND_HANDLER(stm32l4_handle_otp_command
)
2186 return ERROR_COMMAND_SYNTAX_ERROR
;
2188 struct flash_bank
*bank
;
2189 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2190 if (retval
!= ERROR_OK
)
2193 if (!stm32l4_is_otp(bank
)) {
2194 command_print(CMD
, "the specified bank is not an OTP memory");
2197 if (strcmp(CMD_ARGV
[1], "enable") == 0)
2198 stm32l4_otp_enable(bank
, true);
2199 else if (strcmp(CMD_ARGV
[1], "disable") == 0)
2200 stm32l4_otp_enable(bank
, false);
2201 else if (strcmp(CMD_ARGV
[1], "show") == 0)
2202 command_print(CMD
, "OTP memory bank #%d is %s for write commands.",
2203 bank
->bank_number
, stm32l4_otp_is_enabled(bank
) ? "enabled" : "disabled");
2205 return ERROR_COMMAND_SYNTAX_ERROR
;
2210 static const struct command_registration stm32l4_exec_command_handlers
[] = {
2213 .handler
= stm32l4_handle_lock_command
,
2214 .mode
= COMMAND_EXEC
,
2216 .help
= "Lock entire flash device.",
2220 .handler
= stm32l4_handle_unlock_command
,
2221 .mode
= COMMAND_EXEC
,
2223 .help
= "Unlock entire protected flash device.",
2226 .name
= "mass_erase",
2227 .handler
= stm32l4_handle_mass_erase_command
,
2228 .mode
= COMMAND_EXEC
,
2230 .help
= "Erase entire flash device.",
2233 .name
= "option_read",
2234 .handler
= stm32l4_handle_option_read_command
,
2235 .mode
= COMMAND_EXEC
,
2236 .usage
= "bank_id reg_offset",
2237 .help
= "Read & Display device option bytes.",
2240 .name
= "option_write",
2241 .handler
= stm32l4_handle_option_write_command
,
2242 .mode
= COMMAND_EXEC
,
2243 .usage
= "bank_id reg_offset value mask",
2244 .help
= "Write device option bit fields with provided value.",
2247 .name
= "trustzone",
2248 .handler
= stm32l4_handle_trustzone_command
,
2249 .mode
= COMMAND_EXEC
,
2250 .usage
= "<bank_id> [enable|disable]",
2251 .help
= "Configure TrustZone security",
2255 .handler
= stm32l4_handle_wrp_info_command
,
2256 .mode
= COMMAND_EXEC
,
2257 .usage
= "bank_id [bank1|bank2]",
2258 .help
= "list the protected areas using WRP",
2261 .name
= "option_load",
2262 .handler
= stm32l4_handle_option_load_command
,
2263 .mode
= COMMAND_EXEC
,
2265 .help
= "Force re-load of device options (will cause device reset).",
2269 .handler
= stm32l4_handle_otp_command
,
2270 .mode
= COMMAND_EXEC
,
2271 .usage
= "<bank_id> <enable|disable|show>",
2272 .help
= "OTP (One Time Programmable) memory write enable/disable",
2274 COMMAND_REGISTRATION_DONE
2277 static const struct command_registration stm32l4_command_handlers
[] = {
2280 .mode
= COMMAND_ANY
,
2281 .help
= "stm32l4x flash command group",
2283 .chain
= stm32l4_exec_command_handlers
,
2285 COMMAND_REGISTRATION_DONE
2288 const struct flash_driver stm32l4x_flash
= {
2290 .commands
= stm32l4_command_handlers
,
2291 .flash_bank_command
= stm32l4_flash_bank_command
,
2292 .erase
= stm32l4_erase
,
2293 .protect
= stm32l4_protect
,
2294 .write
= stm32l4_write
,
2295 .read
= default_flash_read
,
2296 .probe
= stm32l4_probe
,
2297 .auto_probe
= stm32l4_auto_probe
,
2298 .erase_check
= default_flash_blank_check
,
2299 .protect_check
= stm32l4_protect_check
,
2300 .info
= get_stm32l4_info
,
2301 .free_driver_priv
= default_flash_free_driver_priv
,