1 /***************************************************************************
2 * Copyright (C) 2015 by Uwe Bonnes *
3 * bon@elektron.ikp.physik.tu-darmstadt.de *
5 * Copyright (C) 2019 by Tarek Bochkati for STMicroelectronics *
6 * tarek.bouchkati@gmail.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
20 ***************************************************************************/
27 #include <helper/binarybuffer.h>
28 #include <target/algorithm.h>
29 #include <target/armv7m.h>
32 /* STM32L4xxx series for reference.
34 * RM0351 (STM32L4x5/STM32L4x6)
35 * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
37 * RM0394 (STM32L43x/44x/45x/46x)
38 * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
40 * RM0432 (STM32L4R/4Sxx)
41 * http://www.st.com/resource/en/reference_manual/dm00310109.pdf
43 * STM32L476RG Datasheet (for erase timing)
44 * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
46 * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
47 * an option byte is available to map all sectors to the first bank.
48 * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
51 * RM0394 devices have a single bank only.
53 * RM0432 devices have single and dual bank operating modes.
54 * - for STM32L4R/Sxx the FLASH size is 2Mbyte or 1Mbyte.
55 * - for STM32L4P/Q5x the FLASH size is 1Mbyte or 512Kbyte.
56 * Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
58 * Bank mode is controlled by two different bits in option bytes register.
60 * In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
61 * In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
63 * In 1M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
64 * In 512K FLASH devices bit 21 (DB512K) controls Dual Bank mode.
68 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
70 #define FLASH_ERASE_TIMEOUT 250
72 /* Flash registers offsets */
73 #define STM32_FLASH_ACR 0x00
74 #define STM32_FLASH_KEYR 0x08
75 #define STM32_FLASH_OPTKEYR 0x0c
76 #define STM32_FLASH_SR 0x10
77 #define STM32_FLASH_CR 0x14
78 #define STM32_FLASH_OPTR 0x20
79 #define STM32_FLASH_WRP1AR 0x2c
80 #define STM32_FLASH_WRP1BR 0x30
81 #define STM32_FLASH_WRP2AR 0x4c
82 #define STM32_FLASH_WRP2BR 0x50
84 /* FLASH_CR register bits */
85 #define FLASH_PG (1 << 0)
86 #define FLASH_PER (1 << 1)
87 #define FLASH_MER1 (1 << 2)
88 #define FLASH_PAGE_SHIFT 3
89 #define FLASH_CR_BKER (1 << 11)
90 #define FLASH_MER2 (1 << 15)
91 #define FLASH_STRT (1 << 16)
92 #define FLASH_OPTSTRT (1 << 17)
93 #define FLASH_EOPIE (1 << 24)
94 #define FLASH_ERRIE (1 << 25)
95 #define FLASH_OBLLAUNCH (1 << 27)
96 #define FLASH_OPTLOCK (1 << 30)
97 #define FLASH_LOCK (1 << 31)
99 /* FLASH_SR register bits */
100 #define FLASH_BSY (1 << 16)
101 /* Fast programming not used => related errors not used*/
102 #define FLASH_PGSERR (1 << 7) /* Programming sequence error */
103 #define FLASH_SIZERR (1 << 6) /* Size error */
104 #define FLASH_PGAERR (1 << 5) /* Programming alignment error */
105 #define FLASH_WRPERR (1 << 4) /* Write protection error */
106 #define FLASH_PROGERR (1 << 3) /* Programming error */
107 #define FLASH_OPERR (1 << 1) /* Operation error */
108 #define FLASH_EOP (1 << 0) /* End of operation */
109 #define FLASH_ERROR (FLASH_PGSERR | FLASH_SIZERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_PROGERR | FLASH_OPERR)
111 /* register unlock keys */
112 #define KEY1 0x45670123
113 #define KEY2 0xCDEF89AB
115 /* option register unlock key */
116 #define OPTKEY1 0x08192A3B
117 #define OPTKEY2 0x4C5D6E7F
119 #define RDP_LEVEL_0 0xAA
120 #define RDP_LEVEL_1 0xBB
121 #define RDP_LEVEL_2 0xCC
124 /* other registers */
125 #define DBGMCU_IDCODE 0xE0042000
133 struct stm32l4_part_info
{
135 const char *device_str
;
136 const struct stm32l4_rev
*revs
;
137 const size_t num_revs
;
138 const uint16_t max_flash_size_kb
;
139 const bool has_dual_bank
;
140 const uint32_t flash_regs_base
;
141 const uint32_t fsize_addr
;
144 struct stm32l4_flash_bank
{
150 const struct stm32l4_part_info
*part_info
;
153 static const struct stm32l4_rev stm32_415_revs
[] = {
154 { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
157 static const struct stm32l4_rev stm32_435_revs
[] = {
158 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
161 static const struct stm32l4_rev stm32_461_revs
[] = {
162 { 0x1000, "A" }, { 0x2000, "B" },
165 static const struct stm32l4_rev stm32_462_revs
[] = {
166 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
169 static const struct stm32l4_rev stm32_464_revs
[] = {
173 static const struct stm32l4_rev stm32_470_revs
[] = {
174 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" },
177 static const struct stm32l4_rev stm32_471_revs
[] = {
181 static const struct stm32l4_rev stm32_495_revs
[] = {
185 static const struct stm32l4_part_info stm32l4_parts
[] = {
188 .revs
= stm32_415_revs
,
189 .num_revs
= ARRAY_SIZE(stm32_415_revs
),
190 .device_str
= "STM32L47/L48xx",
191 .max_flash_size_kb
= 1024,
192 .has_dual_bank
= true,
193 .flash_regs_base
= 0x40022000,
194 .fsize_addr
= 0x1FFF75E0,
198 .revs
= stm32_435_revs
,
199 .num_revs
= ARRAY_SIZE(stm32_435_revs
),
200 .device_str
= "STM32L43/L44xx",
201 .max_flash_size_kb
= 256,
202 .has_dual_bank
= false,
203 .flash_regs_base
= 0x40022000,
204 .fsize_addr
= 0x1FFF75E0,
208 .revs
= stm32_461_revs
,
209 .num_revs
= ARRAY_SIZE(stm32_461_revs
),
210 .device_str
= "STM32L49/L4Axx",
211 .max_flash_size_kb
= 1024,
212 .has_dual_bank
= true,
213 .flash_regs_base
= 0x40022000,
214 .fsize_addr
= 0x1FFF75E0,
218 .revs
= stm32_462_revs
,
219 .num_revs
= ARRAY_SIZE(stm32_462_revs
),
220 .device_str
= "STM32L45/L46xx",
221 .max_flash_size_kb
= 512,
222 .has_dual_bank
= false,
223 .flash_regs_base
= 0x40022000,
224 .fsize_addr
= 0x1FFF75E0,
228 .revs
= stm32_464_revs
,
229 .num_revs
= ARRAY_SIZE(stm32_464_revs
),
230 .device_str
= "STM32L41/L42xx",
231 .max_flash_size_kb
= 128,
232 .has_dual_bank
= false,
233 .flash_regs_base
= 0x40022000,
234 .fsize_addr
= 0x1FFF75E0,
238 .revs
= stm32_470_revs
,
239 .num_revs
= ARRAY_SIZE(stm32_470_revs
),
240 .device_str
= "STM32L4R/L4Sxx",
241 .max_flash_size_kb
= 2048,
242 .has_dual_bank
= true,
243 .flash_regs_base
= 0x40022000,
244 .fsize_addr
= 0x1FFF75E0,
248 .revs
= stm32_471_revs
,
249 .num_revs
= ARRAY_SIZE(stm32_471_revs
),
250 .device_str
= "STM32L4P5/L4Q5x",
251 .max_flash_size_kb
= 1024,
252 .has_dual_bank
= true,
253 .flash_regs_base
= 0x40022000,
254 .fsize_addr
= 0x1FFF75E0,
258 .revs
= stm32_495_revs
,
259 .num_revs
= ARRAY_SIZE(stm32_495_revs
),
260 .device_str
= "STM32WB5x",
261 .max_flash_size_kb
= 1024,
262 .has_dual_bank
= false,
263 .flash_regs_base
= 0x58004000,
264 .fsize_addr
= 0x1FFF75E0,
268 /* flash bank stm32l4x <base> <size> 0 0 <target#> */
269 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command
)
271 struct stm32l4_flash_bank
*stm32l4_info
;
274 return ERROR_COMMAND_SYNTAX_ERROR
;
276 stm32l4_info
= malloc(sizeof(struct stm32l4_flash_bank
));
278 return ERROR_FAIL
; /* Checkme: What better error to use?*/
279 bank
->driver_priv
= stm32l4_info
;
281 /* The flash write must be aligned to a double word (8-bytes) boundary.
282 * Ask the flash infrastructure to ensure required alignment */
283 bank
->write_start_alignment
= bank
->write_end_alignment
= 8;
285 stm32l4_info
->probed
= 0;
290 static inline uint32_t stm32l4_get_flash_reg(struct flash_bank
*bank
, uint32_t reg_offset
)
292 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
293 return stm32l4_info
->part_info
->flash_regs_base
+ reg_offset
;
296 static inline int stm32l4_read_flash_reg(struct flash_bank
*bank
, uint32_t reg_offset
, uint32_t *value
)
298 return target_read_u32(bank
->target
, stm32l4_get_flash_reg(bank
, reg_offset
), value
);
301 static inline int stm32l4_write_flash_reg(struct flash_bank
*bank
, uint32_t reg_offset
, uint32_t value
)
303 return target_write_u32(bank
->target
, stm32l4_get_flash_reg(bank
, reg_offset
), value
);
306 static int stm32l4_wait_status_busy(struct flash_bank
*bank
, int timeout
)
309 int retval
= ERROR_OK
;
311 /* wait for busy to clear */
313 retval
= stm32l4_read_flash_reg(bank
, STM32_FLASH_SR
, &status
);
314 if (retval
!= ERROR_OK
)
316 LOG_DEBUG("status: 0x%" PRIx32
"", status
);
317 if ((status
& FLASH_BSY
) == 0)
319 if (timeout
-- <= 0) {
320 LOG_ERROR("timed out waiting for flash");
327 if (status
& FLASH_WRPERR
) {
328 LOG_ERROR("stm32x device protected");
332 /* Clear but report errors */
333 if (status
& FLASH_ERROR
) {
334 if (retval
== ERROR_OK
)
336 /* If this operation fails, we ignore it and report the original
339 stm32l4_write_flash_reg(bank
, STM32_FLASH_SR
, status
& FLASH_ERROR
);
345 static int stm32l4_unlock_reg(struct flash_bank
*bank
)
349 /* first check if not already unlocked
350 * otherwise writing on STM32_FLASH_KEYR will fail
352 int retval
= stm32l4_read_flash_reg(bank
, STM32_FLASH_CR
, &ctrl
);
353 if (retval
!= ERROR_OK
)
356 if ((ctrl
& FLASH_LOCK
) == 0)
359 /* unlock flash registers */
360 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_KEYR
, KEY1
);
361 if (retval
!= ERROR_OK
)
364 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_KEYR
, KEY2
);
365 if (retval
!= ERROR_OK
)
368 retval
= stm32l4_read_flash_reg(bank
, STM32_FLASH_CR
, &ctrl
);
369 if (retval
!= ERROR_OK
)
372 if (ctrl
& FLASH_LOCK
) {
373 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32
, ctrl
);
374 return ERROR_TARGET_FAILURE
;
380 static int stm32l4_unlock_option_reg(struct flash_bank
*bank
)
384 int retval
= stm32l4_read_flash_reg(bank
, STM32_FLASH_CR
, &ctrl
);
385 if (retval
!= ERROR_OK
)
388 if ((ctrl
& FLASH_OPTLOCK
) == 0)
391 /* unlock option registers */
392 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_OPTKEYR
, OPTKEY1
);
393 if (retval
!= ERROR_OK
)
396 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_OPTKEYR
, OPTKEY2
);
397 if (retval
!= ERROR_OK
)
400 retval
= stm32l4_read_flash_reg(bank
, STM32_FLASH_CR
, &ctrl
);
401 if (retval
!= ERROR_OK
)
404 if (ctrl
& FLASH_OPTLOCK
) {
405 LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32
, ctrl
);
406 return ERROR_TARGET_FAILURE
;
412 static int stm32l4_write_option(struct flash_bank
*bank
, uint32_t reg_offset
, uint32_t value
, uint32_t mask
)
416 int retval
= stm32l4_read_flash_reg(bank
, reg_offset
, &optiondata
);
417 if (retval
!= ERROR_OK
)
420 retval
= stm32l4_unlock_reg(bank
);
421 if (retval
!= ERROR_OK
)
424 retval
= stm32l4_unlock_option_reg(bank
);
425 if (retval
!= ERROR_OK
)
428 optiondata
= (optiondata
& ~mask
) | (value
& mask
);
430 retval
= stm32l4_write_flash_reg(bank
, reg_offset
, optiondata
);
431 if (retval
!= ERROR_OK
)
434 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, FLASH_OPTSTRT
);
435 if (retval
!= ERROR_OK
)
438 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
439 if (retval
!= ERROR_OK
)
445 static int stm32l4_protect_check(struct flash_bank
*bank
)
447 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
449 uint32_t wrp1ar
, wrp1br
, wrp2ar
, wrp2br
;
450 stm32l4_read_flash_reg(bank
, STM32_FLASH_WRP1AR
, &wrp1ar
);
451 stm32l4_read_flash_reg(bank
, STM32_FLASH_WRP1BR
, &wrp1br
);
452 stm32l4_read_flash_reg(bank
, STM32_FLASH_WRP2AR
, &wrp2ar
);
453 stm32l4_read_flash_reg(bank
, STM32_FLASH_WRP2BR
, &wrp2br
);
455 const uint8_t wrp1a_start
= wrp1ar
& 0xFF;
456 const uint8_t wrp1a_end
= (wrp1ar
>> 16) & 0xFF;
457 const uint8_t wrp1b_start
= wrp1br
& 0xFF;
458 const uint8_t wrp1b_end
= (wrp1br
>> 16) & 0xFF;
459 const uint8_t wrp2a_start
= wrp2ar
& 0xFF;
460 const uint8_t wrp2a_end
= (wrp2ar
>> 16) & 0xFF;
461 const uint8_t wrp2b_start
= wrp2br
& 0xFF;
462 const uint8_t wrp2b_end
= (wrp2br
>> 16) & 0xFF;
464 for (int i
= 0; i
< bank
->num_sectors
; i
++) {
465 if (i
< stm32l4_info
->bank1_sectors
) {
466 if (((i
>= wrp1a_start
) &&
468 ((i
>= wrp1b_start
) &&
470 bank
->sectors
[i
].is_protected
= 1;
472 bank
->sectors
[i
].is_protected
= 0;
475 snb
= i
- stm32l4_info
->bank1_sectors
;
476 if (((snb
>= wrp2a_start
) &&
477 (snb
<= wrp2a_end
)) ||
478 ((snb
>= wrp2b_start
) &&
480 bank
->sectors
[i
].is_protected
= 1;
482 bank
->sectors
[i
].is_protected
= 0;
488 static int stm32l4_erase(struct flash_bank
*bank
, int first
, int last
)
490 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
494 assert(first
< bank
->num_sectors
);
495 assert(last
< bank
->num_sectors
);
497 if (bank
->target
->state
!= TARGET_HALTED
) {
498 LOG_ERROR("Target not halted");
499 return ERROR_TARGET_NOT_HALTED
;
502 retval
= stm32l4_unlock_reg(bank
);
503 if (retval
!= ERROR_OK
)
508 To erase a sector, follow the procedure below:
509 1. Check that no Flash memory operation is ongoing by
510 checking the BSY bit in the FLASH_SR register
511 2. Set the PER bit and select the page and bank
512 you wish to erase in the FLASH_CR register
513 3. Set the STRT bit in the FLASH_CR register
514 4. Wait for the BSY bit to be cleared
517 for (i
= first
; i
<= last
; i
++) {
518 uint32_t erase_flags
;
519 erase_flags
= FLASH_PER
| FLASH_STRT
;
521 if (i
>= stm32l4_info
->bank1_sectors
) {
523 snb
= i
- stm32l4_info
->bank1_sectors
;
524 erase_flags
|= snb
<< FLASH_PAGE_SHIFT
| FLASH_CR_BKER
;
526 erase_flags
|= i
<< FLASH_PAGE_SHIFT
;
527 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, erase_flags
);
528 if (retval
!= ERROR_OK
)
531 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
532 if (retval
!= ERROR_OK
)
535 bank
->sectors
[i
].is_erased
= 1;
538 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, FLASH_LOCK
);
539 if (retval
!= ERROR_OK
)
545 static int stm32l4_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
547 struct target
*target
= bank
->target
;
548 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
550 if (target
->state
!= TARGET_HALTED
) {
551 LOG_ERROR("Target not halted");
552 return ERROR_TARGET_NOT_HALTED
;
557 uint32_t reg_value
= 0xFF; /* Default to bank un-protected */
558 if (last
>= stm32l4_info
->bank1_sectors
) {
560 uint8_t begin
= first
> stm32l4_info
->bank1_sectors
? first
: 0x00;
561 reg_value
= ((last
& 0xFF) << 16) | begin
;
564 ret
= stm32l4_write_option(bank
, STM32_FLASH_WRP2AR
, reg_value
, 0xffffffff);
567 reg_value
= 0xFF; /* Default to bank un-protected */
568 if (first
< stm32l4_info
->bank1_sectors
) {
570 uint8_t end
= last
>= stm32l4_info
->bank1_sectors
? 0xFF : last
;
571 reg_value
= (end
<< 16) | (first
& 0xFF);
574 ret
= stm32l4_write_option(bank
, STM32_FLASH_WRP1AR
, reg_value
, 0xffffffff);
580 /* Count is in double-words */
581 static int stm32l4_write_block(struct flash_bank
*bank
, const uint8_t *buffer
,
582 uint32_t offset
, uint32_t count
)
584 struct target
*target
= bank
->target
;
585 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
586 uint32_t buffer_size
= 16384;
587 struct working_area
*write_algorithm
;
588 struct working_area
*source
;
589 uint32_t address
= bank
->base
+ offset
;
590 struct reg_param reg_params
[5];
591 struct armv7m_algorithm armv7m_info
;
592 int retval
= ERROR_OK
;
594 static const uint8_t stm32l4_flash_write_code
[] = {
595 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
598 if (target_alloc_working_area(target
, sizeof(stm32l4_flash_write_code
),
599 &write_algorithm
) != ERROR_OK
) {
600 LOG_WARNING("no working area available, can't do block memory writes");
601 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
604 retval
= target_write_buffer(target
, write_algorithm
->address
,
605 sizeof(stm32l4_flash_write_code
),
606 stm32l4_flash_write_code
);
607 if (retval
!= ERROR_OK
) {
608 target_free_working_area(target
, write_algorithm
);
613 while (target_alloc_working_area_try(target
, buffer_size
, &source
) !=
616 if (buffer_size
<= 256) {
617 /* we already allocated the writing code, but failed to get a
618 * buffer, free the algorithm */
619 target_free_working_area(target
, write_algorithm
);
621 LOG_WARNING("large enough working area not available, can't do block memory writes");
622 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
626 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
627 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
629 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* buffer start, status (out) */
630 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* buffer end */
631 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* target address */
632 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
); /* count (double word-64bit) */
633 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
); /* flash regs base */
635 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
636 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
+ source
->size
);
637 buf_set_u32(reg_params
[2].value
, 0, 32, address
);
638 buf_set_u32(reg_params
[3].value
, 0, 32, count
);
639 buf_set_u32(reg_params
[4].value
, 0, 32, stm32l4_info
->part_info
->flash_regs_base
);
641 retval
= target_run_flash_async_algorithm(target
, buffer
, count
, 8,
644 source
->address
, source
->size
,
645 write_algorithm
->address
, 0,
648 if (retval
== ERROR_FLASH_OPERATION_FAILED
) {
649 LOG_ERROR("error executing stm32l4 flash write algorithm");
651 uint32_t error
= buf_get_u32(reg_params
[0].value
, 0, 32) & FLASH_ERROR
;
653 if (error
& FLASH_WRPERR
)
654 LOG_ERROR("flash memory write protected");
657 LOG_ERROR("flash write failed = %08" PRIx32
, error
);
658 /* Clear but report errors */
659 stm32l4_write_flash_reg(bank
, STM32_FLASH_SR
, error
);
664 target_free_working_area(target
, source
);
665 target_free_working_area(target
, write_algorithm
);
667 destroy_reg_param(®_params
[0]);
668 destroy_reg_param(®_params
[1]);
669 destroy_reg_param(®_params
[2]);
670 destroy_reg_param(®_params
[3]);
671 destroy_reg_param(®_params
[4]);
676 static int stm32l4_write(struct flash_bank
*bank
, const uint8_t *buffer
,
677 uint32_t offset
, uint32_t count
)
681 if (bank
->target
->state
!= TARGET_HALTED
) {
682 LOG_ERROR("Target not halted");
683 return ERROR_TARGET_NOT_HALTED
;
686 /* The flash write must be aligned to a double word (8-bytes) boundary.
687 * The flash infrastructure ensures it, do just a security check */
688 assert(offset
% 8 == 0);
689 assert(count
% 8 == 0);
691 retval
= stm32l4_unlock_reg(bank
);
692 if (retval
!= ERROR_OK
)
695 retval
= stm32l4_write_block(bank
, buffer
, offset
, count
/ 8);
697 retval2
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, FLASH_LOCK
);
699 if (retval
!= ERROR_OK
) {
700 LOG_ERROR("block write failed");
706 static int stm32l4_read_idcode(struct flash_bank
*bank
, uint32_t *id
)
708 int retval
= target_read_u32(bank
->target
, DBGMCU_IDCODE
, id
);
709 if (retval
!= ERROR_OK
)
715 static int stm32l4_probe(struct flash_bank
*bank
)
717 struct target
*target
= bank
->target
;
718 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
719 const struct stm32l4_part_info
*part_info
;
721 uint16_t flash_size_in_kb
= 0xffff;
725 stm32l4_info
->probed
= 0;
727 /* read stm32 device id register */
728 int retval
= stm32l4_read_idcode(bank
, &stm32l4_info
->idcode
);
729 if (retval
!= ERROR_OK
)
732 device_id
= stm32l4_info
->idcode
& 0xFFF;
734 for (unsigned int n
= 0; n
< ARRAY_SIZE(stm32l4_parts
); n
++) {
735 if (device_id
== stm32l4_parts
[n
].id
)
736 stm32l4_info
->part_info
= &stm32l4_parts
[n
];
739 if (!stm32l4_info
->part_info
) {
740 LOG_WARNING("Cannot identify target as an STM32 L4 or WB family device.");
744 part_info
= stm32l4_info
->part_info
;
746 char device_info
[1024];
747 retval
= bank
->driver
->info(bank
, device_info
, sizeof(device_info
));
748 if (retval
!= ERROR_OK
)
751 LOG_INFO("device idcode = 0x%08" PRIx32
" (%s)", stm32l4_info
->idcode
, device_info
);
753 /* get flash size from target. */
754 retval
= target_read_u16(target
, part_info
->fsize_addr
, &flash_size_in_kb
);
756 /* failed reading flash size or flash size invalid (early silicon),
757 * default to max target family */
758 if (retval
!= ERROR_OK
|| flash_size_in_kb
== 0xffff || flash_size_in_kb
== 0
759 || flash_size_in_kb
> part_info
->max_flash_size_kb
) {
760 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
761 part_info
->max_flash_size_kb
);
762 flash_size_in_kb
= part_info
->max_flash_size_kb
;
765 LOG_INFO("flash size = %dkbytes", flash_size_in_kb
);
767 /* did we assign a flash size? */
768 assert((flash_size_in_kb
!= 0xffff) && flash_size_in_kb
);
770 /* read flash option register */
771 retval
= stm32l4_read_flash_reg(bank
, STM32_FLASH_OPTR
, &options
);
772 if (retval
!= ERROR_OK
)
775 stm32l4_info
->bank1_sectors
= 0;
776 stm32l4_info
->hole_sectors
= 0;
781 stm32l4_info
->dual_bank_mode
= false;
786 /* if flash size is max (1M) the device is always dual bank
787 * 0x415: has variants with 512K
788 * 0x461: has variants with 512 and 256
789 * for these variants:
790 * if DUAL_BANK = 0 -> single bank
791 * else -> dual bank without gap
792 * note: the page size is invariant
795 num_pages
= flash_size_in_kb
/ 2;
796 stm32l4_info
->bank1_sectors
= num_pages
;
798 /* check DUAL_BANK bit[21] if the flash is less than 1M */
799 if (flash_size_in_kb
== 1024 || (options
& BIT(21))) {
800 stm32l4_info
->dual_bank_mode
= true;
801 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
807 /* single bank flash */
809 num_pages
= flash_size_in_kb
/ 2;
810 stm32l4_info
->bank1_sectors
= num_pages
;
814 /* STM32L4R/S can be single/dual bank:
815 * if size = 2M check DBANK bit(22)
816 * if size = 1M check DB1M bit(21)
817 * STM32L4P/Q can be single/dual bank
818 * if size = 1M check DBANK bit(22)
819 * if size = 512K check DB512K bit(21)
820 * in single bank configuration the page size is 8K
821 * else (dual bank) the page size is 4K without gap between banks
824 num_pages
= flash_size_in_kb
/ 8;
825 stm32l4_info
->bank1_sectors
= num_pages
;
826 const bool use_dbank_bit
= flash_size_in_kb
== part_info
->max_flash_size_kb
;
827 if ((use_dbank_bit
&& (options
& BIT(22))) ||
828 (!use_dbank_bit
&& (options
& BIT(21)))) {
829 stm32l4_info
->dual_bank_mode
= true;
831 num_pages
= flash_size_in_kb
/ 4;
832 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
836 /* single bank flash */
838 num_pages
= flash_size_in_kb
/ 4;
839 stm32l4_info
->bank1_sectors
= num_pages
;
842 LOG_ERROR("unsupported device");
846 LOG_INFO("flash mode : %s-bank", stm32l4_info
->dual_bank_mode
? "dual" : "single");
848 const int gap_size
= stm32l4_info
->hole_sectors
* page_size
;
850 if (stm32l4_info
->dual_bank_mode
& gap_size
) {
851 LOG_INFO("gap detected starting from %0x08" PRIx32
" to %0x08" PRIx32
,
852 0x8000000 + stm32l4_info
->bank1_sectors
* page_size
,
853 0x8000000 + stm32l4_info
->bank1_sectors
* page_size
+ gap_size
);
858 bank
->sectors
= NULL
;
861 bank
->size
= flash_size_in_kb
* 1024 + gap_size
;
862 bank
->base
= 0x08000000;
863 bank
->num_sectors
= num_pages
;
864 bank
->sectors
= malloc(sizeof(struct flash_sector
) * bank
->num_sectors
);
865 if (bank
->sectors
== NULL
) {
866 LOG_ERROR("failed to allocate bank sectors");
870 for (i
= 0; i
< bank
->num_sectors
; i
++) {
871 bank
->sectors
[i
].offset
= i
* page_size
;
872 /* in dual bank configuration, if there is a gap between banks
873 * we fix up the sector offset to consider this gap */
874 if (i
>= stm32l4_info
->bank1_sectors
&& stm32l4_info
->hole_sectors
)
875 bank
->sectors
[i
].offset
+= gap_size
;
876 bank
->sectors
[i
].size
= page_size
;
877 bank
->sectors
[i
].is_erased
= -1;
878 bank
->sectors
[i
].is_protected
= 1;
881 stm32l4_info
->probed
= 1;
885 static int stm32l4_auto_probe(struct flash_bank
*bank
)
887 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
888 if (stm32l4_info
->probed
)
891 return stm32l4_probe(bank
);
894 static int get_stm32l4_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
896 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
897 const struct stm32l4_part_info
*part_info
= stm32l4_info
->part_info
;
900 const char *rev_str
= NULL
;
901 uint16_t rev_id
= stm32l4_info
->idcode
>> 16;
902 for (unsigned int i
= 0; i
< part_info
->num_revs
; i
++) {
903 if (rev_id
== part_info
->revs
[i
].rev
) {
904 rev_str
= part_info
->revs
[i
].str
;
906 if (rev_str
!= NULL
) {
907 snprintf(buf
, buf_size
, "%s - Rev: %s",
908 part_info
->device_str
, rev_str
);
914 snprintf(buf
, buf_size
, "%s - Rev: unknown (0x%04x)",
915 part_info
->device_str
, rev_id
);
918 snprintf(buf
, buf_size
, "Cannot identify target as an STM32 L4 or WB device");
925 static int stm32l4_mass_erase(struct flash_bank
*bank
)
928 struct target
*target
= bank
->target
;
929 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
931 uint32_t action
= FLASH_MER1
;
933 if (stm32l4_info
->part_info
->has_dual_bank
)
934 action
|= FLASH_MER2
;
936 if (target
->state
!= TARGET_HALTED
) {
937 LOG_ERROR("Target not halted");
938 return ERROR_TARGET_NOT_HALTED
;
941 retval
= stm32l4_unlock_reg(bank
);
942 if (retval
!= ERROR_OK
)
945 /* mass erase flash memory */
946 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
/ 10);
947 if (retval
!= ERROR_OK
)
950 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, action
);
951 if (retval
!= ERROR_OK
)
953 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, action
| FLASH_STRT
);
954 if (retval
!= ERROR_OK
)
957 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
958 if (retval
!= ERROR_OK
)
961 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, FLASH_LOCK
);
962 if (retval
!= ERROR_OK
)
968 COMMAND_HANDLER(stm32l4_handle_mass_erase_command
)
973 command_print(CMD
, "stm32l4x mass_erase <STM32L4 bank>");
974 return ERROR_COMMAND_SYNTAX_ERROR
;
977 struct flash_bank
*bank
;
978 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
979 if (ERROR_OK
!= retval
)
982 retval
= stm32l4_mass_erase(bank
);
983 if (retval
== ERROR_OK
) {
984 /* set all sectors as erased */
985 for (i
= 0; i
< bank
->num_sectors
; i
++)
986 bank
->sectors
[i
].is_erased
= 1;
988 command_print(CMD
, "stm32l4x mass erase complete");
990 command_print(CMD
, "stm32l4x mass erase failed");
996 COMMAND_HANDLER(stm32l4_handle_option_read_command
)
999 command_print(CMD
, "stm32l4x option_read <STM32L4 bank> <option_reg offset>");
1000 return ERROR_COMMAND_SYNTAX_ERROR
;
1003 struct flash_bank
*bank
;
1004 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1005 if (ERROR_OK
!= retval
)
1008 uint32_t reg_offset
, reg_addr
;
1011 reg_offset
= strtoul(CMD_ARGV
[1], NULL
, 16);
1012 reg_addr
= stm32l4_get_flash_reg(bank
, reg_offset
);
1014 retval
= stm32l4_read_flash_reg(bank
, reg_offset
, &value
);
1015 if (ERROR_OK
!= retval
)
1018 command_print(CMD
, "Option Register: <0x%" PRIx32
"> = 0x%" PRIx32
"", reg_addr
, value
);
1023 COMMAND_HANDLER(stm32l4_handle_option_write_command
)
1026 command_print(CMD
, "stm32l4x option_write <STM32L4 bank> <option_reg offset> <value> [mask]");
1027 return ERROR_COMMAND_SYNTAX_ERROR
;
1030 struct flash_bank
*bank
;
1031 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1032 if (ERROR_OK
!= retval
)
1035 uint32_t reg_offset
;
1037 uint32_t mask
= 0xFFFFFFFF;
1039 reg_offset
= strtoul(CMD_ARGV
[1], NULL
, 16);
1040 value
= strtoul(CMD_ARGV
[2], NULL
, 16);
1042 mask
= strtoul(CMD_ARGV
[3], NULL
, 16);
1044 command_print(CMD
, "%s Option written.\n"
1045 "INFO: a reset or power cycle is required "
1046 "for the new settings to take effect.", bank
->driver
->name
);
1048 retval
= stm32l4_write_option(bank
, reg_offset
, value
, mask
);
1052 COMMAND_HANDLER(stm32l4_handle_option_load_command
)
1055 return ERROR_COMMAND_SYNTAX_ERROR
;
1057 struct flash_bank
*bank
;
1058 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1059 if (ERROR_OK
!= retval
)
1062 retval
= stm32l4_unlock_reg(bank
);
1063 if (ERROR_OK
!= retval
)
1066 retval
= stm32l4_unlock_option_reg(bank
);
1067 if (ERROR_OK
!= retval
)
1070 /* Write the OBLLAUNCH bit in CR -> Cause device "POR" and option bytes reload */
1071 retval
= stm32l4_write_flash_reg(bank
, STM32_FLASH_CR
, FLASH_OBLLAUNCH
);
1073 command_print(CMD
, "stm32l4x option load (POR) completed.");
1077 COMMAND_HANDLER(stm32l4_handle_lock_command
)
1079 struct target
*target
= NULL
;
1082 return ERROR_COMMAND_SYNTAX_ERROR
;
1084 struct flash_bank
*bank
;
1085 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1086 if (ERROR_OK
!= retval
)
1089 target
= bank
->target
;
1091 if (target
->state
!= TARGET_HALTED
) {
1092 LOG_ERROR("Target not halted");
1093 return ERROR_TARGET_NOT_HALTED
;
1096 /* set readout protection level 1 by erasing the RDP option byte */
1097 if (stm32l4_write_option(bank
, STM32_FLASH_OPTR
, 0, 0x000000FF) != ERROR_OK
) {
1098 command_print(CMD
, "%s failed to lock device", bank
->driver
->name
);
1105 COMMAND_HANDLER(stm32l4_handle_unlock_command
)
1107 struct target
*target
= NULL
;
1110 return ERROR_COMMAND_SYNTAX_ERROR
;
1112 struct flash_bank
*bank
;
1113 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1114 if (ERROR_OK
!= retval
)
1117 target
= bank
->target
;
1119 if (target
->state
!= TARGET_HALTED
) {
1120 LOG_ERROR("Target not halted");
1121 return ERROR_TARGET_NOT_HALTED
;
1124 if (stm32l4_write_option(bank
, STM32_FLASH_OPTR
, RDP_LEVEL_0
, 0x000000FF) != ERROR_OK
) {
1125 command_print(CMD
, "%s failed to unlock device", bank
->driver
->name
);
1132 static const struct command_registration stm32l4_exec_command_handlers
[] = {
1135 .handler
= stm32l4_handle_lock_command
,
1136 .mode
= COMMAND_EXEC
,
1138 .help
= "Lock entire flash device.",
1142 .handler
= stm32l4_handle_unlock_command
,
1143 .mode
= COMMAND_EXEC
,
1145 .help
= "Unlock entire protected flash device.",
1148 .name
= "mass_erase",
1149 .handler
= stm32l4_handle_mass_erase_command
,
1150 .mode
= COMMAND_EXEC
,
1152 .help
= "Erase entire flash device.",
1155 .name
= "option_read",
1156 .handler
= stm32l4_handle_option_read_command
,
1157 .mode
= COMMAND_EXEC
,
1158 .usage
= "bank_id reg_offset",
1159 .help
= "Read & Display device option bytes.",
1162 .name
= "option_write",
1163 .handler
= stm32l4_handle_option_write_command
,
1164 .mode
= COMMAND_EXEC
,
1165 .usage
= "bank_id reg_offset value mask",
1166 .help
= "Write device option bit fields with provided value.",
1169 .name
= "option_load",
1170 .handler
= stm32l4_handle_option_load_command
,
1171 .mode
= COMMAND_EXEC
,
1173 .help
= "Force re-load of device options (will cause device reset).",
1175 COMMAND_REGISTRATION_DONE
1178 static const struct command_registration stm32l4_command_handlers
[] = {
1181 .mode
= COMMAND_ANY
,
1182 .help
= "stm32l4x flash command group",
1184 .chain
= stm32l4_exec_command_handlers
,
1186 COMMAND_REGISTRATION_DONE
1189 const struct flash_driver stm32l4x_flash
= {
1191 .commands
= stm32l4_command_handlers
,
1192 .flash_bank_command
= stm32l4_flash_bank_command
,
1193 .erase
= stm32l4_erase
,
1194 .protect
= stm32l4_protect
,
1195 .write
= stm32l4_write
,
1196 .read
= default_flash_read
,
1197 .probe
= stm32l4_probe
,
1198 .auto_probe
= stm32l4_auto_probe
,
1199 .erase_check
= default_flash_blank_check
,
1200 .protect_check
= stm32l4_protect_check
,
1201 .info
= get_stm32l4_info
,
1202 .free_driver_priv
= default_flash_free_driver_priv
,
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