src/flash/nor/stm32l4x.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2015 by Uwe Bonnes                                      *
   5  *   bon@elektron.ikp.physik.tu-darmstadt.de                               *
   6  ***************************************************************************/
   7
   8 #ifndef OPENOCD_FLASH_NOR_STM32L4X
   9 #define OPENOCD_FLASH_NOR_STM32L4X
  10
  11 /* IMPORTANT: this file is included by stm32l4x driver and flashloader,
  12  * so please when changing this file, do not forget to check the flashloader */
  13
  14 /* FIXME: #include "helper/bits.h" cause build errors when compiling
  15  * the flashloader, for now just redefine the needed 'BIT 'macro */
  16
  17 #ifndef BIT
  18 #define BIT(nr)                 (1UL << (nr))
  19 #endif
  20
  21 /* FLASH_CR register bits */
  22 #define FLASH_PG                                BIT(0)
  23 #define FLASH_PER                               BIT(1)
  24 #define FLASH_MER1                              BIT(2)
  25 #define FLASH_PAGE_SHIFT                3
  26 #define FLASH_BKER                              BIT(11)
  27 #define FLASH_BKER_G0                   BIT(13)
  28 #define FLASH_MER2                              BIT(15)
  29 #define FLASH_STRT                              BIT(16)
  30 #define FLASH_OPTSTRT                   BIT(17)
  31 #define FLASH_EOPIE                             BIT(24)
  32 #define FLASH_ERRIE                             BIT(25)
  33 #define FLASH_OBL_LAUNCH                BIT(27)
  34 #define FLASH_OPTLOCK                   BIT(30)
  35 #define FLASH_LOCK                              BIT(31)
  36
  37 /* FLASH_SR register bits */
  38 #define FLASH_BSY                               BIT(16)
  39 #define FLASH_BSY2                              BIT(17)
  40
  41 /* Fast programming not used => related errors not used*/
  42 #define FLASH_PGSERR                    BIT(7) /* Programming sequence error */
  43 #define FLASH_SIZERR                    BIT(6) /* Size error */
  44 #define FLASH_PGAERR                    BIT(5) /* Programming alignment error */
  45 #define FLASH_WRPERR                    BIT(4) /* Write protection error */
  46 #define FLASH_PROGERR                   BIT(3) /* Programming error */
  47 #define FLASH_OPERR                             BIT(1) /* Operation error */
  48 #define FLASH_EOP                               BIT(0) /* End of operation */
  49 #define FLASH_ERROR                             (FLASH_PGSERR | FLASH_SIZERR | FLASH_PGAERR | \
  50                                                                 FLASH_WRPERR | FLASH_PROGERR | FLASH_OPERR)
  51
  52 /* register unlock keys */
  53 #define KEY1                                    0x45670123
  54 #define KEY2                                    0xCDEF89AB
  55
  56 /* option register unlock key */
  57 #define OPTKEY1                                 0x08192A3B
  58 #define OPTKEY2                                 0x4C5D6E7F
  59
  60 /* FLASH_OPTR register bits */
  61 #define FLASH_RDP_MASK                  0xFF
  62 #define FLASH_G0_DUAL_BANK              BIT(21)
  63 #define FLASH_G4_DUAL_BANK              BIT(22)
  64 #define FLASH_L4_DUAL_BANK              BIT(21)
  65 #define FLASH_L4R_DBANK                 BIT(22)
  66 #define FLASH_LRR_DB1M                  BIT(21)
  67 #define FLASH_L5_DBANK                  BIT(22)
  68 #define FLASH_L5_DB256                  BIT(21)
  69 #define FLASH_U5_DUALBANK               BIT(21)
  70 #define FLASH_TZEN                              BIT(31)
  71
  72 /* FLASH secure block based bank 1/2 register offsets */
  73 #define FLASH_SECBB1(X) (0x80 + 4 * (X - 1))
  74 #define FLASH_SECBB2(X) (0xA0 + 4 * (X - 1))
  75
  76 #define FLASH_SECBB_SECURE      0xFFFFFFFF
  77 #define FLASH_SECBB_NON_SECURE  0
  78
  79 /* IDCODE register possible addresses */
  80 #define DBGMCU_IDCODE_G0                0x40015800
  81 #define DBGMCU_IDCODE_L4_G4             0xE0042000
  82 #define DBGMCU_IDCODE_L5                0xE0044000
  83 #define UID64_DEVNUM                    0x1FFF7580
  84 #define UID64_IDS                               0x1FFF7584
  85 #define UID64_IDS_STM32WL               0x0080E115
  86
  87 /* Supported device IDs */
  88 #define DEVID_STM32L47_L48XX    0x415
  89 #define DEVID_STM32L43_L44XX    0x435
  90 #define DEVID_STM32G05_G06XX    0x456
  91 #define DEVID_STM32G07_G08XX    0x460
  92 #define DEVID_STM32L49_L4AXX    0x461
  93 #define DEVID_STM32L45_L46XX    0x462
  94 #define DEVID_STM32L41_L42XX    0x464
  95 #define DEVID_STM32G03_G04XX    0x466
  96 #define DEVID_STM32G0B_G0CXX    0x467
  97 #define DEVID_STM32G43_G44XX    0x468
  98 #define DEVID_STM32G47_G48XX    0x469
  99 #define DEVID_STM32L4R_L4SXX    0x470
 100 #define DEVID_STM32L4P_L4QXX    0x471
 101 #define DEVID_STM32L55_L56XX    0x472
 102 #define DEVID_STM32G49_G4AXX    0x479
 103 #define DEVID_STM32U57_U58XX    0x482
 104 #define DEVID_STM32WB1XX                0x494
 105 #define DEVID_STM32WB5XX                0x495
 106 #define DEVID_STM32WB3XX                0x496
 107 #define DEVID_STM32WLE_WL5XX    0x497
 108
 109 /* known Flash base addresses */
 110 #define STM32_FLASH_BANK_BASE   0x08000000
 111 #define STM32_FLASH_S_BANK_BASE 0x0C000000
 112
 113 /* offset between non-secure and secure flash registers */
 114 #define STM32L5_REGS_SEC_OFFSET 0x10000000
 115
 116 /* 100 bytes as loader stack should be large enough for the loader to operate */
 117 #define LDR_STACK_SIZE                  100
 118
 119 struct stm32l4_work_area {
 120         struct stm32l4_loader_params {
 121                 uint32_t flash_sr_addr;
 122                 uint32_t flash_cr_addr;
 123                 uint32_t flash_word_size;
 124                 uint32_t flash_sr_bsy_mask;
 125         } params;
 126         uint8_t stack[LDR_STACK_SIZE];
 127         struct flash_async_algorithm_circbuf {
 128                 /* note: stm32l4_work_area struct is shared between the loader
 129                  * and stm32l4x flash driver.
 130                  *
 131                  * '*wp' and '*rp' pointers' size is 4 bytes each since stm32l4x
 132                  * devices have 32-bit processors.
 133                  * however when used in openocd code, their size depends on the host
 134                  *   if the host is 32-bit, then the size is 4 bytes each.
 135                  *   if the host is 64-bit, then the size is 8 bytes each.
 136                  * to avoid this size difference, change their types depending on the
 137                  * usage (pointers for the loader, and 32-bit integers in openocd code).
 138                  */
 139 #ifdef OPENOCD_CONTRIB_LOADERS_FLASH_STM32_STM32L4X
 140                 uint8_t *wp;
 141                 uint8_t *rp;
 142 #else
 143                 uint32_t wp;
 144                 uint32_t rp;
 145 #endif /* OPENOCD_CONTRIB_LOADERS_FLASH_STM32_STM32L4X */
 146         } fifo;
 147 };
 148
 149 #endif