1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2011 by Clement Burin des Roziers *
9 * clement.burin-des-roziers@hikob.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/armv7m.h>
33 #include <target/cortex_m.h>
35 /* stm32lx flash register locations */
37 #define FLASH_ACR 0x00
38 #define FLASH_PECR 0x04
39 #define FLASH_PDKEYR 0x08
40 #define FLASH_PEKEYR 0x0C
41 #define FLASH_PRGKEYR 0x10
42 #define FLASH_OPTKEYR 0x14
44 #define FLASH_OBR 0x1C
45 #define FLASH_WRPR 0x20
48 #define FLASH_ACR__LATENCY (1<<0)
49 #define FLASH_ACR__PRFTEN (1<<1)
50 #define FLASH_ACR__ACC64 (1<<2)
51 #define FLASH_ACR__SLEEP_PD (1<<3)
52 #define FLASH_ACR__RUN_PD (1<<4)
55 #define FLASH_PECR__PELOCK (1<<0)
56 #define FLASH_PECR__PRGLOCK (1<<1)
57 #define FLASH_PECR__OPTLOCK (1<<2)
58 #define FLASH_PECR__PROG (1<<3)
59 #define FLASH_PECR__DATA (1<<4)
60 #define FLASH_PECR__FTDW (1<<8)
61 #define FLASH_PECR__ERASE (1<<9)
62 #define FLASH_PECR__FPRG (1<<10)
63 #define FLASH_PECR__EOPIE (1<<16)
64 #define FLASH_PECR__ERRIE (1<<17)
65 #define FLASH_PECR__OBL_LAUNCH (1<<18)
68 #define FLASH_SR__BSY (1<<0)
69 #define FLASH_SR__EOP (1<<1)
70 #define FLASH_SR__ENDHV (1<<2)
71 #define FLASH_SR__READY (1<<3)
72 #define FLASH_SR__WRPERR (1<<8)
73 #define FLASH_SR__PGAERR (1<<9)
74 #define FLASH_SR__SIZERR (1<<10)
75 #define FLASH_SR__OPTVERR (1<<11)
78 #define PEKEY1 0x89ABCDEF
79 #define PEKEY2 0x02030405
80 #define PRGKEY1 0x8C9DAEBF
81 #define PRGKEY2 0x13141516
82 #define OPTKEY1 0xFBEAD9C8
83 #define OPTKEY2 0x24252627
86 #define DBGMCU_IDCODE 0xE0042000
87 #define DBGMCU_IDCODE_L0 0x40015800
90 #define FLASH_SECTOR_SIZE 4096
91 #define FLASH_BANK0_ADDRESS 0x08000000
94 #define OPTION_BYTES_ADDRESS 0x1FF80000
96 #define OPTION_BYTE_0_PR1 0xFFFF0000
97 #define OPTION_BYTE_0_PR0 0xFF5500AA
99 static int stm32lx_unlock_program_memory(struct flash_bank
*bank
);
100 static int stm32lx_lock_program_memory(struct flash_bank
*bank
);
101 static int stm32lx_enable_write_half_page(struct flash_bank
*bank
);
102 static int stm32lx_erase_sector(struct flash_bank
*bank
, int sector
);
103 static int stm32lx_wait_until_bsy_clear(struct flash_bank
*bank
);
104 static int stm32lx_lock(struct flash_bank
*bank
);
105 static int stm32lx_unlock(struct flash_bank
*bank
);
106 static int stm32lx_mass_erase(struct flash_bank
*bank
);
107 static int stm32lx_wait_until_bsy_clear_timeout(struct flash_bank
*bank
, int timeout
);
108 static int stm32lx_update_part_info(struct flash_bank
*bank
, uint16_t flash_size_in_kb
);
115 struct stm32lx_part_info
{
117 const char *device_str
;
118 const struct stm32lx_rev
*revs
;
120 unsigned int page_size
;
121 unsigned int pages_per_sector
;
122 uint16_t max_flash_size_kb
;
123 uint16_t first_bank_size_kb
; /* used when has_dual_banks is true */
126 uint32_t flash_base
; /* Flash controller registers location */
127 uint32_t fsize_base
; /* Location of FSIZE register */
130 struct stm32lx_flash_bank
{
133 uint32_t user_bank_size
;
136 struct stm32lx_part_info part_info
;
139 static const struct stm32lx_rev stm32_416_revs
[] = {
140 { 0x1000, "A" }, { 0x1008, "Y" }, { 0x1038, "W" }, { 0x1078, "V" },
142 static const struct stm32lx_rev stm32_417_revs
[] = {
143 { 0x1000, "A" }, { 0x1008, "Z" }, { 0x1018, "Y" }, { 0x1038, "X" }
145 static const struct stm32lx_rev stm32_425_revs
[] = {
146 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2008, "Y" },
148 static const struct stm32lx_rev stm32_427_revs
[] = {
149 { 0x1000, "A" }, { 0x1018, "Y" }, { 0x1038, "X" }, { 0x10f8, "V" },
151 static const struct stm32lx_rev stm32_429_revs
[] = {
152 { 0x1000, "A" }, { 0x1018, "Z" },
154 static const struct stm32lx_rev stm32_436_revs
[] = {
155 { 0x1000, "A" }, { 0x1008, "Z" }, { 0x1018, "Y" },
157 static const struct stm32lx_rev stm32_437_revs
[] = {
160 static const struct stm32lx_rev stm32_447_revs
[] = {
161 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2008, "Z" },
163 static const struct stm32lx_rev stm32_457_revs
[] = {
164 { 0x1000, "A" }, { 0x1008, "Z" },
167 static const struct stm32lx_part_info stm32lx_parts
[] = {
170 .revs
= stm32_416_revs
,
171 .num_revs
= ARRAY_SIZE(stm32_416_revs
),
172 .device_str
= "STM32L1xx (Cat.1 - Low/Medium Density)",
174 .pages_per_sector
= 16,
175 .max_flash_size_kb
= 128,
176 .has_dual_banks
= false,
177 .flash_base
= 0x40023C00,
178 .fsize_base
= 0x1FF8004C,
182 .revs
= stm32_417_revs
,
183 .num_revs
= ARRAY_SIZE(stm32_417_revs
),
184 .device_str
= "STM32L0xx (Cat. 3)",
186 .pages_per_sector
= 32,
187 .max_flash_size_kb
= 64,
188 .has_dual_banks
= false,
189 .flash_base
= 0x40022000,
190 .fsize_base
= 0x1FF8007C,
194 .revs
= stm32_425_revs
,
195 .num_revs
= ARRAY_SIZE(stm32_425_revs
),
196 .device_str
= "STM32L0xx (Cat. 2)",
198 .pages_per_sector
= 32,
199 .max_flash_size_kb
= 32,
200 .has_dual_banks
= false,
201 .flash_base
= 0x40022000,
202 .fsize_base
= 0x1FF8007C,
206 .revs
= stm32_427_revs
,
207 .num_revs
= ARRAY_SIZE(stm32_427_revs
),
208 .device_str
= "STM32L1xx (Cat.3 - Medium+ Density)",
210 .pages_per_sector
= 16,
211 .max_flash_size_kb
= 256,
212 .has_dual_banks
= false,
213 .flash_base
= 0x40023C00,
214 .fsize_base
= 0x1FF800CC,
218 .revs
= stm32_429_revs
,
219 .num_revs
= ARRAY_SIZE(stm32_429_revs
),
220 .device_str
= "STM32L1xx (Cat.2)",
222 .pages_per_sector
= 16,
223 .max_flash_size_kb
= 128,
224 .has_dual_banks
= false,
225 .flash_base
= 0x40023C00,
226 .fsize_base
= 0x1FF8004C,
230 .revs
= stm32_436_revs
,
231 .num_revs
= ARRAY_SIZE(stm32_436_revs
),
232 .device_str
= "STM32L1xx (Cat.4/Cat.3 - Medium+/High Density)",
234 .pages_per_sector
= 16,
235 .max_flash_size_kb
= 384,
236 .first_bank_size_kb
= 192,
237 .has_dual_banks
= true,
238 .flash_base
= 0x40023C00,
239 .fsize_base
= 0x1FF800CC,
243 .revs
= stm32_437_revs
,
244 .num_revs
= ARRAY_SIZE(stm32_437_revs
),
245 .device_str
= "STM32L1xx (Cat.5/Cat.6)",
247 .pages_per_sector
= 16,
248 .max_flash_size_kb
= 512,
249 .first_bank_size_kb
= 0, /* determined in runtime */
250 .has_dual_banks
= true,
251 .flash_base
= 0x40023C00,
252 .fsize_base
= 0x1FF800CC,
256 .revs
= stm32_447_revs
,
257 .num_revs
= ARRAY_SIZE(stm32_447_revs
),
258 .device_str
= "STM32L0xx (Cat.5)",
260 .pages_per_sector
= 32,
261 .max_flash_size_kb
= 192,
262 .first_bank_size_kb
= 0, /* determined in runtime */
263 .has_dual_banks
= false, /* determined in runtime */
264 .flash_base
= 0x40022000,
265 .fsize_base
= 0x1FF8007C,
269 .revs
= stm32_457_revs
,
270 .num_revs
= ARRAY_SIZE(stm32_457_revs
),
271 .device_str
= "STM32L0xx (Cat.1)",
273 .pages_per_sector
= 32,
274 .max_flash_size_kb
= 16,
275 .has_dual_banks
= false,
276 .flash_base
= 0x40022000,
277 .fsize_base
= 0x1FF8007C,
281 /* flash bank stm32lx <base> <size> 0 0 <target#>
283 FLASH_BANK_COMMAND_HANDLER(stm32lx_flash_bank_command
)
285 struct stm32lx_flash_bank
*stm32lx_info
;
287 return ERROR_COMMAND_SYNTAX_ERROR
;
289 /* Create the bank structure */
290 stm32lx_info
= calloc(1, sizeof(*stm32lx_info
));
292 /* Check allocation */
293 if (stm32lx_info
== NULL
) {
294 LOG_ERROR("failed to allocate bank structure");
298 bank
->driver_priv
= stm32lx_info
;
300 stm32lx_info
->probed
= 0;
301 stm32lx_info
->user_bank_size
= bank
->size
;
303 /* the stm32l erased value is 0x00 */
304 bank
->default_padded_value
= bank
->erased_value
= 0x00;
309 COMMAND_HANDLER(stm32lx_handle_mass_erase_command
)
314 return ERROR_COMMAND_SYNTAX_ERROR
;
316 struct flash_bank
*bank
;
317 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
318 if (ERROR_OK
!= retval
)
321 retval
= stm32lx_mass_erase(bank
);
322 if (retval
== ERROR_OK
) {
323 /* set all sectors as erased */
324 for (i
= 0; i
< bank
->num_sectors
; i
++)
325 bank
->sectors
[i
].is_erased
= 1;
327 command_print(CMD_CTX
, "stm32lx mass erase complete");
329 command_print(CMD_CTX
, "stm32lx mass erase failed");
335 COMMAND_HANDLER(stm32lx_handle_lock_command
)
338 return ERROR_COMMAND_SYNTAX_ERROR
;
340 struct flash_bank
*bank
;
341 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
342 if (ERROR_OK
!= retval
)
345 retval
= stm32lx_lock(bank
);
347 if (retval
== ERROR_OK
)
348 command_print(CMD_CTX
, "STM32Lx locked, takes effect after power cycle.");
350 command_print(CMD_CTX
, "STM32Lx lock failed");
355 COMMAND_HANDLER(stm32lx_handle_unlock_command
)
358 return ERROR_COMMAND_SYNTAX_ERROR
;
360 struct flash_bank
*bank
;
361 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
362 if (ERROR_OK
!= retval
)
365 retval
= stm32lx_unlock(bank
);
367 if (retval
== ERROR_OK
)
368 command_print(CMD_CTX
, "STM32Lx unlocked, takes effect after power cycle.");
370 command_print(CMD_CTX
, "STM32Lx unlock failed");
375 static int stm32lx_protect_check(struct flash_bank
*bank
)
378 struct target
*target
= bank
->target
;
379 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
384 * Read the WRPR word, and check each bit (corresponding to each
387 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_WRPR
,
389 if (retval
!= ERROR_OK
)
392 for (int i
= 0; i
< bank
->num_sectors
; i
++) {
394 bank
->sectors
[i
].is_protected
= 1;
396 bank
->sectors
[i
].is_protected
= 0;
401 static int stm32lx_erase(struct flash_bank
*bank
, int first
, int last
)
406 * It could be possible to do a mass erase if all sectors must be
407 * erased, but it is not implemented yet.
410 if (bank
->target
->state
!= TARGET_HALTED
) {
411 LOG_ERROR("Target not halted");
412 return ERROR_TARGET_NOT_HALTED
;
416 * Loop over the selected sectors and erase them
418 for (int i
= first
; i
<= last
; i
++) {
419 retval
= stm32lx_erase_sector(bank
, i
);
420 if (retval
!= ERROR_OK
)
422 bank
->sectors
[i
].is_erased
= 1;
427 static int stm32lx_protect(struct flash_bank
*bank
, int set
, int first
,
430 LOG_WARNING("protection of the STM32L flash is not implemented");
434 static int stm32lx_write_half_pages(struct flash_bank
*bank
, const uint8_t *buffer
,
435 uint32_t offset
, uint32_t count
)
437 struct target
*target
= bank
->target
;
438 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
440 uint32_t hp_nb
= stm32lx_info
->part_info
.page_size
/ 2;
441 uint32_t buffer_size
= 16384;
442 struct working_area
*write_algorithm
;
443 struct working_area
*source
;
444 uint32_t address
= bank
->base
+ offset
;
446 struct reg_param reg_params
[3];
447 struct armv7m_algorithm armv7m_info
;
449 int retval
= ERROR_OK
;
451 static const uint8_t stm32lx_flash_write_code
[] = {
452 #include "../../../contrib/loaders/flash/stm32/stm32lx.inc"
455 /* Make sure we're performing a half-page aligned write. */
457 LOG_ERROR("The byte count must be %" PRIu32
"B-aligned but count is %" PRIi32
"B)", hp_nb
, count
);
461 /* flash write code */
462 if (target_alloc_working_area(target
, sizeof(stm32lx_flash_write_code
),
463 &write_algorithm
) != ERROR_OK
) {
464 LOG_DEBUG("no working area for block memory writes");
465 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
468 /* Write the flashing code */
469 retval
= target_write_buffer(target
,
470 write_algorithm
->address
,
471 sizeof(stm32lx_flash_write_code
),
472 stm32lx_flash_write_code
);
473 if (retval
!= ERROR_OK
) {
474 target_free_working_area(target
, write_algorithm
);
478 /* Allocate half pages memory */
479 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
) {
480 if (buffer_size
> 1024)
485 if (buffer_size
<= stm32lx_info
->part_info
.page_size
) {
486 /* we already allocated the writing code, but failed to get a
487 * buffer, free the algorithm */
488 target_free_working_area(target
, write_algorithm
);
490 LOG_WARNING("no large enough working area available, can't do block memory writes");
491 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
495 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
496 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
497 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
498 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
499 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
501 /* Enable half-page write */
502 retval
= stm32lx_enable_write_half_page(bank
);
503 if (retval
!= ERROR_OK
) {
504 target_free_working_area(target
, source
);
505 target_free_working_area(target
, write_algorithm
);
507 destroy_reg_param(®_params
[0]);
508 destroy_reg_param(®_params
[1]);
509 destroy_reg_param(®_params
[2]);
513 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
514 if (armv7m
== NULL
) {
516 /* something is very wrong if armv7m is NULL */
517 LOG_ERROR("unable to get armv7m target");
521 /* save any DEMCR flags and configure target to catch any Hard Faults */
522 uint32_t demcr_save
= armv7m
->demcr
;
523 armv7m
->demcr
= VC_HARDERR
;
525 /* Loop while there are bytes to write */
528 this_count
= (count
> buffer_size
) ? buffer_size
: count
;
530 /* Write the next half pages */
531 retval
= target_write_buffer(target
, source
->address
, this_count
, buffer
);
532 if (retval
!= ERROR_OK
)
535 /* 4: Store useful information in the registers */
536 /* the destination address of the copy (R0) */
537 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
538 /* The source address of the copy (R1) */
539 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
);
540 /* The length of the copy (R2) */
541 buf_set_u32(reg_params
[2].value
, 0, 32, this_count
/ 4);
543 /* 5: Execute the bunch of code */
544 retval
= target_run_algorithm(target
, 0, NULL
, sizeof(reg_params
)
545 / sizeof(*reg_params
), reg_params
,
546 write_algorithm
->address
, 0, 10000, &armv7m_info
);
547 if (retval
!= ERROR_OK
)
550 /* check for Hard Fault */
551 if (armv7m
->exception_number
== 3)
554 /* 6: Wait while busy */
555 retval
= stm32lx_wait_until_bsy_clear(bank
);
556 if (retval
!= ERROR_OK
)
559 buffer
+= this_count
;
560 address
+= this_count
;
564 /* restore previous flags */
565 armv7m
->demcr
= demcr_save
;
567 if (armv7m
->exception_number
== 3) {
569 /* the stm32l15x devices seem to have an issue when blank.
570 * if a ram loader is executed on a blank device it will
571 * Hard Fault, this issue does not happen for a already programmed device.
572 * A related issue is described in the stm32l151xx errata (Doc ID 17721 Rev 6 - 2.1.3).
573 * The workaround of handling the Hard Fault exception does work, but makes the
574 * loader more complicated, as a compromise we manually write the pages, programming time
575 * is reduced by 50% using this slower method.
578 LOG_WARNING("Couldn't use loader, falling back to page memory writes");
582 this_count
= (count
> hp_nb
) ? hp_nb
: count
;
584 /* Write the next half pages */
585 retval
= target_write_buffer(target
, address
, this_count
, buffer
);
586 if (retval
!= ERROR_OK
)
589 /* Wait while busy */
590 retval
= stm32lx_wait_until_bsy_clear(bank
);
591 if (retval
!= ERROR_OK
)
594 buffer
+= this_count
;
595 address
+= this_count
;
600 if (retval
== ERROR_OK
)
601 retval
= stm32lx_lock_program_memory(bank
);
603 target_free_working_area(target
, source
);
604 target_free_working_area(target
, write_algorithm
);
606 destroy_reg_param(®_params
[0]);
607 destroy_reg_param(®_params
[1]);
608 destroy_reg_param(®_params
[2]);
613 static int stm32lx_write(struct flash_bank
*bank
, const uint8_t *buffer
,
614 uint32_t offset
, uint32_t count
)
616 struct target
*target
= bank
->target
;
617 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
619 uint32_t hp_nb
= stm32lx_info
->part_info
.page_size
/ 2;
620 uint32_t halfpages_number
;
621 uint32_t bytes_remaining
= 0;
622 uint32_t address
= bank
->base
+ offset
;
623 uint32_t bytes_written
= 0;
626 if (bank
->target
->state
!= TARGET_HALTED
) {
627 LOG_ERROR("Target not halted");
628 return ERROR_TARGET_NOT_HALTED
;
632 LOG_ERROR("offset 0x%" PRIx32
" breaks required 4-byte alignment", offset
);
633 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
636 retval
= stm32lx_unlock_program_memory(bank
);
637 if (retval
!= ERROR_OK
)
640 /* first we need to write any unaligned head bytes upto
641 * the next 128 byte page */
644 bytes_remaining
= MIN(count
, hp_nb
- (offset
% hp_nb
));
646 while (bytes_remaining
> 0) {
647 uint8_t value
[4] = {0xff, 0xff, 0xff, 0xff};
649 /* copy remaining bytes into the write buffer */
650 uint32_t bytes_to_write
= MIN(4, bytes_remaining
);
651 memcpy(value
, buffer
+ bytes_written
, bytes_to_write
);
653 retval
= target_write_buffer(target
, address
, 4, value
);
654 if (retval
!= ERROR_OK
)
655 goto reset_pg_and_lock
;
657 bytes_written
+= bytes_to_write
;
658 bytes_remaining
-= bytes_to_write
;
661 retval
= stm32lx_wait_until_bsy_clear(bank
);
662 if (retval
!= ERROR_OK
)
663 goto reset_pg_and_lock
;
666 offset
+= bytes_written
;
667 count
-= bytes_written
;
669 /* this should always pass this check here */
670 assert((offset
% hp_nb
) == 0);
672 /* calculate half pages */
673 halfpages_number
= count
/ hp_nb
;
675 if (halfpages_number
) {
676 retval
= stm32lx_write_half_pages(bank
, buffer
+ bytes_written
, offset
, hp_nb
* halfpages_number
);
677 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
) {
678 /* attempt slow memory writes */
679 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
680 halfpages_number
= 0;
682 if (retval
!= ERROR_OK
)
687 /* write any remaining bytes */
688 uint32_t page_bytes_written
= hp_nb
* halfpages_number
;
689 bytes_written
+= page_bytes_written
;
690 address
+= page_bytes_written
;
691 bytes_remaining
= count
- page_bytes_written
;
693 retval
= stm32lx_unlock_program_memory(bank
);
694 if (retval
!= ERROR_OK
)
697 while (bytes_remaining
> 0) {
698 uint8_t value
[4] = {0xff, 0xff, 0xff, 0xff};
700 /* copy remaining bytes into the write buffer */
701 uint32_t bytes_to_write
= MIN(4, bytes_remaining
);
702 memcpy(value
, buffer
+ bytes_written
, bytes_to_write
);
704 retval
= target_write_buffer(target
, address
, 4, value
);
705 if (retval
!= ERROR_OK
)
706 goto reset_pg_and_lock
;
708 bytes_written
+= bytes_to_write
;
709 bytes_remaining
-= bytes_to_write
;
712 retval
= stm32lx_wait_until_bsy_clear(bank
);
713 if (retval
!= ERROR_OK
)
714 goto reset_pg_and_lock
;
718 retval2
= stm32lx_lock_program_memory(bank
);
719 if (retval
== ERROR_OK
)
725 static int stm32lx_read_id_code(struct target
*target
, uint32_t *id
)
727 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
729 if (armv7m
->arm
.is_armv6m
== true)
730 retval
= target_read_u32(target
, DBGMCU_IDCODE_L0
, id
);
732 /* read stm32 device id register */
733 retval
= target_read_u32(target
, DBGMCU_IDCODE
, id
);
737 static int stm32lx_probe(struct flash_bank
*bank
)
739 struct target
*target
= bank
->target
;
740 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
742 uint16_t flash_size_in_kb
;
744 uint32_t base_address
= FLASH_BANK0_ADDRESS
;
745 uint32_t second_bank_base
;
748 stm32lx_info
->probed
= 0;
750 int retval
= stm32lx_read_id_code(bank
->target
, &device_id
);
751 if (retval
!= ERROR_OK
)
754 stm32lx_info
->idcode
= device_id
;
756 LOG_DEBUG("device id = 0x%08" PRIx32
"", device_id
);
758 for (n
= 0; n
< ARRAY_SIZE(stm32lx_parts
); n
++) {
759 if ((device_id
& 0xfff) == stm32lx_parts
[n
].id
) {
760 stm32lx_info
->part_info
= stm32lx_parts
[n
];
765 if (n
== ARRAY_SIZE(stm32lx_parts
)) {
766 LOG_WARNING("Cannot identify target as a STM32L family.");
769 LOG_INFO("Device: %s", stm32lx_info
->part_info
.device_str
);
772 stm32lx_info
->flash_base
= stm32lx_info
->part_info
.flash_base
;
774 /* Get the flash size from target. */
775 retval
= target_read_u16(target
, stm32lx_info
->part_info
.fsize_base
,
778 /* 0x436 devices report their flash size as a 0 or 1 code indicating 384K
779 * or 256K, respectively. Please see RM0038 r8 or newer and refer to
781 if (retval
== ERROR_OK
&& (device_id
& 0xfff) == 0x436) {
782 if (flash_size_in_kb
== 0)
783 flash_size_in_kb
= 384;
784 else if (flash_size_in_kb
== 1)
785 flash_size_in_kb
= 256;
788 /* 0x429 devices only use the lowest 8 bits of the flash size register */
789 if (retval
== ERROR_OK
&& (device_id
& 0xfff) == 0x429) {
790 flash_size_in_kb
&= 0xff;
793 /* Failed reading flash size or flash size invalid (early silicon),
794 * default to max target family */
795 if (retval
!= ERROR_OK
|| flash_size_in_kb
== 0xffff || flash_size_in_kb
== 0) {
796 LOG_WARNING("STM32L flash size failed, probe inaccurate - assuming %dk flash",
797 stm32lx_info
->part_info
.max_flash_size_kb
);
798 flash_size_in_kb
= stm32lx_info
->part_info
.max_flash_size_kb
;
799 } else if (flash_size_in_kb
> stm32lx_info
->part_info
.max_flash_size_kb
) {
800 LOG_WARNING("STM32L probed flash size assumed incorrect since FLASH_SIZE=%dk > %dk, - assuming %dk flash",
801 flash_size_in_kb
, stm32lx_info
->part_info
.max_flash_size_kb
,
802 stm32lx_info
->part_info
.max_flash_size_kb
);
803 flash_size_in_kb
= stm32lx_info
->part_info
.max_flash_size_kb
;
806 /* Overwrite default dual-bank configuration */
807 retval
= stm32lx_update_part_info(bank
, flash_size_in_kb
);
808 if (retval
!= ERROR_OK
)
811 if (stm32lx_info
->part_info
.has_dual_banks
) {
812 /* Use the configured base address to determine if this is the first or second flash bank.
813 * Verify that the base address is reasonably correct and determine the flash bank size
815 second_bank_base
= base_address
+
816 stm32lx_info
->part_info
.first_bank_size_kb
* 1024;
817 if (bank
->base
== second_bank_base
|| !bank
->base
) {
818 /* This is the second bank */
819 base_address
= second_bank_base
;
820 flash_size_in_kb
= flash_size_in_kb
-
821 stm32lx_info
->part_info
.first_bank_size_kb
;
822 } else if (bank
->base
== base_address
) {
823 /* This is the first bank */
824 flash_size_in_kb
= stm32lx_info
->part_info
.first_bank_size_kb
;
826 LOG_WARNING("STM32L flash bank base address config is incorrect."
827 " 0x%" PRIx32
" but should rather be 0x%" PRIx32
" or 0x%" PRIx32
,
828 bank
->base
, base_address
, second_bank_base
);
831 LOG_INFO("STM32L flash has dual banks. Bank (%d) size is %dkb, base address is 0x%" PRIx32
,
832 bank
->bank_number
, flash_size_in_kb
, base_address
);
834 LOG_INFO("STM32L flash size is %dkb, base address is 0x%" PRIx32
, flash_size_in_kb
, base_address
);
837 /* if the user sets the size manually then ignore the probed value
838 * this allows us to work around devices that have a invalid flash size register value */
839 if (stm32lx_info
->user_bank_size
) {
840 flash_size_in_kb
= stm32lx_info
->user_bank_size
/ 1024;
841 LOG_INFO("ignoring flash probed value, using configured bank size: %dkbytes", flash_size_in_kb
);
844 /* calculate numbers of sectors (4kB per sector) */
845 int num_sectors
= (flash_size_in_kb
* 1024) / FLASH_SECTOR_SIZE
;
849 bank
->sectors
= NULL
;
852 bank
->size
= flash_size_in_kb
* 1024;
853 bank
->base
= base_address
;
854 bank
->num_sectors
= num_sectors
;
855 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_sectors
);
856 if (bank
->sectors
== NULL
) {
857 LOG_ERROR("failed to allocate bank sectors");
861 for (i
= 0; i
< num_sectors
; i
++) {
862 bank
->sectors
[i
].offset
= i
* FLASH_SECTOR_SIZE
;
863 bank
->sectors
[i
].size
= FLASH_SECTOR_SIZE
;
864 bank
->sectors
[i
].is_erased
= -1;
865 bank
->sectors
[i
].is_protected
= 1;
868 stm32lx_info
->probed
= 1;
873 static int stm32lx_auto_probe(struct flash_bank
*bank
)
875 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
877 if (stm32lx_info
->probed
)
880 return stm32lx_probe(bank
);
883 /* This method must return a string displaying information about the bank */
884 static int stm32lx_get_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
886 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
887 const struct stm32lx_part_info
*info
= &stm32lx_info
->part_info
;
888 uint16_t rev_id
= stm32lx_info
->idcode
>> 16;
889 const char *rev_str
= NULL
;
891 if (!stm32lx_info
->probed
) {
892 int retval
= stm32lx_probe(bank
);
893 if (retval
!= ERROR_OK
) {
894 snprintf(buf
, buf_size
,
895 "Unable to find bank information.");
900 for (unsigned int i
= 0; i
< info
->num_revs
; i
++)
901 if (rev_id
== info
->revs
[i
].rev
)
902 rev_str
= info
->revs
[i
].str
;
904 if (rev_str
!= NULL
) {
905 snprintf(buf
, buf_size
,
907 info
->device_str
, rev_str
);
909 snprintf(buf
, buf_size
,
910 "%s - Rev: unknown (0x%04x)",
911 info
->device_str
, rev_id
);
917 static const struct command_registration stm32lx_exec_command_handlers
[] = {
919 .name
= "mass_erase",
920 .handler
= stm32lx_handle_mass_erase_command
,
921 .mode
= COMMAND_EXEC
,
923 .help
= "Erase entire flash device. including available EEPROM",
927 .handler
= stm32lx_handle_lock_command
,
928 .mode
= COMMAND_EXEC
,
930 .help
= "Increase the readout protection to Level 1.",
934 .handler
= stm32lx_handle_unlock_command
,
935 .mode
= COMMAND_EXEC
,
937 .help
= "Lower the readout protection from Level 1 to 0.",
939 COMMAND_REGISTRATION_DONE
942 static const struct command_registration stm32lx_command_handlers
[] = {
946 .help
= "stm32lx flash command group",
948 .chain
= stm32lx_exec_command_handlers
,
950 COMMAND_REGISTRATION_DONE
953 struct flash_driver stm32lx_flash
= {
955 .commands
= stm32lx_command_handlers
,
956 .flash_bank_command
= stm32lx_flash_bank_command
,
957 .erase
= stm32lx_erase
,
958 .protect
= stm32lx_protect
,
959 .write
= stm32lx_write
,
960 .read
= default_flash_read
,
961 .probe
= stm32lx_probe
,
962 .auto_probe
= stm32lx_auto_probe
,
963 .erase_check
= default_flash_blank_check
,
964 .protect_check
= stm32lx_protect_check
,
965 .info
= stm32lx_get_info
,
966 .free_driver_priv
= default_flash_free_driver_priv
,
969 /* Static methods implementation */
970 static int stm32lx_unlock_program_memory(struct flash_bank
*bank
)
972 struct target
*target
= bank
->target
;
973 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
978 * Unlocking the program memory is done by unlocking the PECR,
979 * then by writing the 2 PRGKEY to the PRGKEYR register
982 /* check flash is not already unlocked */
983 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
985 if (retval
!= ERROR_OK
)
988 if ((reg32
& FLASH_PECR__PRGLOCK
) == 0)
991 /* To unlock the PECR write the 2 PEKEY to the PEKEYR register */
992 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PEKEYR
,
994 if (retval
!= ERROR_OK
)
997 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PEKEYR
,
999 if (retval
!= ERROR_OK
)
1002 /* Make sure it worked */
1003 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1005 if (retval
!= ERROR_OK
)
1008 if (reg32
& FLASH_PECR__PELOCK
) {
1009 LOG_ERROR("PELOCK is not cleared :(");
1010 return ERROR_FLASH_OPERATION_FAILED
;
1013 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PRGKEYR
,
1015 if (retval
!= ERROR_OK
)
1017 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PRGKEYR
,
1019 if (retval
!= ERROR_OK
)
1022 /* Make sure it worked */
1023 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1025 if (retval
!= ERROR_OK
)
1028 if (reg32
& FLASH_PECR__PRGLOCK
) {
1029 LOG_ERROR("PRGLOCK is not cleared :(");
1030 return ERROR_FLASH_OPERATION_FAILED
;
1036 static int stm32lx_enable_write_half_page(struct flash_bank
*bank
)
1038 struct target
*target
= bank
->target
;
1039 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
1044 * Unlock the program memory, then set the FPRG bit in the PECR register.
1046 retval
= stm32lx_unlock_program_memory(bank
);
1047 if (retval
!= ERROR_OK
)
1050 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1052 if (retval
!= ERROR_OK
)
1055 reg32
|= FLASH_PECR__FPRG
;
1056 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1058 if (retval
!= ERROR_OK
)
1061 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1063 if (retval
!= ERROR_OK
)
1066 reg32
|= FLASH_PECR__PROG
;
1067 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1073 static int stm32lx_lock_program_memory(struct flash_bank
*bank
)
1075 struct target
*target
= bank
->target
;
1076 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
1080 /* To lock the program memory, simply set the lock bit and lock PECR */
1082 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1084 if (retval
!= ERROR_OK
)
1087 reg32
|= FLASH_PECR__PRGLOCK
;
1088 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1090 if (retval
!= ERROR_OK
)
1093 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1095 if (retval
!= ERROR_OK
)
1098 reg32
|= FLASH_PECR__PELOCK
;
1099 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1101 if (retval
!= ERROR_OK
)
1107 static int stm32lx_erase_sector(struct flash_bank
*bank
, int sector
)
1109 struct target
*target
= bank
->target
;
1110 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
1115 * To erase a sector (i.e. stm32lx_info->part_info.pages_per_sector pages),
1116 * first unlock the memory, loop over the pages of this sector
1117 * and write 0x0 to its first word.
1120 retval
= stm32lx_unlock_program_memory(bank
);
1121 if (retval
!= ERROR_OK
)
1124 for (int page
= 0; page
< (int)stm32lx_info
->part_info
.pages_per_sector
;
1126 reg32
= FLASH_PECR__PROG
| FLASH_PECR__ERASE
;
1127 retval
= target_write_u32(target
,
1128 stm32lx_info
->flash_base
+ FLASH_PECR
, reg32
);
1129 if (retval
!= ERROR_OK
)
1132 retval
= stm32lx_wait_until_bsy_clear(bank
);
1133 if (retval
!= ERROR_OK
)
1136 uint32_t addr
= bank
->base
+ bank
->sectors
[sector
].offset
+ (page
1137 * stm32lx_info
->part_info
.page_size
);
1138 retval
= target_write_u32(target
, addr
, 0x0);
1139 if (retval
!= ERROR_OK
)
1142 retval
= stm32lx_wait_until_bsy_clear(bank
);
1143 if (retval
!= ERROR_OK
)
1147 retval
= stm32lx_lock_program_memory(bank
);
1148 if (retval
!= ERROR_OK
)
1154 static inline int stm32lx_get_flash_status(struct flash_bank
*bank
, uint32_t *status
)
1156 struct target
*target
= bank
->target
;
1157 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
1159 return target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_SR
, status
);
1162 static int stm32lx_wait_until_bsy_clear(struct flash_bank
*bank
)
1164 return stm32lx_wait_until_bsy_clear_timeout(bank
, 100);
1167 static int stm32lx_unlock_options_bytes(struct flash_bank
*bank
)
1169 struct target
*target
= bank
->target
;
1170 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
1175 * Unlocking the options bytes is done by unlocking the PECR,
1176 * then by writing the 2 FLASH_PEKEYR to the FLASH_OPTKEYR register
1179 /* check flash is not already unlocked */
1180 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
, ®32
);
1181 if (retval
!= ERROR_OK
)
1184 if ((reg32
& FLASH_PECR__OPTLOCK
) == 0)
1187 if ((reg32
& FLASH_PECR__PELOCK
) != 0) {
1189 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PEKEYR
, PEKEY1
);
1190 if (retval
!= ERROR_OK
)
1193 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PEKEYR
, PEKEY2
);
1194 if (retval
!= ERROR_OK
)
1198 /* To unlock the PECR write the 2 OPTKEY to the FLASH_OPTKEYR register */
1199 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_OPTKEYR
, OPTKEY1
);
1200 if (retval
!= ERROR_OK
)
1203 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_OPTKEYR
, OPTKEY2
);
1204 if (retval
!= ERROR_OK
)
1210 static int stm32lx_wait_until_bsy_clear_timeout(struct flash_bank
*bank
, int timeout
)
1212 struct target
*target
= bank
->target
;
1213 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
1215 int retval
= ERROR_OK
;
1217 /* wait for busy to clear */
1219 retval
= stm32lx_get_flash_status(bank
, &status
);
1220 if (retval
!= ERROR_OK
)
1223 LOG_DEBUG("status: 0x%" PRIx32
"", status
);
1224 if ((status
& FLASH_SR__BSY
) == 0)
1227 if (timeout
-- <= 0) {
1228 LOG_ERROR("timed out waiting for flash");
1234 if (status
& FLASH_SR__WRPERR
) {
1235 LOG_ERROR("access denied / write protected");
1236 retval
= ERROR_FAIL
;
1239 if (status
& FLASH_SR__PGAERR
) {
1240 LOG_ERROR("invalid program address");
1241 retval
= ERROR_FAIL
;
1244 /* Clear but report errors */
1245 if (status
& FLASH_SR__OPTVERR
) {
1246 /* If this operation fails, we ignore it and report the original retval */
1247 target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_SR
, status
& FLASH_SR__OPTVERR
);
1253 static int stm32lx_obl_launch(struct flash_bank
*bank
)
1255 struct target
*target
= bank
->target
;
1256 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
1259 /* This will fail as the target gets immediately rebooted */
1260 target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1261 FLASH_PECR__OBL_LAUNCH
);
1265 target_halt(target
);
1266 retval
= target_poll(target
);
1267 } while (--tries
> 0 &&
1268 (retval
!= ERROR_OK
|| target
->state
!= TARGET_HALTED
));
1270 return tries
? ERROR_OK
: ERROR_FAIL
;
1273 static int stm32lx_lock(struct flash_bank
*bank
)
1276 struct target
*target
= bank
->target
;
1278 if (target
->state
!= TARGET_HALTED
) {
1279 LOG_ERROR("Target not halted");
1280 return ERROR_TARGET_NOT_HALTED
;
1283 retval
= stm32lx_unlock_options_bytes(bank
);
1284 if (retval
!= ERROR_OK
)
1287 /* set the RDP protection level to 1 */
1288 retval
= target_write_u32(target
, OPTION_BYTES_ADDRESS
, OPTION_BYTE_0_PR1
);
1289 if (retval
!= ERROR_OK
)
1295 static int stm32lx_unlock(struct flash_bank
*bank
)
1298 struct target
*target
= bank
->target
;
1300 if (target
->state
!= TARGET_HALTED
) {
1301 LOG_ERROR("Target not halted");
1302 return ERROR_TARGET_NOT_HALTED
;
1305 retval
= stm32lx_unlock_options_bytes(bank
);
1306 if (retval
!= ERROR_OK
)
1309 /* set the RDP protection level to 0 */
1310 retval
= target_write_u32(target
, OPTION_BYTES_ADDRESS
, OPTION_BYTE_0_PR0
);
1311 if (retval
!= ERROR_OK
)
1314 retval
= stm32lx_wait_until_bsy_clear_timeout(bank
, 30000);
1315 if (retval
!= ERROR_OK
)
1321 static int stm32lx_mass_erase(struct flash_bank
*bank
)
1324 struct target
*target
= bank
->target
;
1325 struct stm32lx_flash_bank
*stm32lx_info
= NULL
;
1328 if (target
->state
!= TARGET_HALTED
) {
1329 LOG_ERROR("Target not halted");
1330 return ERROR_TARGET_NOT_HALTED
;
1333 stm32lx_info
= bank
->driver_priv
;
1335 retval
= stm32lx_lock(bank
);
1336 if (retval
!= ERROR_OK
)
1339 retval
= stm32lx_obl_launch(bank
);
1340 if (retval
!= ERROR_OK
)
1343 retval
= stm32lx_unlock(bank
);
1344 if (retval
!= ERROR_OK
)
1347 retval
= stm32lx_obl_launch(bank
);
1348 if (retval
!= ERROR_OK
)
1351 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
, ®32
);
1352 if (retval
!= ERROR_OK
)
1355 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
, reg32
| FLASH_PECR__OPTLOCK
);
1356 if (retval
!= ERROR_OK
)
1362 static int stm32lx_update_part_info(struct flash_bank
*bank
, uint16_t flash_size_in_kb
)
1364 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
1366 switch (stm32lx_info
->part_info
.id
) {
1367 case 0x447: /* STM32L0xx (Cat.5) devices */
1368 if (flash_size_in_kb
== 192 || flash_size_in_kb
== 128) {
1369 stm32lx_info
->part_info
.first_bank_size_kb
= flash_size_in_kb
/ 2;
1370 stm32lx_info
->part_info
.has_dual_banks
= true;
1373 case 0x437: /* STM32L1xx (Cat.5/Cat.6) */
1374 stm32lx_info
->part_info
.first_bank_size_kb
= flash_size_in_kb
/ 2;
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