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flash: add new stm32l HD variant
[openocd.git] / src / flash / nor / stm32lx.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Clement Burin des Roziers *
9 * clement.burin-des-roziers@hikob.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26
27 #ifdef HAVE_CONFIG_H
28 #include "config.h"
29 #endif
30
31 #include "imp.h"
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34 #include <target/armv7m.h>
35
36 /* stm32lx flash register locations */
37
38 #define FLASH_BASE 0x40023C00
39 #define FLASH_ACR 0x40023C00
40 #define FLASH_PECR 0x40023C04
41 #define FLASH_PDKEYR 0x40023C08
42 #define FLASH_PEKEYR 0x40023C0C
43 #define FLASH_PRGKEYR 0x40023C10
44 #define FLASH_OPTKEYR 0x40023C14
45 #define FLASH_SR 0x40023C18
46 #define FLASH_OBR 0x40023C1C
47 #define FLASH_WRPR 0x40023C20
48
49 /* FLASH_ACR bites */
50 #define FLASH_ACR__LATENCY (1<<0)
51 #define FLASH_ACR__PRFTEN (1<<1)
52 #define FLASH_ACR__ACC64 (1<<2)
53 #define FLASH_ACR__SLEEP_PD (1<<3)
54 #define FLASH_ACR__RUN_PD (1<<4)
55
56 /* FLASH_PECR bits */
57 #define FLASH_PECR__PELOCK (1<<0)
58 #define FLASH_PECR__PRGLOCK (1<<1)
59 #define FLASH_PECR__OPTLOCK (1<<2)
60 #define FLASH_PECR__PROG (1<<3)
61 #define FLASH_PECR__DATA (1<<4)
62 #define FLASH_PECR__FTDW (1<<8)
63 #define FLASH_PECR__ERASE (1<<9)
64 #define FLASH_PECR__FPRG (1<<10)
65 #define FLASH_PECR__EOPIE (1<<16)
66 #define FLASH_PECR__ERRIE (1<<17)
67 #define FLASH_PECR__OBL_LAUNCH (1<<18)
68
69 /* FLASH_SR bits */
70 #define FLASH_SR__BSY (1<<0)
71 #define FLASH_SR__EOP (1<<1)
72 #define FLASH_SR__ENDHV (1<<2)
73 #define FLASH_SR__READY (1<<3)
74 #define FLASH_SR__WRPERR (1<<8)
75 #define FLASH_SR__PGAERR (1<<9)
76 #define FLASH_SR__SIZERR (1<<10)
77 #define FLASH_SR__OPTVERR (1<<11)
78
79 /* Unlock keys */
80 #define PEKEY1 0x89ABCDEF
81 #define PEKEY2 0x02030405
82 #define PRGKEY1 0x8C9DAEBF
83 #define PRGKEY2 0x13141516
84 #define OPTKEY1 0xFBEAD9C8
85 #define OPTKEY2 0x24252627
86
87 /* other registers */
88 #define DBGMCU_IDCODE 0xE0042000
89 #define F_SIZE 0x1FF8004C
90
91 /* Constants */
92 #define FLASH_PAGE_SIZE 256
93 #define FLASH_SECTOR_SIZE 4096
94 #define FLASH_PAGES_PER_SECTOR 16
95 #define FLASH_BANK0_ADDRESS 0x08000000
96
97 /* stm32lx option byte register location */
98 #define OB_RDP 0x1FF80000
99 #define OB_USER 0x1FF80004
100 #define OB_WRP0_1 0x1FF80008
101 #define OB_WRP2_3 0x1FF8000C
102
103 /* OB_RDP values */
104 #define OB_RDP__LEVEL0 0xFF5500AA
105 #define OB_RDP__LEVEL1 0xFFFF0000
106
107 /* stm32lx RCC register locations */
108 #define RCC_CR 0x40023800
109 #define RCC_ICSCR 0x40023804
110 #define RCC_CFGR 0x40023808
111
112 /* RCC_ICSCR bits */
113 #define RCC_ICSCR__MSIRANGE_MASK (7<<13)
114
115 static int stm32lx_unlock_program_memory(struct flash_bank *bank);
116 static int stm32lx_lock_program_memory(struct flash_bank *bank);
117 static int stm32lx_enable_write_half_page(struct flash_bank *bank);
118 static int stm32lx_erase_sector(struct flash_bank *bank, int sector);
119 static int stm32lx_wait_until_bsy_clear(struct flash_bank *bank);
120
121 struct stm32lx_flash_bank {
122 int probed;
123 };
124
125 /* flash bank stm32lx <base> <size> 0 0 <target#>
126 */
127 FLASH_BANK_COMMAND_HANDLER(stm32lx_flash_bank_command)
128 {
129 struct stm32lx_flash_bank *stm32lx_info;
130 if (CMD_ARGC < 6)
131 return ERROR_COMMAND_SYNTAX_ERROR;
132
133 /* Create the bank structure */
134 stm32lx_info = malloc(sizeof(struct stm32lx_flash_bank));
135
136 /* Check allocation */
137 if (stm32lx_info == NULL) {
138 LOG_ERROR("failed to allocate bank structure");
139 return ERROR_FAIL;
140 }
141
142 bank->driver_priv = stm32lx_info;
143
144 stm32lx_info->probed = 0;
145
146 return ERROR_OK;
147 }
148
149 static int stm32lx_protect_check(struct flash_bank *bank)
150 {
151 int retval;
152 struct target *target = bank->target;
153
154 uint32_t wrpr;
155
156 if (target->state != TARGET_HALTED) {
157 LOG_ERROR("Target not halted");
158 return ERROR_TARGET_NOT_HALTED;
159 }
160
161 /*
162 * Read the WRPR word, and check each bit (corresponding to each
163 * flash sector
164 */
165 retval = target_read_u32(target, FLASH_WRPR, &wrpr);
166 if (retval != ERROR_OK)
167 return retval;
168
169 for (int i = 0; i < 32; i++) {
170 if (wrpr & (1 << i))
171 bank->sectors[i].is_protected = 1;
172 else
173 bank->sectors[i].is_protected = 0;
174 }
175 return ERROR_OK;
176 }
177
178 static int stm32lx_erase(struct flash_bank *bank, int first, int last)
179 {
180 int retval;
181
182 /*
183 * It could be possible to do a mass erase if all sectors must be
184 * erased, but it is not implemented yet.
185 */
186
187 if (bank->target->state != TARGET_HALTED) {
188 LOG_ERROR("Target not halted");
189 return ERROR_TARGET_NOT_HALTED;
190 }
191
192 /*
193 * Loop over the selected sectors and erase them
194 */
195 for (int i = first; i <= last; i++) {
196 retval = stm32lx_erase_sector(bank, i);
197 if (retval != ERROR_OK)
198 return retval;
199 bank->sectors[i].is_erased = 1;
200 }
201 return ERROR_OK;
202 }
203
204 static int stm32lx_protect(struct flash_bank *bank, int set, int first,
205 int last)
206 {
207 LOG_WARNING("protection of the STM32L flash is not implemented");
208 return ERROR_OK;
209 }
210
211 static int stm32lx_write_half_pages(struct flash_bank *bank, uint8_t *buffer,
212 uint32_t offset, uint32_t count)
213 {
214 struct target *target = bank->target;
215 uint32_t buffer_size = 4096 * 4;
216 struct working_area *write_algorithm;
217 struct working_area *source;
218 uint32_t address = bank->base + offset;
219
220 struct reg_param reg_params[5];
221 struct armv7m_algorithm armv7m_info;
222
223 int retval = ERROR_OK;
224 uint32_t reg32;
225
226 /* see contib/loaders/flash/stm32lx.s for src */
227
228 static const uint16_t stm32lx_flash_write_code_16[] = {
229 /* 00000000 <write_word-0x4>: */
230 0x2300, /* 0: 2300 movs r3, #0 */
231 0xe004, /* 2: e004 b.n e <test_done> */
232
233 /* 00000004 <write_word>: */
234 0xf851, 0xcb04, /* 4: f851 cb04 ldr.w ip, [r1], #4 */
235 0xf840, 0xcb04, /* 8: f840 cb04 str.w ip, [r0], #4 */
236 0x3301, /* c: 3301 adds r3, #1 */
237
238 /* 0000000e <test_done>: */
239 0x4293, /* e: 4293 cmp r3, r2 */
240 0xd3f8, /* 10: d3f8 bcc.n 4 <write_word> */
241 0xbe00, /* 12: be00 bkpt 0x0000 */
242
243 };
244
245 /* Flip endian */
246 uint8_t stm32lx_flash_write_code[sizeof(stm32lx_flash_write_code_16)];
247 for (unsigned int i = 0; i < sizeof(stm32lx_flash_write_code_16) / 2; i++) {
248 stm32lx_flash_write_code[i * 2 + 0] = stm32lx_flash_write_code_16[i]
249 & 0xff;
250 stm32lx_flash_write_code[i * 2 + 1] = (stm32lx_flash_write_code_16[i]
251 >> 8) & 0xff;
252 }
253 /* Check if there is an even number of half pages (128bytes) */
254 if (count % 128) {
255 LOG_ERROR("there should be an even number "
256 "of half pages = 128 bytes (count = %" PRIi32 " bytes)", count);
257 return ERROR_FAIL;
258 }
259
260 /* Allocate working area */
261 reg32 = sizeof(stm32lx_flash_write_code);
262 /* Add bytes to make 4byte aligned */
263 reg32 += (4 - (reg32 % 4)) % 4;
264 retval = target_alloc_working_area(target, reg32,
265 &write_algorithm);
266 if (retval != ERROR_OK)
267 return retval;
268
269 /* Write the flashing code */
270 retval = target_write_buffer(target,
271 write_algorithm->address,
272 sizeof(stm32lx_flash_write_code),
273 (uint8_t *)stm32lx_flash_write_code);
274 if (retval != ERROR_OK) {
275 target_free_working_area(target, write_algorithm);
276 return retval;
277 }
278
279 /* Allocate half pages memory */
280 while (target_alloc_working_area_try(target, buffer_size, &source)
281 != ERROR_OK) {
282 if (buffer_size > 1024)
283 buffer_size -= 1024;
284 else
285 buffer_size /= 2;
286
287 if (buffer_size <= 256) {
288 /* we already allocated the writing code, but failed to get a
289 * buffer, free the algorithm */
290 target_free_working_area(target, write_algorithm);
291
292 LOG_WARNING("no large enough working area available, can't do block memory writes");
293 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
294 }
295 }
296 LOG_DEBUG("allocated working area for data (%" PRIx32 " bytes)", buffer_size);
297
298 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
299 armv7m_info.core_mode = ARMV7M_MODE_ANY;
300 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
301 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
302 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
303 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN_OUT);
304 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
305
306 /* Enable half-page write */
307 retval = stm32lx_enable_write_half_page(bank);
308 if (retval != ERROR_OK) {
309 target_free_working_area(target, source);
310 target_free_working_area(target, write_algorithm);
311
312 destroy_reg_param(&reg_params[0]);
313 destroy_reg_param(&reg_params[1]);
314 destroy_reg_param(&reg_params[2]);
315 destroy_reg_param(&reg_params[3]);
316 return retval;
317 }
318
319 /* Loop while there are bytes to write */
320 while (count > 0) {
321 uint32_t this_count;
322 this_count = (count > buffer_size) ? buffer_size : count;
323
324 /* Write the next half pages */
325 retval = target_write_buffer(target, source->address, this_count,
326 buffer);
327 if (retval != ERROR_OK)
328 break;
329
330 /* 4: Store useful information in the registers */
331 /* the destination address of the copy (R0) */
332 buf_set_u32(reg_params[0].value, 0, 32, address);
333 /* The source address of the copy (R1) */
334 buf_set_u32(reg_params[1].value, 0, 32, source->address);
335 /* The length of the copy (R2) */
336 buf_set_u32(reg_params[2].value, 0, 32, this_count / 4);
337
338 /* 5: Execute the bunch of code */
339 retval = target_run_algorithm(target, 0, NULL, sizeof(reg_params)
340 / sizeof(*reg_params), reg_params,
341 write_algorithm->address, 0, 20000, &armv7m_info);
342 if (retval != ERROR_OK)
343 break;
344
345 /* 6: Wait while busy */
346 retval = stm32lx_wait_until_bsy_clear(bank);
347 if (retval != ERROR_OK)
348 break;
349
350 buffer += this_count;
351 address += this_count;
352 count -= this_count;
353 }
354
355 if (retval == ERROR_OK)
356 retval = stm32lx_lock_program_memory(bank);
357
358 target_free_working_area(target, source);
359 target_free_working_area(target, write_algorithm);
360
361 destroy_reg_param(&reg_params[0]);
362 destroy_reg_param(&reg_params[1]);
363 destroy_reg_param(&reg_params[2]);
364 destroy_reg_param(&reg_params[3]);
365
366 return retval;
367 }
368 static int stm32lx_write(struct flash_bank *bank, uint8_t *buffer,
369 uint32_t offset, uint32_t count)
370 {
371 struct target *target = bank->target;
372
373 uint32_t halfpages_number;
374 uint32_t words_remaining;
375 uint32_t bytes_remaining;
376 uint32_t address = bank->base + offset;
377 uint32_t bytes_written = 0;
378 int retval;
379
380 if (bank->target->state != TARGET_HALTED) {
381 LOG_ERROR("Target not halted");
382 return ERROR_TARGET_NOT_HALTED;
383 }
384
385 if (offset & 0x1) {
386 LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
387 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
388 }
389
390 /* Check if there are some full half pages */
391 if (((offset % 128) == 0) && (count >= 128)) {
392 halfpages_number = count / 128;
393 words_remaining = (count - 128 * halfpages_number) / 4;
394 bytes_remaining = (count & 0x3);
395 } else {
396 halfpages_number = 0;
397 words_remaining = (count / 4);
398 bytes_remaining = (count & 0x3);
399 }
400
401 if (halfpages_number) {
402 retval = stm32lx_write_half_pages(bank, buffer, offset, 128
403 * halfpages_number);
404 if (retval != ERROR_OK)
405 return ERROR_FAIL;
406 }
407
408 bytes_written = 128 * halfpages_number;
409 address += bytes_written;
410
411 retval = stm32lx_unlock_program_memory(bank);
412 if (retval != ERROR_OK)
413 return retval;
414
415 while (words_remaining > 0) {
416 uint32_t value;
417 uint8_t *p = buffer + bytes_written;
418
419 /* Prepare the word, Little endian conversion */
420 value = p[0] + (p[1] << 8) + (p[2] << 16) + (p[3] << 24);
421
422 retval = target_write_u32(target, address, value);
423 if (retval != ERROR_OK)
424 return retval;
425
426 bytes_written += 4;
427 words_remaining--;
428 address += 4;
429
430 retval = stm32lx_wait_until_bsy_clear(bank);
431 if (retval != ERROR_OK)
432 return retval;
433 }
434
435 if (bytes_remaining) {
436 uint8_t last_word[4] = {0xff, 0xff, 0xff, 0xff};
437
438 /* copy the last remaining bytes into the write buffer */
439 memcpy(last_word, buffer+bytes_written, bytes_remaining);
440
441 retval = target_write_buffer(target, address, 4, last_word);
442 if (retval != ERROR_OK)
443 return retval;
444
445 retval = stm32lx_wait_until_bsy_clear(bank);
446 if (retval != ERROR_OK)
447 return retval;
448 }
449
450 retval = stm32lx_lock_program_memory(bank);
451 if (retval != ERROR_OK)
452 return retval;
453
454 return ERROR_OK;
455 }
456
457 static int stm32lx_probe(struct flash_bank *bank)
458 {
459 struct target *target = bank->target;
460 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
461 int i;
462 uint16_t flash_size_in_kb;
463 uint16_t max_flash_size_in_kb;
464 uint32_t device_id;
465
466 stm32lx_info->probed = 0;
467
468 /* read stm32 device id register */
469 int retval = target_read_u32(target, DBGMCU_IDCODE, &device_id);
470 if (retval != ERROR_OK)
471 return retval;
472
473 LOG_DEBUG("device id = 0x%08" PRIx32 "", device_id);
474
475 /* set max flash size depending on family */
476 switch (device_id & 0xfff) {
477 case 0x416:
478 max_flash_size_in_kb = 128;
479 break;
480 case 0x436:
481 max_flash_size_in_kb = 384;
482 break;
483 default:
484 LOG_WARNING("Cannot identify target as a STM32L family.");
485 return ERROR_FAIL;
486 }
487
488 /* get flash size from target. */
489 retval = target_read_u16(target, F_SIZE, &flash_size_in_kb);
490
491 /* failed reading flash size or flash size invalid (early silicon),
492 * default to max target family */
493 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
494 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
495 max_flash_size_in_kb);
496 flash_size_in_kb = max_flash_size_in_kb;
497 }
498
499 /* STM32L - we have 32 sectors, 16 pages per sector -> 512 pages
500 * 16 pages for a protection area */
501
502 /* calculate numbers of sectors (4kB per sector) */
503 int num_sectors = (flash_size_in_kb * 1024) / FLASH_SECTOR_SIZE;
504 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
505
506 if (bank->sectors) {
507 free(bank->sectors);
508 bank->sectors = NULL;
509 }
510
511 bank->base = FLASH_BANK0_ADDRESS;
512 bank->size = flash_size_in_kb * 1024;
513 bank->num_sectors = num_sectors;
514 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
515 if (bank->sectors == NULL) {
516 LOG_ERROR("failed to allocate bank sectors");
517 return ERROR_FAIL;
518 }
519
520 for (i = 0; i < num_sectors; i++) {
521 bank->sectors[i].offset = i * FLASH_SECTOR_SIZE;
522 bank->sectors[i].size = FLASH_SECTOR_SIZE;
523 bank->sectors[i].is_erased = -1;
524 bank->sectors[i].is_protected = 1;
525 }
526
527 stm32lx_info->probed = 1;
528
529 return ERROR_OK;
530 }
531
532 static int stm32lx_auto_probe(struct flash_bank *bank)
533 {
534 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
535
536 if (stm32lx_info->probed)
537 return ERROR_OK;
538
539 return stm32lx_probe(bank);
540 }
541
542 static int stm32lx_erase_check(struct flash_bank *bank)
543 {
544 struct target *target = bank->target;
545 const int buffer_size = 4096;
546 int i;
547 uint32_t nBytes;
548 int retval = ERROR_OK;
549
550 if (bank->target->state != TARGET_HALTED) {
551 LOG_ERROR("Target not halted");
552 return ERROR_TARGET_NOT_HALTED;
553 }
554
555 uint8_t *buffer = malloc(buffer_size);
556 if (buffer == NULL) {
557 LOG_ERROR("failed to allocate read buffer");
558 return ERROR_FAIL;
559 }
560
561 for (i = 0; i < bank->num_sectors; i++) {
562 uint32_t j;
563 bank->sectors[i].is_erased = 1;
564
565 /* Loop chunk by chunk over the sector */
566 for (j = 0; j < bank->sectors[i].size; j += buffer_size) {
567 uint32_t chunk;
568 chunk = buffer_size;
569 if (chunk > (j - bank->sectors[i].size))
570 chunk = (j - bank->sectors[i].size);
571
572 retval = target_read_memory(target, bank->base
573 + bank->sectors[i].offset + j, 4, chunk / 4, buffer);
574 if (retval != ERROR_OK)
575 break;
576
577 for (nBytes = 0; nBytes < chunk; nBytes++) {
578 if (buffer[nBytes] != 0x00) {
579 bank->sectors[i].is_erased = 0;
580 break;
581 }
582 }
583 }
584 if (retval != ERROR_OK)
585 break;
586 }
587 free(buffer);
588
589 return retval;
590 }
591
592 static int stm32lx_get_info(struct flash_bank *bank, char *buf, int buf_size)
593 {
594 /* This method must return a string displaying information about the bank */
595
596 struct target *target = bank->target;
597 uint32_t device_id;
598 int printed;
599
600 /* read stm32 device id register */
601 int retval = target_read_u32(target, DBGMCU_IDCODE, &device_id);
602 if (retval != ERROR_OK)
603 return retval;
604
605 if ((device_id & 0xfff) == 0x416) {
606 printed = snprintf(buf, buf_size, "stm32lx - Rev: ");
607 buf += printed;
608 buf_size -= printed;
609
610 switch (device_id >> 16) {
611 case 0x1000:
612 snprintf(buf, buf_size, "A");
613 break;
614
615 case 0x1008:
616 snprintf(buf, buf_size, "Y");
617 break;
618
619 case 0x1018:
620 snprintf(buf, buf_size, "X");
621 break;
622
623 case 0x1038:
624 snprintf(buf, buf_size, "W");
625 break;
626
627 case 0x1078:
628 snprintf(buf, buf_size, "V");
629 break;
630
631 default:
632 snprintf(buf, buf_size, "unknown");
633 break;
634 }
635 } else if ((device_id & 0xfff) == 0x436) {
636 printed = snprintf(buf, buf_size, "stm32lx (HD) - Rev: ");
637 buf += printed;
638 buf_size -= printed;
639
640 switch (device_id >> 16) {
641 case 0x1000:
642 snprintf(buf, buf_size, "A");
643 break;
644
645 case 0x1008:
646 snprintf(buf, buf_size, "Z");
647 break;
648
649 case 0x1018:
650 snprintf(buf, buf_size, "Y");
651 break;
652
653 default:
654 snprintf(buf, buf_size, "unknown");
655 break;
656 }
657 } else {
658 snprintf(buf, buf_size, "Cannot identify target as a stm32lx");
659 return ERROR_FAIL;
660 }
661
662 return ERROR_OK;
663 }
664
665 static const struct command_registration stm32lx_exec_command_handlers[] = {
666 COMMAND_REGISTRATION_DONE
667 };
668
669 static const struct command_registration stm32lx_command_handlers[] = {
670 {
671 .name = "stm32lx",
672 .mode = COMMAND_ANY,
673 .help = "stm32lx flash command group",
674 .usage = "",
675 .chain = stm32lx_exec_command_handlers,
676 },
677 COMMAND_REGISTRATION_DONE
678 };
679
680 struct flash_driver stm32lx_flash = {
681 .name = "stm32lx",
682 .commands = stm32lx_command_handlers,
683 .flash_bank_command = stm32lx_flash_bank_command,
684 .erase = stm32lx_erase,
685 .protect = stm32lx_protect,
686 .write = stm32lx_write,
687 .read = default_flash_read,
688 .probe = stm32lx_probe,
689 .auto_probe = stm32lx_auto_probe,
690 .erase_check = stm32lx_erase_check,
691 .protect_check = stm32lx_protect_check,
692 .info = stm32lx_get_info,
693 };
694
695 /* Static methods implementation */
696 static int stm32lx_unlock_program_memory(struct flash_bank *bank)
697 {
698 struct target *target = bank->target;
699 int retval;
700 uint32_t reg32;
701
702 /*
703 * Unlocking the program memory is done by unlocking the PECR,
704 * then by writing the 2 PRGKEY to the PRGKEYR register
705 */
706
707 /* To unlock the PECR write the 2 PEKEY to the PEKEYR register */
708 retval = target_write_u32(target, FLASH_PEKEYR, PEKEY1);
709 if (retval != ERROR_OK)
710 return retval;
711
712 retval = target_write_u32(target, FLASH_PEKEYR, PEKEY2);
713 if (retval != ERROR_OK)
714 return retval;
715
716 /* Make sure it worked */
717 retval = target_read_u32(target, FLASH_PECR, &reg32);
718 if (retval != ERROR_OK)
719 return retval;
720
721 if (reg32 & FLASH_PECR__PELOCK) {
722 LOG_ERROR("PELOCK is not cleared :(");
723 return ERROR_FLASH_OPERATION_FAILED;
724 }
725
726 retval = target_write_u32(target, FLASH_PRGKEYR, PRGKEY1);
727 if (retval != ERROR_OK)
728 return retval;
729 retval = target_write_u32(target, FLASH_PRGKEYR, PRGKEY2);
730 if (retval != ERROR_OK)
731 return retval;
732
733 /* Make sure it worked */
734 retval = target_read_u32(target, FLASH_PECR, &reg32);
735 if (retval != ERROR_OK)
736 return retval;
737
738 if (reg32 & FLASH_PECR__PRGLOCK) {
739 LOG_ERROR("PRGLOCK is not cleared :(");
740 return ERROR_FLASH_OPERATION_FAILED;
741 }
742 return ERROR_OK;
743 }
744
745 static int stm32lx_enable_write_half_page(struct flash_bank *bank)
746 {
747 struct target *target = bank->target;
748 int retval;
749 uint32_t reg32;
750
751 /**
752 * Unlock the program memory, then set the FPRG bit in the PECR register.
753 */
754 retval = stm32lx_unlock_program_memory(bank);
755 if (retval != ERROR_OK)
756 return retval;
757
758 retval = target_read_u32(target, FLASH_PECR, &reg32);
759 if (retval != ERROR_OK)
760 return retval;
761
762 reg32 |= FLASH_PECR__FPRG;
763 retval = target_write_u32(target, FLASH_PECR, reg32);
764 if (retval != ERROR_OK)
765 return retval;
766
767 retval = target_read_u32(target, FLASH_PECR, &reg32);
768 if (retval != ERROR_OK)
769 return retval;
770
771 reg32 |= FLASH_PECR__PROG;
772 retval = target_write_u32(target, FLASH_PECR, reg32);
773
774 return retval;
775 }
776
777 static int stm32lx_lock_program_memory(struct flash_bank *bank)
778 {
779 struct target *target = bank->target;
780 int retval;
781 uint32_t reg32;
782
783 /* To lock the program memory, simply set the lock bit and lock PECR */
784
785 retval = target_read_u32(target, FLASH_PECR, &reg32);
786 if (retval != ERROR_OK)
787 return retval;
788
789 reg32 |= FLASH_PECR__PRGLOCK;
790 retval = target_write_u32(target, FLASH_PECR, reg32);
791 if (retval != ERROR_OK)
792 return retval;
793
794 retval = target_read_u32(target, FLASH_PECR, &reg32);
795 if (retval != ERROR_OK)
796 return retval;
797
798 reg32 |= FLASH_PECR__PELOCK;
799 retval = target_write_u32(target, FLASH_PECR, reg32);
800 if (retval != ERROR_OK)
801 return retval;
802
803 return ERROR_OK;
804 }
805
806 static int stm32lx_erase_sector(struct flash_bank *bank, int sector)
807 {
808 struct target *target = bank->target;
809 int retval;
810 uint32_t reg32;
811
812 /*
813 * To erase a sector (i.e. FLASH_PAGES_PER_SECTOR pages),
814 * first unlock the memory, loop over the pages of this sector
815 * and write 0x0 to its first word.
816 */
817
818 retval = stm32lx_unlock_program_memory(bank);
819 if (retval != ERROR_OK)
820 return retval;
821
822 for (int page = 0; page < FLASH_PAGES_PER_SECTOR; page++) {
823 reg32 = FLASH_PECR__PROG | FLASH_PECR__ERASE;
824 retval = target_write_u32(target, FLASH_PECR, reg32);
825 if (retval != ERROR_OK)
826 return retval;
827
828 retval = stm32lx_wait_until_bsy_clear(bank);
829 if (retval != ERROR_OK)
830 return retval;
831
832 uint32_t addr = bank->base + bank->sectors[sector].offset + (page
833 * FLASH_PAGE_SIZE);
834 retval = target_write_u32(target, addr, 0x0);
835 if (retval != ERROR_OK)
836 return retval;
837
838 retval = stm32lx_wait_until_bsy_clear(bank);
839 if (retval != ERROR_OK)
840 return retval;
841 }
842
843 retval = stm32lx_lock_program_memory(bank);
844 if (retval != ERROR_OK)
845 return retval;
846
847 return ERROR_OK;
848 }
849
850 static int stm32lx_wait_until_bsy_clear(struct flash_bank *bank)
851 {
852 struct target *target = bank->target;
853 uint32_t status;
854 int retval = ERROR_OK;
855 int timeout = 100;
856
857 /* wait for busy to clear */
858 for (;;) {
859 retval = target_read_u32(target, FLASH_SR, &status);
860 if (retval != ERROR_OK)
861 return retval;
862
863 if ((status & FLASH_SR__BSY) == 0)
864 break;
865 if (timeout-- <= 0) {
866 LOG_ERROR("timed out waiting for flash");
867 return ERROR_FAIL;
868 }
869 alive_sleep(1);
870 }
871
872 if (status & FLASH_SR__WRPERR) {
873 LOG_ERROR("access denied / write protected");
874 retval = ERROR_FAIL;
875 }
876
877 if (status & FLASH_SR__PGAERR) {
878 LOG_ERROR("invalid program address");
879 retval = ERROR_FAIL;
880 }
881
882 return retval;
883 }
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