1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2011 by Clement Burin des Roziers *
9 * clement.burin-des-roziers@hikob.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34 #include <target/armv7m.h>
36 /* stm32lx flash register locations */
38 #define FLASH_BASE 0x40023C00
39 #define FLASH_ACR 0x40023C00
40 #define FLASH_PECR 0x40023C04
41 #define FLASH_PDKEYR 0x40023C08
42 #define FLASH_PEKEYR 0x40023C0C
43 #define FLASH_PRGKEYR 0x40023C10
44 #define FLASH_OPTKEYR 0x40023C14
45 #define FLASH_SR 0x40023C18
46 #define FLASH_OBR 0x40023C1C
47 #define FLASH_WRPR 0x40023C20
50 #define FLASH_ACR__LATENCY (1<<0)
51 #define FLASH_ACR__PRFTEN (1<<1)
52 #define FLASH_ACR__ACC64 (1<<2)
53 #define FLASH_ACR__SLEEP_PD (1<<3)
54 #define FLASH_ACR__RUN_PD (1<<4)
57 #define FLASH_PECR__PELOCK (1<<0)
58 #define FLASH_PECR__PRGLOCK (1<<1)
59 #define FLASH_PECR__OPTLOCK (1<<2)
60 #define FLASH_PECR__PROG (1<<3)
61 #define FLASH_PECR__DATA (1<<4)
62 #define FLASH_PECR__FTDW (1<<8)
63 #define FLASH_PECR__ERASE (1<<9)
64 #define FLASH_PECR__FPRG (1<<10)
65 #define FLASH_PECR__EOPIE (1<<16)
66 #define FLASH_PECR__ERRIE (1<<17)
67 #define FLASH_PECR__OBL_LAUNCH (1<<18)
70 #define FLASH_SR__BSY (1<<0)
71 #define FLASH_SR__EOP (1<<1)
72 #define FLASH_SR__ENDHV (1<<2)
73 #define FLASH_SR__READY (1<<3)
74 #define FLASH_SR__WRPERR (1<<8)
75 #define FLASH_SR__PGAERR (1<<9)
76 #define FLASH_SR__SIZERR (1<<10)
77 #define FLASH_SR__OPTVERR (1<<11)
80 #define PEKEY1 0x89ABCDEF
81 #define PEKEY2 0x02030405
82 #define PRGKEY1 0x8C9DAEBF
83 #define PRGKEY2 0x13141516
84 #define OPTKEY1 0xFBEAD9C8
85 #define OPTKEY2 0x24252627
88 #define DBGMCU_IDCODE 0xE0042000
89 #define F_SIZE 0x1FF8004C
92 #define FLASH_PAGE_SIZE 256
93 #define FLASH_SECTOR_SIZE 4096
94 #define FLASH_PAGES_PER_SECTOR 16
95 #define FLASH_BANK0_ADDRESS 0x08000000
97 /* stm32lx option byte register location */
98 #define OB_RDP 0x1FF80000
99 #define OB_USER 0x1FF80004
100 #define OB_WRP0_1 0x1FF80008
101 #define OB_WRP2_3 0x1FF8000C
104 #define OB_RDP__LEVEL0 0xFF5500AA
105 #define OB_RDP__LEVEL1 0xFFFF0000
107 /* stm32lx RCC register locations */
108 #define RCC_CR 0x40023800
109 #define RCC_ICSCR 0x40023804
110 #define RCC_CFGR 0x40023808
113 #define RCC_ICSCR__MSIRANGE_MASK (7<<13)
115 static int stm32lx_unlock_program_memory(struct flash_bank
*bank
);
116 static int stm32lx_lock_program_memory(struct flash_bank
*bank
);
117 static int stm32lx_enable_write_half_page(struct flash_bank
*bank
);
118 static int stm32lx_erase_sector(struct flash_bank
*bank
, int sector
);
119 static int stm32lx_wait_until_bsy_clear(struct flash_bank
*bank
);
121 struct stm32lx_flash_bank
{
125 /* flash bank stm32lx <base> <size> 0 0 <target#>
127 FLASH_BANK_COMMAND_HANDLER(stm32lx_flash_bank_command
)
129 struct stm32lx_flash_bank
*stm32lx_info
;
131 return ERROR_COMMAND_SYNTAX_ERROR
;
133 /* Create the bank structure */
134 stm32lx_info
= malloc(sizeof(struct stm32lx_flash_bank
));
136 /* Check allocation */
137 if (stm32lx_info
== NULL
) {
138 LOG_ERROR("failed to allocate bank structure");
142 bank
->driver_priv
= stm32lx_info
;
144 stm32lx_info
->probed
= 0;
149 static int stm32lx_protect_check(struct flash_bank
*bank
)
152 struct target
*target
= bank
->target
;
156 if (target
->state
!= TARGET_HALTED
) {
157 LOG_ERROR("Target not halted");
158 return ERROR_TARGET_NOT_HALTED
;
162 * Read the WRPR word, and check each bit (corresponding to each
165 retval
= target_read_u32(target
, FLASH_WRPR
, &wrpr
);
166 if (retval
!= ERROR_OK
)
169 for (int i
= 0; i
< 32; i
++) {
171 bank
->sectors
[i
].is_protected
= 1;
173 bank
->sectors
[i
].is_protected
= 0;
178 static int stm32lx_erase(struct flash_bank
*bank
, int first
, int last
)
183 * It could be possible to do a mass erase if all sectors must be
184 * erased, but it is not implemented yet.
187 if (bank
->target
->state
!= TARGET_HALTED
) {
188 LOG_ERROR("Target not halted");
189 return ERROR_TARGET_NOT_HALTED
;
193 * Loop over the selected sectors and erase them
195 for (int i
= first
; i
<= last
; i
++) {
196 retval
= stm32lx_erase_sector(bank
, i
);
197 if (retval
!= ERROR_OK
)
199 bank
->sectors
[i
].is_erased
= 1;
204 static int stm32lx_protect(struct flash_bank
*bank
, int set
, int first
,
207 LOG_WARNING("protection of the STM32L flash is not implemented");
211 static int stm32lx_write_half_pages(struct flash_bank
*bank
, uint8_t *buffer
,
212 uint32_t offset
, uint32_t count
)
214 struct target
*target
= bank
->target
;
215 uint32_t buffer_size
= 16384;
216 struct working_area
*write_algorithm
;
217 struct working_area
*source
;
218 uint32_t address
= bank
->base
+ offset
;
220 struct reg_param reg_params
[3];
221 struct armv7m_algorithm armv7m_info
;
223 int retval
= ERROR_OK
;
225 /* see contib/loaders/flash/stm32lx.S for src */
227 static const uint8_t stm32lx_flash_write_code
[] = {
229 0x00, 0x23, /* movs r3, #0 */
230 0x04, 0xe0, /* b test_done */
233 0x51, 0xf8, 0x04, 0xcb, /* ldr ip, [r1], #4 */
234 0x40, 0xf8, 0x04, 0xcb, /* str ip, [r0], #4 */
235 0x01, 0x33, /* adds r3, #1 */
238 0x93, 0x42, /* cmp r3, r2 */
239 0xf8, 0xd3, /* bcc write_word */
240 0x00, 0xbe, /* bkpt 0 */
243 /* Check if there is an even number of half pages (128bytes) */
245 LOG_ERROR("there should be an even number "
246 "of half pages = 128 bytes (count = %" PRIi32
" bytes)", count
);
250 /* flash write code */
251 if (target_alloc_working_area(target
, sizeof(stm32lx_flash_write_code
),
252 &write_algorithm
) != ERROR_OK
) {
253 LOG_DEBUG("no working area for block memory writes");
254 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
257 /* Write the flashing code */
258 retval
= target_write_buffer(target
,
259 write_algorithm
->address
,
260 sizeof(stm32lx_flash_write_code
),
261 (uint8_t *)stm32lx_flash_write_code
);
262 if (retval
!= ERROR_OK
) {
263 target_free_working_area(target
, write_algorithm
);
267 /* Allocate half pages memory */
268 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
) {
269 if (buffer_size
> 1024)
274 if (buffer_size
<= 256) {
275 /* we already allocated the writing code, but failed to get a
276 * buffer, free the algorithm */
277 target_free_working_area(target
, write_algorithm
);
279 LOG_WARNING("no large enough working area available, can't do block memory writes");
280 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
284 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
285 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
286 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
287 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
288 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
290 /* Enable half-page write */
291 retval
= stm32lx_enable_write_half_page(bank
);
292 if (retval
!= ERROR_OK
) {
293 target_free_working_area(target
, source
);
294 target_free_working_area(target
, write_algorithm
);
296 destroy_reg_param(®_params
[0]);
297 destroy_reg_param(®_params
[1]);
298 destroy_reg_param(®_params
[2]);
302 /* Loop while there are bytes to write */
305 this_count
= (count
> buffer_size
) ? buffer_size
: count
;
307 /* Write the next half pages */
308 retval
= target_write_buffer(target
, source
->address
, this_count
, buffer
);
309 if (retval
!= ERROR_OK
)
312 /* 4: Store useful information in the registers */
313 /* the destination address of the copy (R0) */
314 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
315 /* The source address of the copy (R1) */
316 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
);
317 /* The length of the copy (R2) */
318 buf_set_u32(reg_params
[2].value
, 0, 32, this_count
/ 4);
320 /* 5: Execute the bunch of code */
321 retval
= target_run_algorithm(target
, 0, NULL
, sizeof(reg_params
)
322 / sizeof(*reg_params
), reg_params
,
323 write_algorithm
->address
, 0, 20000, &armv7m_info
);
324 if (retval
!= ERROR_OK
)
327 /* 6: Wait while busy */
328 retval
= stm32lx_wait_until_bsy_clear(bank
);
329 if (retval
!= ERROR_OK
)
332 buffer
+= this_count
;
333 address
+= this_count
;
337 if (retval
== ERROR_OK
)
338 retval
= stm32lx_lock_program_memory(bank
);
340 target_free_working_area(target
, source
);
341 target_free_working_area(target
, write_algorithm
);
343 destroy_reg_param(®_params
[0]);
344 destroy_reg_param(®_params
[1]);
345 destroy_reg_param(®_params
[2]);
350 static int stm32lx_write(struct flash_bank
*bank
, uint8_t *buffer
,
351 uint32_t offset
, uint32_t count
)
353 struct target
*target
= bank
->target
;
355 uint32_t halfpages_number
;
356 uint32_t bytes_remaining
= 0;
357 uint32_t address
= bank
->base
+ offset
;
358 uint32_t bytes_written
= 0;
361 if (bank
->target
->state
!= TARGET_HALTED
) {
362 LOG_ERROR("Target not halted");
363 return ERROR_TARGET_NOT_HALTED
;
367 LOG_ERROR("offset 0x%" PRIx32
" breaks required 4-byte alignment", offset
);
368 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
371 retval
= stm32lx_unlock_program_memory(bank
);
372 if (retval
!= ERROR_OK
)
375 /* first we need to write any unaligned head bytes upto
376 * the next 128 byte page */
379 bytes_remaining
= MIN(count
, 128 - (offset
% 128));
381 while (bytes_remaining
> 0) {
382 uint8_t value
[4] = {0xff, 0xff, 0xff, 0xff};
384 /* copy remaining bytes into the write buffer */
385 uint32_t bytes_to_write
= MIN(4, bytes_remaining
);
386 memcpy(value
, buffer
+ bytes_written
, bytes_to_write
);
388 retval
= target_write_buffer(target
, address
, 4, value
);
389 if (retval
!= ERROR_OK
)
390 goto reset_pg_and_lock
;
392 bytes_written
+= bytes_to_write
;
393 bytes_remaining
-= bytes_to_write
;
396 retval
= stm32lx_wait_until_bsy_clear(bank
);
397 if (retval
!= ERROR_OK
)
398 goto reset_pg_and_lock
;
401 offset
+= bytes_written
;
402 count
-= bytes_written
;
404 /* this should always pass this check here */
405 assert((offset
% 128) == 0);
407 /* calculate half pages */
408 halfpages_number
= count
/ 128;
410 if (halfpages_number
) {
411 retval
= stm32lx_write_half_pages(bank
, buffer
+ bytes_written
, offset
, 128 * halfpages_number
);
412 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
) {
413 /* attempt slow memory writes */
414 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
415 halfpages_number
= 0;
417 if (retval
!= ERROR_OK
)
422 /* write any remaining bytes */
423 uint32_t page_bytes_written
= 128 * halfpages_number
;
424 bytes_written
+= page_bytes_written
;
425 address
+= page_bytes_written
;
426 bytes_remaining
= count
- page_bytes_written
;
428 retval
= stm32lx_unlock_program_memory(bank
);
429 if (retval
!= ERROR_OK
)
432 while (bytes_remaining
> 0) {
433 uint8_t value
[4] = {0xff, 0xff, 0xff, 0xff};
435 /* copy remaining bytes into the write buffer */
436 uint32_t bytes_to_write
= MIN(4, bytes_remaining
);
437 memcpy(value
, buffer
+ bytes_written
, bytes_to_write
);
439 retval
= target_write_buffer(target
, address
, 4, value
);
440 if (retval
!= ERROR_OK
)
441 goto reset_pg_and_lock
;
443 bytes_written
+= bytes_to_write
;
444 bytes_remaining
-= bytes_to_write
;
447 retval
= stm32lx_wait_until_bsy_clear(bank
);
448 if (retval
!= ERROR_OK
)
449 goto reset_pg_and_lock
;
453 retval2
= stm32lx_lock_program_memory(bank
);
454 if (retval
== ERROR_OK
)
460 static int stm32lx_probe(struct flash_bank
*bank
)
462 struct target
*target
= bank
->target
;
463 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
465 uint16_t flash_size_in_kb
;
466 uint16_t max_flash_size_in_kb
;
469 stm32lx_info
->probed
= 0;
471 /* read stm32 device id register */
472 int retval
= target_read_u32(target
, DBGMCU_IDCODE
, &device_id
);
473 if (retval
!= ERROR_OK
)
476 LOG_DEBUG("device id = 0x%08" PRIx32
"", device_id
);
478 /* set max flash size depending on family */
479 switch (device_id
& 0xfff) {
481 max_flash_size_in_kb
= 128;
484 max_flash_size_in_kb
= 384;
487 LOG_WARNING("Cannot identify target as a STM32L family.");
491 /* get flash size from target. */
492 retval
= target_read_u16(target
, F_SIZE
, &flash_size_in_kb
);
494 /* failed reading flash size or flash size invalid (early silicon),
495 * default to max target family */
496 if (retval
!= ERROR_OK
|| flash_size_in_kb
== 0xffff || flash_size_in_kb
== 0) {
497 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
498 max_flash_size_in_kb
);
499 flash_size_in_kb
= max_flash_size_in_kb
;
502 /* STM32L - we have 32 sectors, 16 pages per sector -> 512 pages
503 * 16 pages for a protection area */
505 /* calculate numbers of sectors (4kB per sector) */
506 int num_sectors
= (flash_size_in_kb
* 1024) / FLASH_SECTOR_SIZE
;
507 LOG_INFO("flash size = %dkbytes", flash_size_in_kb
);
511 bank
->sectors
= NULL
;
514 bank
->base
= FLASH_BANK0_ADDRESS
;
515 bank
->size
= flash_size_in_kb
* 1024;
516 bank
->num_sectors
= num_sectors
;
517 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_sectors
);
518 if (bank
->sectors
== NULL
) {
519 LOG_ERROR("failed to allocate bank sectors");
523 for (i
= 0; i
< num_sectors
; i
++) {
524 bank
->sectors
[i
].offset
= i
* FLASH_SECTOR_SIZE
;
525 bank
->sectors
[i
].size
= FLASH_SECTOR_SIZE
;
526 bank
->sectors
[i
].is_erased
= -1;
527 bank
->sectors
[i
].is_protected
= 1;
530 stm32lx_info
->probed
= 1;
535 static int stm32lx_auto_probe(struct flash_bank
*bank
)
537 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
539 if (stm32lx_info
->probed
)
542 return stm32lx_probe(bank
);
545 static int stm32lx_erase_check(struct flash_bank
*bank
)
547 struct target
*target
= bank
->target
;
548 const int buffer_size
= 4096;
551 int retval
= ERROR_OK
;
553 if (bank
->target
->state
!= TARGET_HALTED
) {
554 LOG_ERROR("Target not halted");
555 return ERROR_TARGET_NOT_HALTED
;
558 uint8_t *buffer
= malloc(buffer_size
);
559 if (buffer
== NULL
) {
560 LOG_ERROR("failed to allocate read buffer");
564 for (i
= 0; i
< bank
->num_sectors
; i
++) {
566 bank
->sectors
[i
].is_erased
= 1;
568 /* Loop chunk by chunk over the sector */
569 for (j
= 0; j
< bank
->sectors
[i
].size
; j
+= buffer_size
) {
572 if (chunk
> (j
- bank
->sectors
[i
].size
))
573 chunk
= (j
- bank
->sectors
[i
].size
);
575 retval
= target_read_memory(target
, bank
->base
576 + bank
->sectors
[i
].offset
+ j
, 4, chunk
/ 4, buffer
);
577 if (retval
!= ERROR_OK
)
580 for (nBytes
= 0; nBytes
< chunk
; nBytes
++) {
581 if (buffer
[nBytes
] != 0x00) {
582 bank
->sectors
[i
].is_erased
= 0;
587 if (retval
!= ERROR_OK
)
595 static int stm32lx_get_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
597 /* This method must return a string displaying information about the bank */
599 struct target
*target
= bank
->target
;
603 /* read stm32 device id register */
604 int retval
= target_read_u32(target
, DBGMCU_IDCODE
, &device_id
);
605 if (retval
!= ERROR_OK
)
608 if ((device_id
& 0xfff) == 0x416) {
609 printed
= snprintf(buf
, buf_size
, "stm32lx - Rev: ");
613 switch (device_id
>> 16) {
615 snprintf(buf
, buf_size
, "A");
619 snprintf(buf
, buf_size
, "Y");
623 snprintf(buf
, buf_size
, "X");
627 snprintf(buf
, buf_size
, "W");
631 snprintf(buf
, buf_size
, "V");
635 snprintf(buf
, buf_size
, "unknown");
638 } else if ((device_id
& 0xfff) == 0x436) {
639 printed
= snprintf(buf
, buf_size
, "stm32lx (HD) - Rev: ");
643 switch (device_id
>> 16) {
645 snprintf(buf
, buf_size
, "A");
649 snprintf(buf
, buf_size
, "Z");
653 snprintf(buf
, buf_size
, "Y");
657 snprintf(buf
, buf_size
, "unknown");
661 snprintf(buf
, buf_size
, "Cannot identify target as a stm32lx");
668 static const struct command_registration stm32lx_exec_command_handlers
[] = {
669 COMMAND_REGISTRATION_DONE
672 static const struct command_registration stm32lx_command_handlers
[] = {
676 .help
= "stm32lx flash command group",
678 .chain
= stm32lx_exec_command_handlers
,
680 COMMAND_REGISTRATION_DONE
683 struct flash_driver stm32lx_flash
= {
685 .commands
= stm32lx_command_handlers
,
686 .flash_bank_command
= stm32lx_flash_bank_command
,
687 .erase
= stm32lx_erase
,
688 .protect
= stm32lx_protect
,
689 .write
= stm32lx_write
,
690 .read
= default_flash_read
,
691 .probe
= stm32lx_probe
,
692 .auto_probe
= stm32lx_auto_probe
,
693 .erase_check
= stm32lx_erase_check
,
694 .protect_check
= stm32lx_protect_check
,
695 .info
= stm32lx_get_info
,
698 /* Static methods implementation */
699 static int stm32lx_unlock_program_memory(struct flash_bank
*bank
)
701 struct target
*target
= bank
->target
;
706 * Unlocking the program memory is done by unlocking the PECR,
707 * then by writing the 2 PRGKEY to the PRGKEYR register
710 /* check flash is not already unlocked */
711 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
712 if (retval
!= ERROR_OK
)
715 if ((reg32
& FLASH_PECR__PRGLOCK
) == 0)
718 /* To unlock the PECR write the 2 PEKEY to the PEKEYR register */
719 retval
= target_write_u32(target
, FLASH_PEKEYR
, PEKEY1
);
720 if (retval
!= ERROR_OK
)
723 retval
= target_write_u32(target
, FLASH_PEKEYR
, PEKEY2
);
724 if (retval
!= ERROR_OK
)
727 /* Make sure it worked */
728 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
729 if (retval
!= ERROR_OK
)
732 if (reg32
& FLASH_PECR__PELOCK
) {
733 LOG_ERROR("PELOCK is not cleared :(");
734 return ERROR_FLASH_OPERATION_FAILED
;
737 retval
= target_write_u32(target
, FLASH_PRGKEYR
, PRGKEY1
);
738 if (retval
!= ERROR_OK
)
740 retval
= target_write_u32(target
, FLASH_PRGKEYR
, PRGKEY2
);
741 if (retval
!= ERROR_OK
)
744 /* Make sure it worked */
745 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
746 if (retval
!= ERROR_OK
)
749 if (reg32
& FLASH_PECR__PRGLOCK
) {
750 LOG_ERROR("PRGLOCK is not cleared :(");
751 return ERROR_FLASH_OPERATION_FAILED
;
757 static int stm32lx_enable_write_half_page(struct flash_bank
*bank
)
759 struct target
*target
= bank
->target
;
764 * Unlock the program memory, then set the FPRG bit in the PECR register.
766 retval
= stm32lx_unlock_program_memory(bank
);
767 if (retval
!= ERROR_OK
)
770 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
771 if (retval
!= ERROR_OK
)
774 reg32
|= FLASH_PECR__FPRG
;
775 retval
= target_write_u32(target
, FLASH_PECR
, reg32
);
776 if (retval
!= ERROR_OK
)
779 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
780 if (retval
!= ERROR_OK
)
783 reg32
|= FLASH_PECR__PROG
;
784 retval
= target_write_u32(target
, FLASH_PECR
, reg32
);
789 static int stm32lx_lock_program_memory(struct flash_bank
*bank
)
791 struct target
*target
= bank
->target
;
795 /* To lock the program memory, simply set the lock bit and lock PECR */
797 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
798 if (retval
!= ERROR_OK
)
801 reg32
|= FLASH_PECR__PRGLOCK
;
802 retval
= target_write_u32(target
, FLASH_PECR
, reg32
);
803 if (retval
!= ERROR_OK
)
806 retval
= target_read_u32(target
, FLASH_PECR
, ®32
);
807 if (retval
!= ERROR_OK
)
810 reg32
|= FLASH_PECR__PELOCK
;
811 retval
= target_write_u32(target
, FLASH_PECR
, reg32
);
812 if (retval
!= ERROR_OK
)
818 static int stm32lx_erase_sector(struct flash_bank
*bank
, int sector
)
820 struct target
*target
= bank
->target
;
825 * To erase a sector (i.e. FLASH_PAGES_PER_SECTOR pages),
826 * first unlock the memory, loop over the pages of this sector
827 * and write 0x0 to its first word.
830 retval
= stm32lx_unlock_program_memory(bank
);
831 if (retval
!= ERROR_OK
)
834 for (int page
= 0; page
< FLASH_PAGES_PER_SECTOR
; page
++) {
835 reg32
= FLASH_PECR__PROG
| FLASH_PECR__ERASE
;
836 retval
= target_write_u32(target
, FLASH_PECR
, reg32
);
837 if (retval
!= ERROR_OK
)
840 retval
= stm32lx_wait_until_bsy_clear(bank
);
841 if (retval
!= ERROR_OK
)
844 uint32_t addr
= bank
->base
+ bank
->sectors
[sector
].offset
+ (page
846 retval
= target_write_u32(target
, addr
, 0x0);
847 if (retval
!= ERROR_OK
)
850 retval
= stm32lx_wait_until_bsy_clear(bank
);
851 if (retval
!= ERROR_OK
)
855 retval
= stm32lx_lock_program_memory(bank
);
856 if (retval
!= ERROR_OK
)
862 static int stm32lx_wait_until_bsy_clear(struct flash_bank
*bank
)
864 struct target
*target
= bank
->target
;
866 int retval
= ERROR_OK
;
869 /* wait for busy to clear */
871 retval
= target_read_u32(target
, FLASH_SR
, &status
);
872 if (retval
!= ERROR_OK
)
875 if ((status
& FLASH_SR__BSY
) == 0)
877 if (timeout
-- <= 0) {
878 LOG_ERROR("timed out waiting for flash");
884 if (status
& FLASH_SR__WRPERR
) {
885 LOG_ERROR("access denied / write protected");
889 if (status
& FLASH_SR__PGAERR
) {
890 LOG_ERROR("invalid program address");
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)