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[openocd.git] / src / flash / nor / stm32x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "imp.h"
28 #include "stm32x.h"
29 #include <helper/binarybuffer.h>
30 #include <target/algorithm.h>
31 #include <target/armv7m.h>
32
33
34 static int stm32x_mass_erase(struct flash_bank *bank);
35
36 /* flash bank stm32x <base> <size> 0 0 <target#>
37 */
38 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
39 {
40 struct stm32x_flash_bank *stm32x_info;
41
42 if (CMD_ARGC < 6)
43 {
44 LOG_WARNING("incomplete flash_bank stm32x configuration");
45 return ERROR_FLASH_BANK_INVALID;
46 }
47
48 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
49 bank->driver_priv = stm32x_info;
50
51 stm32x_info->write_algorithm = NULL;
52 stm32x_info->probed = 0;
53
54 return ERROR_OK;
55 }
56
57 static uint32_t stm32x_get_flash_status(struct flash_bank *bank)
58 {
59 struct target *target = bank->target;
60 uint32_t status;
61
62 target_read_u32(target, STM32_FLASH_SR, &status);
63
64 return status;
65 }
66
67 static uint32_t stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
68 {
69 struct target *target = bank->target;
70 uint32_t status;
71
72 /* wait for busy to clear */
73 while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))
74 {
75 LOG_DEBUG("status: 0x%" PRIx32 "", status);
76 alive_sleep(1);
77 }
78 /* Clear but report errors */
79 if (status & (FLASH_WRPRTERR | FLASH_PGERR))
80 {
81 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR | FLASH_PGERR);
82 }
83 return status;
84 }
85
86 static int stm32x_read_options(struct flash_bank *bank)
87 {
88 uint32_t optiondata;
89 struct stm32x_flash_bank *stm32x_info = NULL;
90 struct target *target = bank->target;
91
92 stm32x_info = bank->driver_priv;
93
94 /* read current option bytes */
95 target_read_u32(target, STM32_FLASH_OBR, &optiondata);
96
97 stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
98 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
99
100 if (optiondata & (1 << OPT_READOUT))
101 LOG_INFO("Device Security Bit Set");
102
103 /* each bit refers to a 4bank protection */
104 target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
105
106 stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
107 stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
108 stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
109 stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
110
111 return ERROR_OK;
112 }
113
114 static int stm32x_erase_options(struct flash_bank *bank)
115 {
116 struct stm32x_flash_bank *stm32x_info = NULL;
117 struct target *target = bank->target;
118 uint32_t status;
119
120 stm32x_info = bank->driver_priv;
121
122 /* read current options */
123 stm32x_read_options(bank);
124
125 /* unlock flash registers */
126 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
127 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
128
129 /* unlock option flash registers */
130 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
131 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
132
133 /* erase option bytes */
134 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_OPTWRE);
135 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
136
137 status = stm32x_wait_status_busy(bank, 10);
138
139 if (status & FLASH_WRPRTERR)
140 return ERROR_FLASH_OPERATION_FAILED;
141 if (status & FLASH_PGERR)
142 return ERROR_FLASH_OPERATION_FAILED;
143
144 /* clear readout protection and complementary option bytes
145 * this will also force a device unlock if set */
146 stm32x_info->option_bytes.RDP = 0x5AA5;
147
148 return ERROR_OK;
149 }
150
151 static int stm32x_write_options(struct flash_bank *bank)
152 {
153 struct stm32x_flash_bank *stm32x_info = NULL;
154 struct target *target = bank->target;
155 uint32_t status;
156
157 stm32x_info = bank->driver_priv;
158
159 /* unlock flash registers */
160 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
161 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
162
163 /* unlock option flash registers */
164 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
165 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
166
167 /* program option bytes */
168 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG | FLASH_OPTWRE);
169
170 /* write user option byte */
171 target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
172
173 status = stm32x_wait_status_busy(bank, 10);
174
175 if (status & FLASH_WRPRTERR)
176 return ERROR_FLASH_OPERATION_FAILED;
177 if (status & FLASH_PGERR)
178 return ERROR_FLASH_OPERATION_FAILED;
179
180 /* write protection byte 1 */
181 target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
182
183 status = stm32x_wait_status_busy(bank, 10);
184
185 if (status & FLASH_WRPRTERR)
186 return ERROR_FLASH_OPERATION_FAILED;
187 if (status & FLASH_PGERR)
188 return ERROR_FLASH_OPERATION_FAILED;
189
190 /* write protection byte 2 */
191 target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
192
193 status = stm32x_wait_status_busy(bank, 10);
194
195 if (status & FLASH_WRPRTERR)
196 return ERROR_FLASH_OPERATION_FAILED;
197 if (status & FLASH_PGERR)
198 return ERROR_FLASH_OPERATION_FAILED;
199
200 /* write protection byte 3 */
201 target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
202
203 status = stm32x_wait_status_busy(bank, 10);
204
205 if (status & FLASH_WRPRTERR)
206 return ERROR_FLASH_OPERATION_FAILED;
207 if (status & FLASH_PGERR)
208 return ERROR_FLASH_OPERATION_FAILED;
209
210 /* write protection byte 4 */
211 target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
212
213 status = stm32x_wait_status_busy(bank, 10);
214
215 if (status & FLASH_WRPRTERR)
216 return ERROR_FLASH_OPERATION_FAILED;
217 if (status & FLASH_PGERR)
218 return ERROR_FLASH_OPERATION_FAILED;
219
220 /* write readout protection bit */
221 target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
222
223 status = stm32x_wait_status_busy(bank, 10);
224
225 if (status & FLASH_WRPRTERR)
226 return ERROR_FLASH_OPERATION_FAILED;
227 if (status & FLASH_PGERR)
228 return ERROR_FLASH_OPERATION_FAILED;
229
230 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
231
232 return ERROR_OK;
233 }
234
235 static int stm32x_protect_check(struct flash_bank *bank)
236 {
237 struct target *target = bank->target;
238 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
239
240 uint32_t protection;
241 int i, s;
242 int num_bits;
243 int set;
244
245 if (target->state != TARGET_HALTED)
246 {
247 LOG_ERROR("Target not halted");
248 return ERROR_TARGET_NOT_HALTED;
249 }
250
251 /* medium density - each bit refers to a 4bank protection
252 * high density - each bit refers to a 2bank protection */
253 target_read_u32(target, STM32_FLASH_WRPR, &protection);
254
255 /* medium density - each protection bit is for 4 * 1K pages
256 * high density - each protection bit is for 2 * 2K pages */
257 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
258
259 if (stm32x_info->ppage_size == 2)
260 {
261 /* high density flash/connectivity line protection */
262
263 set = 1;
264
265 if (protection & (1 << 31))
266 set = 0;
267
268 /* bit 31 controls sector 62 - 255 protection for high density
269 * bit 31 controls sector 62 - 127 protection for connectivity line */
270 for (s = 62; s < bank->num_sectors; s++)
271 {
272 bank->sectors[s].is_protected = set;
273 }
274
275 if (bank->num_sectors > 61)
276 num_bits = 31;
277
278 for (i = 0; i < num_bits; i++)
279 {
280 set = 1;
281
282 if (protection & (1 << i))
283 set = 0;
284
285 for (s = 0; s < stm32x_info->ppage_size; s++)
286 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
287 }
288 }
289 else
290 {
291 /* low/medium density flash protection */
292 for (i = 0; i < num_bits; i++)
293 {
294 set = 1;
295
296 if (protection & (1 << i))
297 set = 0;
298
299 for (s = 0; s < stm32x_info->ppage_size; s++)
300 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
301 }
302 }
303
304 return ERROR_OK;
305 }
306
307 static int stm32x_erase(struct flash_bank *bank, int first, int last)
308 {
309 struct target *target = bank->target;
310 int i;
311 uint32_t status;
312
313 if (bank->target->state != TARGET_HALTED)
314 {
315 LOG_ERROR("Target not halted");
316 return ERROR_TARGET_NOT_HALTED;
317 }
318
319 if ((first == 0) && (last == (bank->num_sectors - 1)))
320 {
321 return stm32x_mass_erase(bank);
322 }
323
324 /* unlock flash registers */
325 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
326 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
327
328 for (i = first; i <= last; i++)
329 {
330 target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
331 target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
332 target_write_u32(target, STM32_FLASH_CR, FLASH_PER | FLASH_STRT);
333
334 status = stm32x_wait_status_busy(bank, 100);
335
336 if (status & FLASH_WRPRTERR)
337 return ERROR_FLASH_OPERATION_FAILED;
338 if (status & FLASH_PGERR)
339 return ERROR_FLASH_OPERATION_FAILED;
340 bank->sectors[i].is_erased = 1;
341 }
342
343 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
344
345 return ERROR_OK;
346 }
347
348 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
349 {
350 struct stm32x_flash_bank *stm32x_info = NULL;
351 struct target *target = bank->target;
352 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
353 int i, reg, bit;
354 int status;
355 uint32_t protection;
356
357 stm32x_info = bank->driver_priv;
358
359 if (target->state != TARGET_HALTED)
360 {
361 LOG_ERROR("Target not halted");
362 return ERROR_TARGET_NOT_HALTED;
363 }
364
365 if ((first && (first % stm32x_info->ppage_size)) || ((last + 1) &&
366 (last + 1) % stm32x_info->ppage_size))
367 {
368 LOG_WARNING("Error: start and end sectors must be on a %d sector boundary",
369 stm32x_info->ppage_size);
370 return ERROR_FLASH_SECTOR_INVALID;
371 }
372
373 /* medium density - each bit refers to a 4bank protection
374 * high density - each bit refers to a 2bank protection */
375 target_read_u32(target, STM32_FLASH_WRPR, &protection);
376
377 prot_reg[0] = (uint16_t)protection;
378 prot_reg[1] = (uint16_t)(protection >> 8);
379 prot_reg[2] = (uint16_t)(protection >> 16);
380 prot_reg[3] = (uint16_t)(protection >> 24);
381
382 if (stm32x_info->ppage_size == 2)
383 {
384 /* high density flash */
385
386 /* bit 7 controls sector 62 - 255 protection */
387 if (last > 61)
388 {
389 if (set)
390 prot_reg[3] &= ~(1 << 7);
391 else
392 prot_reg[3] |= (1 << 7);
393 }
394
395 if (first > 61)
396 first = 62;
397 if (last > 61)
398 last = 61;
399
400 for (i = first; i <= last; i++)
401 {
402 reg = (i / stm32x_info->ppage_size) / 8;
403 bit = (i / stm32x_info->ppage_size) - (reg * 8);
404
405 if (set)
406 prot_reg[reg] &= ~(1 << bit);
407 else
408 prot_reg[reg] |= (1 << bit);
409 }
410 }
411 else
412 {
413 /* medium density flash */
414 for (i = first; i <= last; i++)
415 {
416 reg = (i / stm32x_info->ppage_size) / 8;
417 bit = (i / stm32x_info->ppage_size) - (reg * 8);
418
419 if (set)
420 prot_reg[reg] &= ~(1 << bit);
421 else
422 prot_reg[reg] |= (1 << bit);
423 }
424 }
425
426 if ((status = stm32x_erase_options(bank)) != ERROR_OK)
427 return status;
428
429 stm32x_info->option_bytes.protection[0] = prot_reg[0];
430 stm32x_info->option_bytes.protection[1] = prot_reg[1];
431 stm32x_info->option_bytes.protection[2] = prot_reg[2];
432 stm32x_info->option_bytes.protection[3] = prot_reg[3];
433
434 return stm32x_write_options(bank);
435 }
436
437 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
438 uint32_t offset, uint32_t count)
439 {
440 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
441 struct target *target = bank->target;
442 uint32_t buffer_size = 16384;
443 struct working_area *source;
444 uint32_t address = bank->base + offset;
445 struct reg_param reg_params[4];
446 struct armv7m_algorithm armv7m_info;
447 int retval = ERROR_OK;
448
449 /* see contib/loaders/flash/stm32x.s for src */
450
451 static const uint8_t stm32x_flash_write_code[] = {
452 /* write: */
453 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
454 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
455 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
456 0x23, 0x60, /* str r3, [r4, #0] */
457 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
458 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
459 /* busy: */
460 0x2B, 0x68, /* ldr r3, [r5, #0] */
461 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
462 0xFB, 0xD0, /* beq busy */
463 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
464 0x01, 0xD1, /* bne exit */
465 0x01, 0x3A, /* subs r2, r2, #1 */
466 0xED, 0xD1, /* bne write */
467 /* exit: */
468 0x00, 0xBE, /* bkpt #0 */
469 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
470 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
471 };
472
473 /* flash write code */
474 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
475 &stm32x_info->write_algorithm) != ERROR_OK)
476 {
477 LOG_WARNING("no working area available, can't do block memory writes");
478 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
479 };
480
481 if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address,
482 sizeof(stm32x_flash_write_code),
483 (uint8_t*)stm32x_flash_write_code)) != ERROR_OK)
484 return retval;
485
486 /* memory buffer */
487 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
488 {
489 buffer_size /= 2;
490 if (buffer_size <= 256)
491 {
492 /* if we already allocated the writing code, but failed to get a
493 * buffer, free the algorithm */
494 if (stm32x_info->write_algorithm)
495 target_free_working_area(target, stm32x_info->write_algorithm);
496
497 LOG_WARNING("no large enough working area available, can't do block memory writes");
498 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
499 }
500 };
501
502 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
503 armv7m_info.core_mode = ARMV7M_MODE_ANY;
504
505 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
506 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
507 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
508 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
509
510 while (count > 0)
511 {
512 uint32_t thisrun_count = (count > (buffer_size / 2)) ?
513 (buffer_size / 2) : count;
514
515 if ((retval = target_write_buffer(target, source->address,
516 thisrun_count * 2, buffer)) != ERROR_OK)
517 break;
518
519 buf_set_u32(reg_params[0].value, 0, 32, source->address);
520 buf_set_u32(reg_params[1].value, 0, 32, address);
521 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
522
523 if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params,
524 stm32x_info->write_algorithm->address,
525 0,
526 10000, &armv7m_info)) != ERROR_OK)
527 {
528 LOG_ERROR("error executing stm32x flash write algorithm");
529 retval = ERROR_FLASH_OPERATION_FAILED;
530 break;
531 }
532
533 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_PGERR)
534 {
535 LOG_ERROR("flash memory not erased before writing");
536 /* Clear but report errors */
537 target_write_u32(target, STM32_FLASH_SR, FLASH_PGERR);
538 retval = ERROR_FLASH_OPERATION_FAILED;
539 break;
540 }
541
542 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_WRPRTERR)
543 {
544 LOG_ERROR("flash memory write protected");
545 /* Clear but report errors */
546 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR);
547 retval = ERROR_FLASH_OPERATION_FAILED;
548 break;
549 }
550
551 buffer += thisrun_count * 2;
552 address += thisrun_count * 2;
553 count -= thisrun_count;
554 }
555
556 target_free_working_area(target, source);
557 target_free_working_area(target, stm32x_info->write_algorithm);
558
559 destroy_reg_param(&reg_params[0]);
560 destroy_reg_param(&reg_params[1]);
561 destroy_reg_param(&reg_params[2]);
562 destroy_reg_param(&reg_params[3]);
563
564 return retval;
565 }
566
567 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
568 uint32_t offset, uint32_t count)
569 {
570 struct target *target = bank->target;
571 uint32_t words_remaining = (count / 2);
572 uint32_t bytes_remaining = (count & 0x00000001);
573 uint32_t address = bank->base + offset;
574 uint32_t bytes_written = 0;
575 uint8_t status;
576 int retval;
577
578 if (bank->target->state != TARGET_HALTED)
579 {
580 LOG_ERROR("Target not halted");
581 return ERROR_TARGET_NOT_HALTED;
582 }
583
584 if (offset & 0x1)
585 {
586 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
587 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
588 }
589
590 /* unlock flash registers */
591 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
592 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
593
594 /* multiple half words (2-byte) to be programmed? */
595 if (words_remaining > 0)
596 {
597 /* try using a block write */
598 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
599 {
600 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
601 {
602 /* if block write failed (no sufficient working area),
603 * we use normal (slow) single dword accesses */
604 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
605 }
606 else if (retval == ERROR_FLASH_OPERATION_FAILED)
607 {
608 LOG_ERROR("flash writing failed with error code: 0x%x", retval);
609 return ERROR_FLASH_OPERATION_FAILED;
610 }
611 }
612 else
613 {
614 buffer += words_remaining * 2;
615 address += words_remaining * 2;
616 words_remaining = 0;
617 }
618 }
619
620 while (words_remaining > 0)
621 {
622 uint16_t value;
623 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
624
625 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
626 target_write_u16(target, address, value);
627
628 status = stm32x_wait_status_busy(bank, 5);
629
630 if (status & FLASH_WRPRTERR)
631 {
632 LOG_ERROR("flash memory not erased before writing");
633 return ERROR_FLASH_OPERATION_FAILED;
634 }
635 if (status & FLASH_PGERR)
636 {
637 LOG_ERROR("flash memory write protected");
638 return ERROR_FLASH_OPERATION_FAILED;
639 }
640
641 bytes_written += 2;
642 words_remaining--;
643 address += 2;
644 }
645
646 if (bytes_remaining)
647 {
648 uint16_t value = 0xffff;
649 memcpy(&value, buffer + bytes_written, bytes_remaining);
650
651 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
652 target_write_u16(target, address, value);
653
654 status = stm32x_wait_status_busy(bank, 5);
655
656 if (status & FLASH_WRPRTERR)
657 {
658 LOG_ERROR("flash memory not erased before writing");
659 return ERROR_FLASH_OPERATION_FAILED;
660 }
661 if (status & FLASH_PGERR)
662 {
663 LOG_ERROR("flash memory write protected");
664 return ERROR_FLASH_OPERATION_FAILED;
665 }
666 }
667
668 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
669
670 return ERROR_OK;
671 }
672
673 static int stm32x_probe(struct flash_bank *bank)
674 {
675 struct target *target = bank->target;
676 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
677 int i;
678 uint16_t num_pages;
679 uint32_t device_id;
680 int page_size;
681
682 stm32x_info->probed = 0;
683
684 /* read stm32 device id register */
685 target_read_u32(target, 0xE0042000, &device_id);
686 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
687
688 /* get flash size from target */
689 if (target_read_u16(target, 0x1FFFF7E0, &num_pages) != ERROR_OK)
690 {
691 /* failed reading flash size, default to max target family */
692 num_pages = 0xffff;
693 }
694
695 if ((device_id & 0x7ff) == 0x410)
696 {
697 /* medium density - we have 1k pages
698 * 4 pages for a protection area */
699 page_size = 1024;
700 stm32x_info->ppage_size = 4;
701
702 /* check for early silicon */
703 if (num_pages == 0xffff)
704 {
705 /* number of sectors incorrect on revA */
706 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
707 num_pages = 128;
708 }
709 }
710 else if ((device_id & 0x7ff) == 0x412)
711 {
712 /* low density - we have 1k pages
713 * 4 pages for a protection area */
714 page_size = 1024;
715 stm32x_info->ppage_size = 4;
716
717 /* check for early silicon */
718 if (num_pages == 0xffff)
719 {
720 /* number of sectors incorrect on revA */
721 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
722 num_pages = 32;
723 }
724 }
725 else if ((device_id & 0x7ff) == 0x414)
726 {
727 /* high density - we have 2k pages
728 * 2 pages for a protection area */
729 page_size = 2048;
730 stm32x_info->ppage_size = 2;
731
732 /* check for early silicon */
733 if (num_pages == 0xffff)
734 {
735 /* number of sectors incorrect on revZ */
736 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
737 num_pages = 512;
738 }
739 }
740 else if ((device_id & 0x7ff) == 0x418)
741 {
742 /* connectivity line density - we have 2k pages
743 * 2 pages for a protection area */
744 page_size = 2048;
745 stm32x_info->ppage_size = 2;
746
747 /* check for early silicon */
748 if (num_pages == 0xffff)
749 {
750 /* number of sectors incorrect on revZ */
751 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
752 num_pages = 256;
753 }
754 }
755 else if ((device_id & 0x7ff) == 0x420)
756 {
757 /* value line density - we have 1k pages
758 * 4 pages for a protection area */
759 page_size = 1024;
760 stm32x_info->ppage_size = 4;
761
762 /* check for early silicon */
763 if (num_pages == 0xffff)
764 {
765 /* number of sectors may be incorrrect on early silicon */
766 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
767 num_pages = 128;
768 }
769 }
770 else
771 {
772 LOG_WARNING("Cannot identify target as a STM32 family.");
773 return ERROR_FLASH_OPERATION_FAILED;
774 }
775
776 LOG_INFO("flash size = %dkbytes", num_pages);
777
778 /* calculate numbers of pages */
779 num_pages /= (page_size / 1024);
780
781 if (bank->sectors)
782 {
783 free(bank->sectors);
784 bank->sectors = NULL;
785 }
786
787 bank->base = 0x08000000;
788 bank->size = (num_pages * page_size);
789 bank->num_sectors = num_pages;
790 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
791
792 for (i = 0; i < num_pages; i++)
793 {
794 bank->sectors[i].offset = i * page_size;
795 bank->sectors[i].size = page_size;
796 bank->sectors[i].is_erased = -1;
797 bank->sectors[i].is_protected = 1;
798 }
799
800 stm32x_info->probed = 1;
801
802 return ERROR_OK;
803 }
804
805 static int stm32x_auto_probe(struct flash_bank *bank)
806 {
807 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
808 if (stm32x_info->probed)
809 return ERROR_OK;
810 return stm32x_probe(bank);
811 }
812
813 #if 0
814 COMMAND_HANDLER(stm32x_handle_part_id_command)
815 {
816 return ERROR_OK;
817 }
818 #endif
819
820 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
821 {
822 struct target *target = bank->target;
823 uint32_t device_id;
824 int printed;
825
826 /* read stm32 device id register */
827 target_read_u32(target, 0xE0042000, &device_id);
828
829 if ((device_id & 0x7ff) == 0x410)
830 {
831 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
832 buf += printed;
833 buf_size -= printed;
834
835 switch (device_id >> 16)
836 {
837 case 0x0000:
838 snprintf(buf, buf_size, "A");
839 break;
840
841 case 0x2000:
842 snprintf(buf, buf_size, "B");
843 break;
844
845 case 0x2001:
846 snprintf(buf, buf_size, "Z");
847 break;
848
849 case 0x2003:
850 snprintf(buf, buf_size, "Y");
851 break;
852
853 default:
854 snprintf(buf, buf_size, "unknown");
855 break;
856 }
857 }
858 else if ((device_id & 0x7ff) == 0x412)
859 {
860 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
861 buf += printed;
862 buf_size -= printed;
863
864 switch (device_id >> 16)
865 {
866 case 0x1000:
867 snprintf(buf, buf_size, "A");
868 break;
869
870 default:
871 snprintf(buf, buf_size, "unknown");
872 break;
873 }
874 }
875 else if ((device_id & 0x7ff) == 0x414)
876 {
877 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
878 buf += printed;
879 buf_size -= printed;
880
881 switch (device_id >> 16)
882 {
883 case 0x1000:
884 snprintf(buf, buf_size, "A");
885 break;
886
887 case 0x1001:
888 snprintf(buf, buf_size, "Z");
889 break;
890
891 default:
892 snprintf(buf, buf_size, "unknown");
893 break;
894 }
895 }
896 else if ((device_id & 0x7ff) == 0x418)
897 {
898 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
899 buf += printed;
900 buf_size -= printed;
901
902 switch (device_id >> 16)
903 {
904 case 0x1000:
905 snprintf(buf, buf_size, "A");
906 break;
907
908 case 0x1001:
909 snprintf(buf, buf_size, "Z");
910 break;
911
912 default:
913 snprintf(buf, buf_size, "unknown");
914 break;
915 }
916 }
917 else if ((device_id & 0x7ff) == 0x420)
918 {
919 printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
920 buf += printed;
921 buf_size -= printed;
922
923 switch (device_id >> 16)
924 {
925 case 0x1000:
926 snprintf(buf, buf_size, "A");
927 break;
928
929 case 0x1001:
930 snprintf(buf, buf_size, "Z");
931 break;
932
933 default:
934 snprintf(buf, buf_size, "unknown");
935 break;
936 }
937 }
938 else
939 {
940 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
941 return ERROR_FLASH_OPERATION_FAILED;
942 }
943
944 return ERROR_OK;
945 }
946
947 COMMAND_HANDLER(stm32x_handle_lock_command)
948 {
949 struct target *target = NULL;
950 struct stm32x_flash_bank *stm32x_info = NULL;
951
952 if (CMD_ARGC < 1)
953 {
954 command_print(CMD_CTX, "stm32x lock <bank>");
955 return ERROR_OK;
956 }
957
958 struct flash_bank *bank;
959 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
960 if (ERROR_OK != retval)
961 return retval;
962
963 stm32x_info = bank->driver_priv;
964
965 target = bank->target;
966
967 if (target->state != TARGET_HALTED)
968 {
969 LOG_ERROR("Target not halted");
970 return ERROR_TARGET_NOT_HALTED;
971 }
972
973 if (stm32x_erase_options(bank) != ERROR_OK)
974 {
975 command_print(CMD_CTX, "stm32x failed to erase options");
976 return ERROR_OK;
977 }
978
979 /* set readout protection */
980 stm32x_info->option_bytes.RDP = 0;
981
982 if (stm32x_write_options(bank) != ERROR_OK)
983 {
984 command_print(CMD_CTX, "stm32x failed to lock device");
985 return ERROR_OK;
986 }
987
988 command_print(CMD_CTX, "stm32x locked");
989
990 return ERROR_OK;
991 }
992
993 COMMAND_HANDLER(stm32x_handle_unlock_command)
994 {
995 struct target *target = NULL;
996 struct stm32x_flash_bank *stm32x_info = NULL;
997
998 if (CMD_ARGC < 1)
999 {
1000 command_print(CMD_CTX, "stm32x unlock <bank>");
1001 return ERROR_OK;
1002 }
1003
1004 struct flash_bank *bank;
1005 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1006 if (ERROR_OK != retval)
1007 return retval;
1008
1009 stm32x_info = bank->driver_priv;
1010
1011 target = bank->target;
1012
1013 if (target->state != TARGET_HALTED)
1014 {
1015 LOG_ERROR("Target not halted");
1016 return ERROR_TARGET_NOT_HALTED;
1017 }
1018
1019 if (stm32x_erase_options(bank) != ERROR_OK)
1020 {
1021 command_print(CMD_CTX, "stm32x failed to unlock device");
1022 return ERROR_OK;
1023 }
1024
1025 if (stm32x_write_options(bank) != ERROR_OK)
1026 {
1027 command_print(CMD_CTX, "stm32x failed to lock device");
1028 return ERROR_OK;
1029 }
1030
1031 command_print(CMD_CTX, "stm32x unlocked.\n"
1032 "INFO: a reset or power cycle is required "
1033 "for the new settings to take effect.");
1034
1035 return ERROR_OK;
1036 }
1037
1038 COMMAND_HANDLER(stm32x_handle_options_read_command)
1039 {
1040 uint32_t optionbyte;
1041 struct target *target = NULL;
1042 struct stm32x_flash_bank *stm32x_info = NULL;
1043
1044 if (CMD_ARGC < 1)
1045 {
1046 command_print(CMD_CTX, "stm32x options_read <bank>");
1047 return ERROR_OK;
1048 }
1049
1050 struct flash_bank *bank;
1051 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1052 if (ERROR_OK != retval)
1053 return retval;
1054
1055 stm32x_info = bank->driver_priv;
1056
1057 target = bank->target;
1058
1059 if (target->state != TARGET_HALTED)
1060 {
1061 LOG_ERROR("Target not halted");
1062 return ERROR_TARGET_NOT_HALTED;
1063 }
1064
1065 target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
1066 command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1067
1068 if (buf_get_u32((uint8_t*)&optionbyte, OPT_ERROR, 1))
1069 command_print(CMD_CTX, "Option Byte Complement Error");
1070
1071 if (buf_get_u32((uint8_t*)&optionbyte, OPT_READOUT, 1))
1072 command_print(CMD_CTX, "Readout Protection On");
1073 else
1074 command_print(CMD_CTX, "Readout Protection Off");
1075
1076 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDWDGSW, 1))
1077 command_print(CMD_CTX, "Software Watchdog");
1078 else
1079 command_print(CMD_CTX, "Hardware Watchdog");
1080
1081 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTOP, 1))
1082 command_print(CMD_CTX, "Stop: No reset generated");
1083 else
1084 command_print(CMD_CTX, "Stop: Reset generated");
1085
1086 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTDBY, 1))
1087 command_print(CMD_CTX, "Standby: No reset generated");
1088 else
1089 command_print(CMD_CTX, "Standby: Reset generated");
1090
1091 return ERROR_OK;
1092 }
1093
1094 COMMAND_HANDLER(stm32x_handle_options_write_command)
1095 {
1096 struct target *target = NULL;
1097 struct stm32x_flash_bank *stm32x_info = NULL;
1098 uint16_t optionbyte = 0xF8;
1099
1100 if (CMD_ARGC < 4)
1101 {
1102 command_print(CMD_CTX, "stm32x options_write <bank> <SWWDG | HWWDG> <RSTSTNDBY | NORSTSTNDBY> <RSTSTOP | NORSTSTOP>");
1103 return ERROR_OK;
1104 }
1105
1106 struct flash_bank *bank;
1107 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1108 if (ERROR_OK != retval)
1109 return retval;
1110
1111 stm32x_info = bank->driver_priv;
1112
1113 target = bank->target;
1114
1115 if (target->state != TARGET_HALTED)
1116 {
1117 LOG_ERROR("Target not halted");
1118 return ERROR_TARGET_NOT_HALTED;
1119 }
1120
1121 /* REVISIT: ignores some options which we will display...
1122 * and doesn't insist on the specified syntax.
1123 */
1124
1125 /* OPT_RDWDGSW */
1126 if (strcmp(CMD_ARGV[1], "SWWDG") == 0)
1127 {
1128 optionbyte |= (1 << 0);
1129 }
1130 else /* REVISIT must be "HWWDG" then ... */
1131 {
1132 optionbyte &= ~(1 << 0);
1133 }
1134
1135 /* OPT_RDRSTSTDBY */
1136 if (strcmp(CMD_ARGV[2], "NORSTSTNDBY") == 0)
1137 {
1138 optionbyte |= (1 << 1);
1139 }
1140 else /* REVISIT must be "RSTSTNDBY" then ... */
1141 {
1142 optionbyte &= ~(1 << 1);
1143 }
1144
1145 /* OPT_RDRSTSTOP */
1146 if (strcmp(CMD_ARGV[3], "NORSTSTOP") == 0)
1147 {
1148 optionbyte |= (1 << 2);
1149 }
1150 else /* REVISIT must be "RSTSTOP" then ... */
1151 {
1152 optionbyte &= ~(1 << 2);
1153 }
1154
1155 if (stm32x_erase_options(bank) != ERROR_OK)
1156 {
1157 command_print(CMD_CTX, "stm32x failed to erase options");
1158 return ERROR_OK;
1159 }
1160
1161 stm32x_info->option_bytes.user_options = optionbyte;
1162
1163 if (stm32x_write_options(bank) != ERROR_OK)
1164 {
1165 command_print(CMD_CTX, "stm32x failed to write options");
1166 return ERROR_OK;
1167 }
1168
1169 command_print(CMD_CTX, "stm32x write options complete.\n"
1170 "INFO: a reset or power cycle is required "
1171 "for the new settings to take effect.");
1172
1173 return ERROR_OK;
1174 }
1175
1176 static int stm32x_mass_erase(struct flash_bank *bank)
1177 {
1178 struct target *target = bank->target;
1179 uint32_t status;
1180
1181 if (target->state != TARGET_HALTED)
1182 {
1183 LOG_ERROR("Target not halted");
1184 return ERROR_TARGET_NOT_HALTED;
1185 }
1186
1187 /* unlock option flash registers */
1188 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
1189 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
1190
1191 /* mass erase flash memory */
1192 target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
1193 target_write_u32(target, STM32_FLASH_CR, FLASH_MER | FLASH_STRT);
1194
1195 status = stm32x_wait_status_busy(bank, 100);
1196
1197 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
1198
1199 if (status & FLASH_WRPRTERR)
1200 {
1201 LOG_ERROR("stm32x device protected");
1202 return ERROR_FLASH_OPERATION_FAILED;
1203 }
1204
1205 if (status & FLASH_PGERR)
1206 {
1207 LOG_ERROR("stm32x device programming failed");
1208 return ERROR_FLASH_OPERATION_FAILED;
1209 }
1210
1211 return ERROR_OK;
1212 }
1213
1214 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1215 {
1216 int i;
1217
1218 if (CMD_ARGC < 1)
1219 {
1220 command_print(CMD_CTX, "stm32x mass_erase <bank>");
1221 return ERROR_OK;
1222 }
1223
1224 struct flash_bank *bank;
1225 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1226 if (ERROR_OK != retval)
1227 return retval;
1228
1229 retval = stm32x_mass_erase(bank);
1230 if (retval == ERROR_OK)
1231 {
1232 /* set all sectors as erased */
1233 for (i = 0; i < bank->num_sectors; i++)
1234 {
1235 bank->sectors[i].is_erased = 1;
1236 }
1237
1238 command_print(CMD_CTX, "stm32x mass erase complete");
1239 }
1240 else
1241 {
1242 command_print(CMD_CTX, "stm32x mass erase failed");
1243 }
1244
1245 return retval;
1246 }
1247
1248 static const struct command_registration stm32x_exec_command_handlers[] = {
1249 {
1250 .name = "lock",
1251 .handler = stm32x_handle_lock_command,
1252 .mode = COMMAND_EXEC,
1253 .usage = "bank_id",
1254 .help = "Lock entire flash device.",
1255 },
1256 {
1257 .name = "unlock",
1258 .handler = stm32x_handle_unlock_command,
1259 .mode = COMMAND_EXEC,
1260 .usage = "bank_id",
1261 .help = "Unlock entire protected flash device.",
1262 },
1263 {
1264 .name = "mass_erase",
1265 .handler = stm32x_handle_mass_erase_command,
1266 .mode = COMMAND_EXEC,
1267 .usage = "bank_id",
1268 .help = "Erase entire flash device.",
1269 },
1270 {
1271 .name = "options_read",
1272 .handler = stm32x_handle_options_read_command,
1273 .mode = COMMAND_EXEC,
1274 .usage = "bank_id",
1275 .help = "Read and display device option byte.",
1276 },
1277 {
1278 .name = "options_write",
1279 .handler = stm32x_handle_options_write_command,
1280 .mode = COMMAND_EXEC,
1281 .usage = "bank_id ('SWWDG'|'HWWDG') "
1282 "('RSTSTNDBY'|'NORSTSTNDBY') "
1283 "('RSTSTOP'|'NORSTSTOP')",
1284 .help = "Replace bits in device option byte.",
1285 },
1286 COMMAND_REGISTRATION_DONE
1287 };
1288
1289 static const struct command_registration stm32x_command_handlers[] = {
1290 {
1291 .name = "stm32x",
1292 .mode = COMMAND_ANY,
1293 .help = "stm32x flash command group",
1294 .chain = stm32x_exec_command_handlers,
1295 },
1296 COMMAND_REGISTRATION_DONE
1297 };
1298
1299 struct flash_driver stm32x_flash = {
1300 .name = "stm32x",
1301 .commands = stm32x_command_handlers,
1302 .flash_bank_command = stm32x_flash_bank_command,
1303 .erase = stm32x_erase,
1304 .protect = stm32x_protect,
1305 .write = stm32x_write,
1306 .read = default_flash_read,
1307 .probe = stm32x_probe,
1308 .auto_probe = stm32x_auto_probe,
1309 .erase_check = default_flash_mem_blank_check,
1310 .protect_check = stm32x_protect_check,
1311 .info = get_stm32x_info,
1312 };
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