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6b46afc8d543bdfefe10b9365d12b441a1cba343
[openocd.git] / src / flash / nor / stm32x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "imp.h"
28 #include "stm32x.h"
29 #include <helper/binarybuffer.h>
30 #include <target/algorithm.h>
31 #include <target/armv7m.h>
32
33
34 static int stm32x_mass_erase(struct flash_bank *bank);
35
36 /* flash bank stm32x <base> <size> 0 0 <target#>
37 */
38 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
39 {
40 struct stm32x_flash_bank *stm32x_info;
41
42 if (CMD_ARGC < 6)
43 {
44 LOG_WARNING("incomplete flash_bank stm32x configuration");
45 return ERROR_FLASH_BANK_INVALID;
46 }
47
48 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
49 bank->driver_priv = stm32x_info;
50
51 stm32x_info->write_algorithm = NULL;
52 stm32x_info->probed = 0;
53
54 return ERROR_OK;
55 }
56
57 static int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
58 {
59 struct target *target = bank->target;
60 return target_read_u32(target, STM32_FLASH_SR, status);
61 }
62
63 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
64 {
65 struct target *target = bank->target;
66 uint32_t status;
67 int retval = ERROR_OK;
68
69 /* wait for busy to clear */
70 for (;;)
71 {
72 retval = stm32x_get_flash_status(bank, &status);
73 if (retval != ERROR_OK)
74 return retval;
75 LOG_DEBUG("status: 0x%" PRIx32 "", status);
76 if ((status & FLASH_BSY) == 0)
77 break;
78 if (timeout-- <= 0)
79 {
80 LOG_ERROR("timed out waiting for flash");
81 return ERROR_FAIL;
82 }
83 alive_sleep(1);
84 }
85
86 if (status & FLASH_WRPRTERR)
87 {
88 LOG_ERROR("stm32x device protected");
89 retval = ERROR_FAIL;
90 }
91
92 if (status & FLASH_PGERR)
93 {
94 LOG_ERROR("stm32x device programming failed");
95 retval = ERROR_FAIL;
96 }
97
98 /* Clear but report errors */
99 if (status & (FLASH_WRPRTERR | FLASH_PGERR))
100 {
101 /* If this operation fails, we ignore it and report the original
102 * retval
103 */
104 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR | FLASH_PGERR);
105 }
106 return retval;
107 }
108
109 static int stm32x_read_options(struct flash_bank *bank)
110 {
111 uint32_t optiondata;
112 struct stm32x_flash_bank *stm32x_info = NULL;
113 struct target *target = bank->target;
114
115 stm32x_info = bank->driver_priv;
116
117 /* read current option bytes */
118 int retval = target_read_u32(target, STM32_FLASH_OBR, &optiondata);
119 if (retval != ERROR_OK)
120 return retval;
121
122 stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
123 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
124
125 if (optiondata & (1 << OPT_READOUT))
126 LOG_INFO("Device Security Bit Set");
127
128 /* each bit refers to a 4bank protection */
129 retval = target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
130 if (retval != ERROR_OK)
131 return retval;
132
133 stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
134 stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
135 stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
136 stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
137
138 return ERROR_OK;
139 }
140
141 static int stm32x_erase_options(struct flash_bank *bank)
142 {
143 struct stm32x_flash_bank *stm32x_info = NULL;
144 struct target *target = bank->target;
145
146 stm32x_info = bank->driver_priv;
147
148 /* read current options */
149 stm32x_read_options(bank);
150
151 /* unlock flash registers */
152 int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
153 if (retval != ERROR_OK)
154 return retval;
155
156 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
157 if (retval != ERROR_OK)
158 return retval;
159
160 /* unlock option flash registers */
161 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
162 if (retval != ERROR_OK)
163 return retval;
164 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
165 if (retval != ERROR_OK)
166 return retval;
167
168 /* erase option bytes */
169 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_OPTWRE);
170 if (retval != ERROR_OK)
171 return retval;
172 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
173 if (retval != ERROR_OK)
174 return retval;
175
176 retval = stm32x_wait_status_busy(bank, 10);
177 if (retval != ERROR_OK)
178 return retval;
179
180 /* clear readout protection and complementary option bytes
181 * this will also force a device unlock if set */
182 stm32x_info->option_bytes.RDP = 0x5AA5;
183
184 return ERROR_OK;
185 }
186
187 static int stm32x_write_options(struct flash_bank *bank)
188 {
189 struct stm32x_flash_bank *stm32x_info = NULL;
190 struct target *target = bank->target;
191
192 stm32x_info = bank->driver_priv;
193
194 /* unlock flash registers */
195 int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
196 if (retval != ERROR_OK)
197 return retval;
198 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
199 if (retval != ERROR_OK)
200 return retval;
201
202 /* unlock option flash registers */
203 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
204 if (retval != ERROR_OK)
205 return retval;
206 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
207 if (retval != ERROR_OK)
208 return retval;
209
210 /* program option bytes */
211 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG | FLASH_OPTWRE);
212 if (retval != ERROR_OK)
213 return retval;
214
215 /* write user option byte */
216 retval = target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
217 if (retval != ERROR_OK)
218 return retval;
219
220 retval = stm32x_wait_status_busy(bank, 10);
221 if (retval != ERROR_OK)
222 return retval;
223
224 /* write protection byte 1 */
225 retval = target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
226 if (retval != ERROR_OK)
227 return retval;
228
229 retval = stm32x_wait_status_busy(bank, 10);
230 if (retval != ERROR_OK)
231 return retval;
232
233 /* write protection byte 2 */
234 retval = target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
235 if (retval != ERROR_OK)
236 return retval;
237
238 retval = stm32x_wait_status_busy(bank, 10);
239 if (retval != ERROR_OK)
240 return retval;
241
242 /* write protection byte 3 */
243 retval = target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
244 if (retval != ERROR_OK)
245 return retval;
246
247 retval = stm32x_wait_status_busy(bank, 10);
248 if (retval != ERROR_OK)
249 return retval;
250
251 /* write protection byte 4 */
252 retval = target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
253 if (retval != ERROR_OK)
254 return retval;
255
256 retval = stm32x_wait_status_busy(bank, 10);
257 if (retval != ERROR_OK)
258 return retval;
259
260 /* write readout protection bit */
261 retval = target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
262 if (retval != ERROR_OK)
263 return retval;
264
265 retval = stm32x_wait_status_busy(bank, 10);
266 if (retval != ERROR_OK)
267 return retval;
268
269 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
270 if (retval != ERROR_OK)
271 return retval;
272
273 return ERROR_OK;
274 }
275
276 static int stm32x_protect_check(struct flash_bank *bank)
277 {
278 struct target *target = bank->target;
279 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
280
281 uint32_t protection;
282 int i, s;
283 int num_bits;
284 int set;
285
286 if (target->state != TARGET_HALTED)
287 {
288 LOG_ERROR("Target not halted");
289 return ERROR_TARGET_NOT_HALTED;
290 }
291
292 /* medium density - each bit refers to a 4bank protection
293 * high density - each bit refers to a 2bank protection */
294 int retval = target_read_u32(target, STM32_FLASH_WRPR, &protection);
295 if (retval != ERROR_OK)
296 return retval;
297
298 /* medium density - each protection bit is for 4 * 1K pages
299 * high density - each protection bit is for 2 * 2K pages */
300 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
301
302 if (stm32x_info->ppage_size == 2)
303 {
304 /* high density flash/connectivity line protection */
305
306 set = 1;
307
308 if (protection & (1 << 31))
309 set = 0;
310
311 /* bit 31 controls sector 62 - 255 protection for high density
312 * bit 31 controls sector 62 - 127 protection for connectivity line */
313 for (s = 62; s < bank->num_sectors; s++)
314 {
315 bank->sectors[s].is_protected = set;
316 }
317
318 if (bank->num_sectors > 61)
319 num_bits = 31;
320
321 for (i = 0; i < num_bits; i++)
322 {
323 set = 1;
324
325 if (protection & (1 << i))
326 set = 0;
327
328 for (s = 0; s < stm32x_info->ppage_size; s++)
329 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
330 }
331 }
332 else
333 {
334 /* low/medium density flash protection */
335 for (i = 0; i < num_bits; i++)
336 {
337 set = 1;
338
339 if (protection & (1 << i))
340 set = 0;
341
342 for (s = 0; s < stm32x_info->ppage_size; s++)
343 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
344 }
345 }
346
347 return ERROR_OK;
348 }
349
350 static int stm32x_erase(struct flash_bank *bank, int first, int last)
351 {
352 struct target *target = bank->target;
353 int i;
354
355 if (bank->target->state != TARGET_HALTED)
356 {
357 LOG_ERROR("Target not halted");
358 return ERROR_TARGET_NOT_HALTED;
359 }
360
361 if ((first == 0) && (last == (bank->num_sectors - 1)))
362 {
363 return stm32x_mass_erase(bank);
364 }
365
366 /* unlock flash registers */
367 int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
368 if (retval != ERROR_OK)
369 return retval;
370 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
371 if (retval != ERROR_OK)
372 return retval;
373
374 for (i = first; i <= last; i++)
375 {
376 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
377 if (retval != ERROR_OK)
378 return retval;
379 retval = target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
380 if (retval != ERROR_OK)
381 return retval;
382 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PER | FLASH_STRT);
383 if (retval != ERROR_OK)
384 return retval;
385
386 retval = stm32x_wait_status_busy(bank, 100);
387 if (retval != ERROR_OK)
388 return retval;
389
390 bank->sectors[i].is_erased = 1;
391 }
392
393 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
394 if (retval != ERROR_OK)
395 return retval;
396
397 return ERROR_OK;
398 }
399
400 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
401 {
402 struct stm32x_flash_bank *stm32x_info = NULL;
403 struct target *target = bank->target;
404 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
405 int i, reg, bit;
406 int status;
407 uint32_t protection;
408
409 stm32x_info = bank->driver_priv;
410
411 if (target->state != TARGET_HALTED)
412 {
413 LOG_ERROR("Target not halted");
414 return ERROR_TARGET_NOT_HALTED;
415 }
416
417 if ((first && (first % stm32x_info->ppage_size)) || ((last + 1) &&
418 (last + 1) % stm32x_info->ppage_size))
419 {
420 LOG_WARNING("Error: start and end sectors must be on a %d sector boundary",
421 stm32x_info->ppage_size);
422 return ERROR_FLASH_SECTOR_INVALID;
423 }
424
425 /* medium density - each bit refers to a 4bank protection
426 * high density - each bit refers to a 2bank protection */
427 int retval = target_read_u32(target, STM32_FLASH_WRPR, &protection);
428 if (retval != ERROR_OK)
429 return retval;
430
431 prot_reg[0] = (uint16_t)protection;
432 prot_reg[1] = (uint16_t)(protection >> 8);
433 prot_reg[2] = (uint16_t)(protection >> 16);
434 prot_reg[3] = (uint16_t)(protection >> 24);
435
436 if (stm32x_info->ppage_size == 2)
437 {
438 /* high density flash */
439
440 /* bit 7 controls sector 62 - 255 protection */
441 if (last > 61)
442 {
443 if (set)
444 prot_reg[3] &= ~(1 << 7);
445 else
446 prot_reg[3] |= (1 << 7);
447 }
448
449 if (first > 61)
450 first = 62;
451 if (last > 61)
452 last = 61;
453
454 for (i = first; i <= last; i++)
455 {
456 reg = (i / stm32x_info->ppage_size) / 8;
457 bit = (i / stm32x_info->ppage_size) - (reg * 8);
458
459 if (set)
460 prot_reg[reg] &= ~(1 << bit);
461 else
462 prot_reg[reg] |= (1 << bit);
463 }
464 }
465 else
466 {
467 /* medium density flash */
468 for (i = first; i <= last; i++)
469 {
470 reg = (i / stm32x_info->ppage_size) / 8;
471 bit = (i / stm32x_info->ppage_size) - (reg * 8);
472
473 if (set)
474 prot_reg[reg] &= ~(1 << bit);
475 else
476 prot_reg[reg] |= (1 << bit);
477 }
478 }
479
480 if ((status = stm32x_erase_options(bank)) != ERROR_OK)
481 return status;
482
483 stm32x_info->option_bytes.protection[0] = prot_reg[0];
484 stm32x_info->option_bytes.protection[1] = prot_reg[1];
485 stm32x_info->option_bytes.protection[2] = prot_reg[2];
486 stm32x_info->option_bytes.protection[3] = prot_reg[3];
487
488 return stm32x_write_options(bank);
489 }
490
491 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
492 uint32_t offset, uint32_t count)
493 {
494 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
495 struct target *target = bank->target;
496 uint32_t buffer_size = 16384;
497 struct working_area *source;
498 uint32_t address = bank->base + offset;
499 struct reg_param reg_params[4];
500 struct armv7m_algorithm armv7m_info;
501 int retval = ERROR_OK;
502
503 /* see contib/loaders/flash/stm32x.s for src */
504
505 static const uint8_t stm32x_flash_write_code[] = {
506 /* write: */
507 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
508 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
509 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
510 0x23, 0x60, /* str r3, [r4, #0] */
511 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
512 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
513 /* busy: */
514 0x2B, 0x68, /* ldr r3, [r5, #0] */
515 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
516 0xFB, 0xD0, /* beq busy */
517 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
518 0x01, 0xD1, /* bne exit */
519 0x01, 0x3A, /* subs r2, r2, #1 */
520 0xED, 0xD1, /* bne write */
521 /* exit: */
522 0x00, 0xBE, /* bkpt #0 */
523 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
524 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
525 };
526
527 /* flash write code */
528 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
529 &stm32x_info->write_algorithm) != ERROR_OK)
530 {
531 LOG_WARNING("no working area available, can't do block memory writes");
532 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
533 };
534
535 if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address,
536 sizeof(stm32x_flash_write_code),
537 (uint8_t*)stm32x_flash_write_code)) != ERROR_OK)
538 return retval;
539
540 /* memory buffer */
541 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
542 {
543 buffer_size /= 2;
544 if (buffer_size <= 256)
545 {
546 /* if we already allocated the writing code, but failed to get a
547 * buffer, free the algorithm */
548 if (stm32x_info->write_algorithm)
549 target_free_working_area(target, stm32x_info->write_algorithm);
550
551 LOG_WARNING("no large enough working area available, can't do block memory writes");
552 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
553 }
554 };
555
556 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
557 armv7m_info.core_mode = ARMV7M_MODE_ANY;
558
559 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
560 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
561 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
562 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
563
564 while (count > 0)
565 {
566 uint32_t thisrun_count = (count > (buffer_size / 2)) ?
567 (buffer_size / 2) : count;
568
569 if ((retval = target_write_buffer(target, source->address,
570 thisrun_count * 2, buffer)) != ERROR_OK)
571 break;
572
573 buf_set_u32(reg_params[0].value, 0, 32, source->address);
574 buf_set_u32(reg_params[1].value, 0, 32, address);
575 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
576
577 if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params,
578 stm32x_info->write_algorithm->address,
579 0,
580 10000, &armv7m_info)) != ERROR_OK)
581 {
582 LOG_ERROR("error executing stm32x flash write algorithm");
583 break;
584 }
585
586 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_PGERR)
587 {
588 LOG_ERROR("flash memory not erased before writing");
589 /* Clear but report errors */
590 target_write_u32(target, STM32_FLASH_SR, FLASH_PGERR);
591 retval = ERROR_FAIL;
592 break;
593 }
594
595 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_WRPRTERR)
596 {
597 LOG_ERROR("flash memory write protected");
598 /* Clear but report errors */
599 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR);
600 retval = ERROR_FAIL;
601 break;
602 }
603
604 buffer += thisrun_count * 2;
605 address += thisrun_count * 2;
606 count -= thisrun_count;
607 }
608
609 target_free_working_area(target, source);
610 target_free_working_area(target, stm32x_info->write_algorithm);
611
612 destroy_reg_param(&reg_params[0]);
613 destroy_reg_param(&reg_params[1]);
614 destroy_reg_param(&reg_params[2]);
615 destroy_reg_param(&reg_params[3]);
616
617 return retval;
618 }
619
620 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
621 uint32_t offset, uint32_t count)
622 {
623 struct target *target = bank->target;
624 uint32_t words_remaining = (count / 2);
625 uint32_t bytes_remaining = (count & 0x00000001);
626 uint32_t address = bank->base + offset;
627 uint32_t bytes_written = 0;
628 int retval;
629
630 if (bank->target->state != TARGET_HALTED)
631 {
632 LOG_ERROR("Target not halted");
633 return ERROR_TARGET_NOT_HALTED;
634 }
635
636 if (offset & 0x1)
637 {
638 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
639 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
640 }
641
642 /* unlock flash registers */
643 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
644 if (retval != ERROR_OK)
645 return retval;
646 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
647 if (retval != ERROR_OK)
648 return retval;
649
650 /* multiple half words (2-byte) to be programmed? */
651 if (words_remaining > 0)
652 {
653 /* try using a block write */
654 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
655 {
656 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
657 {
658 /* if block write failed (no sufficient working area),
659 * we use normal (slow) single dword accesses */
660 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
661 }
662 }
663 else
664 {
665 buffer += words_remaining * 2;
666 address += words_remaining * 2;
667 words_remaining = 0;
668 }
669 }
670
671 if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
672 return retval;
673
674 while (words_remaining > 0)
675 {
676 uint16_t value;
677 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
678
679 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
680 if (retval != ERROR_OK)
681 return retval;
682 retval = target_write_u16(target, address, value);
683 if (retval != ERROR_OK)
684 return retval;
685
686 retval = stm32x_wait_status_busy(bank, 5);
687 if (retval != ERROR_OK)
688 return retval;
689
690 bytes_written += 2;
691 words_remaining--;
692 address += 2;
693 }
694
695 if (bytes_remaining)
696 {
697 uint16_t value = 0xffff;
698 memcpy(&value, buffer + bytes_written, bytes_remaining);
699
700 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
701 if (retval != ERROR_OK)
702 return retval;
703 retval = target_write_u16(target, address, value);
704 if (retval != ERROR_OK)
705 return retval;
706
707 retval = stm32x_wait_status_busy(bank, 5);
708 if (retval != ERROR_OK)
709 return retval;
710 }
711
712 return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
713 }
714
715 static int stm32x_probe(struct flash_bank *bank)
716 {
717 struct target *target = bank->target;
718 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
719 int i;
720 uint16_t num_pages;
721 uint32_t device_id;
722 int page_size;
723
724 stm32x_info->probed = 0;
725
726 /* read stm32 device id register */
727 int retval = target_read_u32(target, 0xE0042000, &device_id);
728 if (retval != ERROR_OK)
729 return retval;
730 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
731
732 /* get flash size from target. */
733 retval = target_read_u16(target, 0x1FFFF7E0, &num_pages);
734 if (retval != ERROR_OK)
735 {
736 LOG_WARNING("failed reading flash size, default to max target family");
737 /* failed reading flash size, default to max target family */
738 num_pages = 0xffff;
739 }
740
741 if ((device_id & 0x7ff) == 0x410)
742 {
743 /* medium density - we have 1k pages
744 * 4 pages for a protection area */
745 page_size = 1024;
746 stm32x_info->ppage_size = 4;
747
748 /* check for early silicon */
749 if (num_pages == 0xffff)
750 {
751 /* number of sectors incorrect on revA */
752 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
753 num_pages = 128;
754 }
755 }
756 else if ((device_id & 0x7ff) == 0x412)
757 {
758 /* low density - we have 1k pages
759 * 4 pages for a protection area */
760 page_size = 1024;
761 stm32x_info->ppage_size = 4;
762
763 /* check for early silicon */
764 if (num_pages == 0xffff)
765 {
766 /* number of sectors incorrect on revA */
767 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
768 num_pages = 32;
769 }
770 }
771 else if ((device_id & 0x7ff) == 0x414)
772 {
773 /* high density - we have 2k pages
774 * 2 pages for a protection area */
775 page_size = 2048;
776 stm32x_info->ppage_size = 2;
777
778 /* check for early silicon */
779 if (num_pages == 0xffff)
780 {
781 /* number of sectors incorrect on revZ */
782 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
783 num_pages = 512;
784 }
785 }
786 else if ((device_id & 0x7ff) == 0x418)
787 {
788 /* connectivity line density - we have 2k pages
789 * 2 pages for a protection area */
790 page_size = 2048;
791 stm32x_info->ppage_size = 2;
792
793 /* check for early silicon */
794 if (num_pages == 0xffff)
795 {
796 /* number of sectors incorrect on revZ */
797 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
798 num_pages = 256;
799 }
800 }
801 else if ((device_id & 0x7ff) == 0x420)
802 {
803 /* value line density - we have 1k pages
804 * 4 pages for a protection area */
805 page_size = 1024;
806 stm32x_info->ppage_size = 4;
807
808 /* check for early silicon */
809 if (num_pages == 0xffff)
810 {
811 /* number of sectors may be incorrrect on early silicon */
812 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
813 num_pages = 128;
814 }
815 }
816 else
817 {
818 LOG_WARNING("Cannot identify target as a STM32 family.");
819 return ERROR_FAIL;
820 }
821
822 LOG_INFO("flash size = %dkbytes", num_pages);
823
824 /* calculate numbers of pages */
825 num_pages /= (page_size / 1024);
826
827 if (bank->sectors)
828 {
829 free(bank->sectors);
830 bank->sectors = NULL;
831 }
832
833 bank->base = 0x08000000;
834 bank->size = (num_pages * page_size);
835 bank->num_sectors = num_pages;
836 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
837
838 for (i = 0; i < num_pages; i++)
839 {
840 bank->sectors[i].offset = i * page_size;
841 bank->sectors[i].size = page_size;
842 bank->sectors[i].is_erased = -1;
843 bank->sectors[i].is_protected = 1;
844 }
845
846 stm32x_info->probed = 1;
847
848 return ERROR_OK;
849 }
850
851 static int stm32x_auto_probe(struct flash_bank *bank)
852 {
853 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
854 if (stm32x_info->probed)
855 return ERROR_OK;
856 return stm32x_probe(bank);
857 }
858
859 #if 0
860 COMMAND_HANDLER(stm32x_handle_part_id_command)
861 {
862 return ERROR_OK;
863 }
864 #endif
865
866 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
867 {
868 struct target *target = bank->target;
869 uint32_t device_id;
870 int printed;
871
872 /* read stm32 device id register */
873 int retval = target_read_u32(target, 0xE0042000, &device_id);
874 if (retval != ERROR_OK)
875 return retval;
876
877 if ((device_id & 0x7ff) == 0x410)
878 {
879 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
880 buf += printed;
881 buf_size -= printed;
882
883 switch (device_id >> 16)
884 {
885 case 0x0000:
886 snprintf(buf, buf_size, "A");
887 break;
888
889 case 0x2000:
890 snprintf(buf, buf_size, "B");
891 break;
892
893 case 0x2001:
894 snprintf(buf, buf_size, "Z");
895 break;
896
897 case 0x2003:
898 snprintf(buf, buf_size, "Y");
899 break;
900
901 default:
902 snprintf(buf, buf_size, "unknown");
903 break;
904 }
905 }
906 else if ((device_id & 0x7ff) == 0x412)
907 {
908 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
909 buf += printed;
910 buf_size -= printed;
911
912 switch (device_id >> 16)
913 {
914 case 0x1000:
915 snprintf(buf, buf_size, "A");
916 break;
917
918 default:
919 snprintf(buf, buf_size, "unknown");
920 break;
921 }
922 }
923 else if ((device_id & 0x7ff) == 0x414)
924 {
925 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
926 buf += printed;
927 buf_size -= printed;
928
929 switch (device_id >> 16)
930 {
931 case 0x1000:
932 snprintf(buf, buf_size, "A");
933 break;
934
935 case 0x1001:
936 snprintf(buf, buf_size, "Z");
937 break;
938
939 default:
940 snprintf(buf, buf_size, "unknown");
941 break;
942 }
943 }
944 else if ((device_id & 0x7ff) == 0x418)
945 {
946 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
947 buf += printed;
948 buf_size -= printed;
949
950 switch (device_id >> 16)
951 {
952 case 0x1000:
953 snprintf(buf, buf_size, "A");
954 break;
955
956 case 0x1001:
957 snprintf(buf, buf_size, "Z");
958 break;
959
960 default:
961 snprintf(buf, buf_size, "unknown");
962 break;
963 }
964 }
965 else if ((device_id & 0x7ff) == 0x420)
966 {
967 printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
968 buf += printed;
969 buf_size -= printed;
970
971 switch (device_id >> 16)
972 {
973 case 0x1000:
974 snprintf(buf, buf_size, "A");
975 break;
976
977 case 0x1001:
978 snprintf(buf, buf_size, "Z");
979 break;
980
981 default:
982 snprintf(buf, buf_size, "unknown");
983 break;
984 }
985 }
986 else
987 {
988 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
989 return ERROR_FAIL;
990 }
991
992 return ERROR_OK;
993 }
994
995 COMMAND_HANDLER(stm32x_handle_lock_command)
996 {
997 struct target *target = NULL;
998 struct stm32x_flash_bank *stm32x_info = NULL;
999
1000 if (CMD_ARGC < 1)
1001 {
1002 command_print(CMD_CTX, "stm32x lock <bank>");
1003 return ERROR_OK;
1004 }
1005
1006 struct flash_bank *bank;
1007 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1008 if (ERROR_OK != retval)
1009 return retval;
1010
1011 stm32x_info = bank->driver_priv;
1012
1013 target = bank->target;
1014
1015 if (target->state != TARGET_HALTED)
1016 {
1017 LOG_ERROR("Target not halted");
1018 return ERROR_TARGET_NOT_HALTED;
1019 }
1020
1021 if (stm32x_erase_options(bank) != ERROR_OK)
1022 {
1023 command_print(CMD_CTX, "stm32x failed to erase options");
1024 return ERROR_OK;
1025 }
1026
1027 /* set readout protection */
1028 stm32x_info->option_bytes.RDP = 0;
1029
1030 if (stm32x_write_options(bank) != ERROR_OK)
1031 {
1032 command_print(CMD_CTX, "stm32x failed to lock device");
1033 return ERROR_OK;
1034 }
1035
1036 command_print(CMD_CTX, "stm32x locked");
1037
1038 return ERROR_OK;
1039 }
1040
1041 COMMAND_HANDLER(stm32x_handle_unlock_command)
1042 {
1043 struct target *target = NULL;
1044 struct stm32x_flash_bank *stm32x_info = NULL;
1045
1046 if (CMD_ARGC < 1)
1047 {
1048 command_print(CMD_CTX, "stm32x unlock <bank>");
1049 return ERROR_OK;
1050 }
1051
1052 struct flash_bank *bank;
1053 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1054 if (ERROR_OK != retval)
1055 return retval;
1056
1057 stm32x_info = bank->driver_priv;
1058
1059 target = bank->target;
1060
1061 if (target->state != TARGET_HALTED)
1062 {
1063 LOG_ERROR("Target not halted");
1064 return ERROR_TARGET_NOT_HALTED;
1065 }
1066
1067 if (stm32x_erase_options(bank) != ERROR_OK)
1068 {
1069 command_print(CMD_CTX, "stm32x failed to unlock device");
1070 return ERROR_OK;
1071 }
1072
1073 if (stm32x_write_options(bank) != ERROR_OK)
1074 {
1075 command_print(CMD_CTX, "stm32x failed to lock device");
1076 return ERROR_OK;
1077 }
1078
1079 command_print(CMD_CTX, "stm32x unlocked.\n"
1080 "INFO: a reset or power cycle is required "
1081 "for the new settings to take effect.");
1082
1083 return ERROR_OK;
1084 }
1085
1086 COMMAND_HANDLER(stm32x_handle_options_read_command)
1087 {
1088 uint32_t optionbyte;
1089 struct target *target = NULL;
1090 struct stm32x_flash_bank *stm32x_info = NULL;
1091
1092 if (CMD_ARGC < 1)
1093 {
1094 command_print(CMD_CTX, "stm32x options_read <bank>");
1095 return ERROR_OK;
1096 }
1097
1098 struct flash_bank *bank;
1099 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1100 if (ERROR_OK != retval)
1101 return retval;
1102
1103 stm32x_info = bank->driver_priv;
1104
1105 target = bank->target;
1106
1107 if (target->state != TARGET_HALTED)
1108 {
1109 LOG_ERROR("Target not halted");
1110 return ERROR_TARGET_NOT_HALTED;
1111 }
1112
1113 retval = target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
1114 if (retval != ERROR_OK)
1115 return retval;
1116 command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1117
1118 if (buf_get_u32((uint8_t*)&optionbyte, OPT_ERROR, 1))
1119 command_print(CMD_CTX, "Option Byte Complement Error");
1120
1121 if (buf_get_u32((uint8_t*)&optionbyte, OPT_READOUT, 1))
1122 command_print(CMD_CTX, "Readout Protection On");
1123 else
1124 command_print(CMD_CTX, "Readout Protection Off");
1125
1126 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDWDGSW, 1))
1127 command_print(CMD_CTX, "Software Watchdog");
1128 else
1129 command_print(CMD_CTX, "Hardware Watchdog");
1130
1131 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTOP, 1))
1132 command_print(CMD_CTX, "Stop: No reset generated");
1133 else
1134 command_print(CMD_CTX, "Stop: Reset generated");
1135
1136 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTDBY, 1))
1137 command_print(CMD_CTX, "Standby: No reset generated");
1138 else
1139 command_print(CMD_CTX, "Standby: Reset generated");
1140
1141 return ERROR_OK;
1142 }
1143
1144 COMMAND_HANDLER(stm32x_handle_options_write_command)
1145 {
1146 struct target *target = NULL;
1147 struct stm32x_flash_bank *stm32x_info = NULL;
1148 uint16_t optionbyte = 0xF8;
1149
1150 if (CMD_ARGC < 4)
1151 {
1152 command_print(CMD_CTX, "stm32x options_write <bank> <SWWDG | HWWDG> <RSTSTNDBY | NORSTSTNDBY> <RSTSTOP | NORSTSTOP>");
1153 return ERROR_OK;
1154 }
1155
1156 struct flash_bank *bank;
1157 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1158 if (ERROR_OK != retval)
1159 return retval;
1160
1161 stm32x_info = bank->driver_priv;
1162
1163 target = bank->target;
1164
1165 if (target->state != TARGET_HALTED)
1166 {
1167 LOG_ERROR("Target not halted");
1168 return ERROR_TARGET_NOT_HALTED;
1169 }
1170
1171 /* REVISIT: ignores some options which we will display...
1172 * and doesn't insist on the specified syntax.
1173 */
1174
1175 /* OPT_RDWDGSW */
1176 if (strcmp(CMD_ARGV[1], "SWWDG") == 0)
1177 {
1178 optionbyte |= (1 << 0);
1179 }
1180 else /* REVISIT must be "HWWDG" then ... */
1181 {
1182 optionbyte &= ~(1 << 0);
1183 }
1184
1185 /* OPT_RDRSTSTDBY */
1186 if (strcmp(CMD_ARGV[2], "NORSTSTNDBY") == 0)
1187 {
1188 optionbyte |= (1 << 1);
1189 }
1190 else /* REVISIT must be "RSTSTNDBY" then ... */
1191 {
1192 optionbyte &= ~(1 << 1);
1193 }
1194
1195 /* OPT_RDRSTSTOP */
1196 if (strcmp(CMD_ARGV[3], "NORSTSTOP") == 0)
1197 {
1198 optionbyte |= (1 << 2);
1199 }
1200 else /* REVISIT must be "RSTSTOP" then ... */
1201 {
1202 optionbyte &= ~(1 << 2);
1203 }
1204
1205 if (stm32x_erase_options(bank) != ERROR_OK)
1206 {
1207 command_print(CMD_CTX, "stm32x failed to erase options");
1208 return ERROR_OK;
1209 }
1210
1211 stm32x_info->option_bytes.user_options = optionbyte;
1212
1213 if (stm32x_write_options(bank) != ERROR_OK)
1214 {
1215 command_print(CMD_CTX, "stm32x failed to write options");
1216 return ERROR_OK;
1217 }
1218
1219 command_print(CMD_CTX, "stm32x write options complete.\n"
1220 "INFO: a reset or power cycle is required "
1221 "for the new settings to take effect.");
1222
1223 return ERROR_OK;
1224 }
1225
1226 static int stm32x_mass_erase(struct flash_bank *bank)
1227 {
1228 struct target *target = bank->target;
1229
1230 if (target->state != TARGET_HALTED)
1231 {
1232 LOG_ERROR("Target not halted");
1233 return ERROR_TARGET_NOT_HALTED;
1234 }
1235
1236 /* unlock option flash registers */
1237 int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
1238 if (retval != ERROR_OK)
1239 return retval;
1240 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
1241 if (retval != ERROR_OK)
1242 return retval;
1243
1244 /* mass erase flash memory */
1245 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
1246 if (retval != ERROR_OK)
1247 return retval;
1248 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_MER | FLASH_STRT);
1249 if (retval != ERROR_OK)
1250 return retval;
1251
1252 retval = stm32x_wait_status_busy(bank, 100);
1253 if (retval != ERROR_OK)
1254 return retval;
1255
1256 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
1257 if (retval != ERROR_OK)
1258 return retval;
1259
1260 return ERROR_OK;
1261 }
1262
1263 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1264 {
1265 int i;
1266
1267 if (CMD_ARGC < 1)
1268 {
1269 command_print(CMD_CTX, "stm32x mass_erase <bank>");
1270 return ERROR_OK;
1271 }
1272
1273 struct flash_bank *bank;
1274 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1275 if (ERROR_OK != retval)
1276 return retval;
1277
1278 retval = stm32x_mass_erase(bank);
1279 if (retval == ERROR_OK)
1280 {
1281 /* set all sectors as erased */
1282 for (i = 0; i < bank->num_sectors; i++)
1283 {
1284 bank->sectors[i].is_erased = 1;
1285 }
1286
1287 command_print(CMD_CTX, "stm32x mass erase complete");
1288 }
1289 else
1290 {
1291 command_print(CMD_CTX, "stm32x mass erase failed");
1292 }
1293
1294 return retval;
1295 }
1296
1297 static const struct command_registration stm32x_exec_command_handlers[] = {
1298 {
1299 .name = "lock",
1300 .handler = stm32x_handle_lock_command,
1301 .mode = COMMAND_EXEC,
1302 .usage = "bank_id",
1303 .help = "Lock entire flash device.",
1304 },
1305 {
1306 .name = "unlock",
1307 .handler = stm32x_handle_unlock_command,
1308 .mode = COMMAND_EXEC,
1309 .usage = "bank_id",
1310 .help = "Unlock entire protected flash device.",
1311 },
1312 {
1313 .name = "mass_erase",
1314 .handler = stm32x_handle_mass_erase_command,
1315 .mode = COMMAND_EXEC,
1316 .usage = "bank_id",
1317 .help = "Erase entire flash device.",
1318 },
1319 {
1320 .name = "options_read",
1321 .handler = stm32x_handle_options_read_command,
1322 .mode = COMMAND_EXEC,
1323 .usage = "bank_id",
1324 .help = "Read and display device option byte.",
1325 },
1326 {
1327 .name = "options_write",
1328 .handler = stm32x_handle_options_write_command,
1329 .mode = COMMAND_EXEC,
1330 .usage = "bank_id ('SWWDG'|'HWWDG') "
1331 "('RSTSTNDBY'|'NORSTSTNDBY') "
1332 "('RSTSTOP'|'NORSTSTOP')",
1333 .help = "Replace bits in device option byte.",
1334 },
1335 COMMAND_REGISTRATION_DONE
1336 };
1337
1338 static const struct command_registration stm32x_command_handlers[] = {
1339 {
1340 .name = "stm32x",
1341 .mode = COMMAND_ANY,
1342 .help = "stm32x flash command group",
1343 .chain = stm32x_exec_command_handlers,
1344 },
1345 COMMAND_REGISTRATION_DONE
1346 };
1347
1348 struct flash_driver stm32x_flash = {
1349 .name = "stm32x",
1350 .commands = stm32x_command_handlers,
1351 .flash_bank_command = stm32x_flash_bank_command,
1352 .erase = stm32x_erase,
1353 .protect = stm32x_protect,
1354 .write = stm32x_write,
1355 .read = default_flash_read,
1356 .probe = stm32x_probe,
1357 .auto_probe = stm32x_auto_probe,
1358 .erase_check = default_flash_mem_blank_check,
1359 .protect_check = stm32x_protect_check,
1360 .info = get_stm32x_info,
1361 };
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