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flash: fix bug with multiple back-to-back flash chips
[openocd.git] / src / flash / nor / stm32x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "imp.h"
28 #include "stm32x.h"
29 #include <helper/binarybuffer.h>
30 #include <target/algorithm.h>
31 #include <target/armv7m.h>
32
33
34 static int stm32x_mass_erase(struct flash_bank *bank);
35
36 /* flash bank stm32x <base> <size> 0 0 <target#>
37 */
38 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
39 {
40 struct stm32x_flash_bank *stm32x_info;
41
42 if (CMD_ARGC < 6)
43 {
44 LOG_WARNING("incomplete flash_bank stm32x configuration");
45 return ERROR_FLASH_BANK_INVALID;
46 }
47
48 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
49 bank->driver_priv = stm32x_info;
50
51 stm32x_info->write_algorithm = NULL;
52 stm32x_info->probed = 0;
53
54 return ERROR_OK;
55 }
56
57 static int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
58 {
59 struct target *target = bank->target;
60 return target_read_u32(target, STM32_FLASH_SR, status);
61 }
62
63 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
64 {
65 struct target *target = bank->target;
66 uint32_t status;
67 int retval = ERROR_OK;
68
69 /* wait for busy to clear */
70 for (;;)
71 {
72 retval = stm32x_get_flash_status(bank, &status);
73 if (retval != ERROR_OK)
74 return retval;
75 LOG_DEBUG("status: 0x%" PRIx32 "", status);
76 if ((status & FLASH_BSY) == 0)
77 break;
78 if (timeout-- <= 0)
79 {
80 LOG_ERROR("timed out waiting for flash");
81 return ERROR_FAIL;
82 }
83 alive_sleep(1);
84 }
85
86 if (status & FLASH_WRPRTERR)
87 {
88 LOG_ERROR("stm32x device protected");
89 retval = ERROR_FAIL;
90 }
91
92 if (status & FLASH_PGERR)
93 {
94 LOG_ERROR("stm32x device programming failed");
95 retval = ERROR_FAIL;
96 }
97
98 /* Clear but report errors */
99 if (status & (FLASH_WRPRTERR | FLASH_PGERR))
100 {
101 /* If this operation fails, we ignore it and report the original
102 * retval
103 */
104 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR | FLASH_PGERR);
105 }
106 return retval;
107 }
108
109 static int stm32x_read_options(struct flash_bank *bank)
110 {
111 uint32_t optiondata;
112 struct stm32x_flash_bank *stm32x_info = NULL;
113 struct target *target = bank->target;
114
115 stm32x_info = bank->driver_priv;
116
117 /* read current option bytes */
118 int retval = target_read_u32(target, STM32_FLASH_OBR, &optiondata);
119 if (retval != ERROR_OK)
120 return retval;
121
122 stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
123 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
124
125 if (optiondata & (1 << OPT_READOUT))
126 LOG_INFO("Device Security Bit Set");
127
128 /* each bit refers to a 4bank protection */
129 retval = target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
130 if (retval != ERROR_OK)
131 return retval;
132
133 stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
134 stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
135 stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
136 stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
137
138 return ERROR_OK;
139 }
140
141 static int stm32x_erase_options(struct flash_bank *bank)
142 {
143 struct stm32x_flash_bank *stm32x_info = NULL;
144 struct target *target = bank->target;
145
146 stm32x_info = bank->driver_priv;
147
148 /* read current options */
149 stm32x_read_options(bank);
150
151 /* unlock flash registers */
152 int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
153 if (retval != ERROR_OK)
154 return retval;
155
156 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
157 if (retval != ERROR_OK)
158 return retval;
159
160 /* unlock option flash registers */
161 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
162 if (retval != ERROR_OK)
163 return retval;
164 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
165 if (retval != ERROR_OK)
166 return retval;
167
168 /* erase option bytes */
169 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_OPTWRE);
170 if (retval != ERROR_OK)
171 return retval;
172 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
173 if (retval != ERROR_OK)
174 return retval;
175
176 retval = stm32x_wait_status_busy(bank, 10);
177 if (retval != ERROR_OK)
178 return retval;
179
180 /* clear readout protection and complementary option bytes
181 * this will also force a device unlock if set */
182 stm32x_info->option_bytes.RDP = 0x5AA5;
183
184 return ERROR_OK;
185 }
186
187 static int stm32x_write_options(struct flash_bank *bank)
188 {
189 struct stm32x_flash_bank *stm32x_info = NULL;
190 struct target *target = bank->target;
191
192 stm32x_info = bank->driver_priv;
193
194 /* unlock flash registers */
195 int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
196 if (retval != ERROR_OK)
197 return retval;
198 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
199 if (retval != ERROR_OK)
200 return retval;
201
202 /* unlock option flash registers */
203 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
204 if (retval != ERROR_OK)
205 return retval;
206 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
207 if (retval != ERROR_OK)
208 return retval;
209
210 /* program option bytes */
211 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG | FLASH_OPTWRE);
212 if (retval != ERROR_OK)
213 return retval;
214
215 /* write user option byte */
216 retval = target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
217 if (retval != ERROR_OK)
218 return retval;
219
220 retval = stm32x_wait_status_busy(bank, 10);
221 if (retval != ERROR_OK)
222 return retval;
223
224 /* write protection byte 1 */
225 retval = target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
226 if (retval != ERROR_OK)
227 return retval;
228
229 retval = stm32x_wait_status_busy(bank, 10);
230 if (retval != ERROR_OK)
231 return retval;
232
233 /* write protection byte 2 */
234 retval = target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
235 if (retval != ERROR_OK)
236 return retval;
237
238 retval = stm32x_wait_status_busy(bank, 10);
239 if (retval != ERROR_OK)
240 return retval;
241
242 /* write protection byte 3 */
243 retval = target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
244 if (retval != ERROR_OK)
245 return retval;
246
247 retval = stm32x_wait_status_busy(bank, 10);
248 if (retval != ERROR_OK)
249 return retval;
250
251 /* write protection byte 4 */
252 retval = target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
253 if (retval != ERROR_OK)
254 return retval;
255
256 retval = stm32x_wait_status_busy(bank, 10);
257 if (retval != ERROR_OK)
258 return retval;
259
260 /* write readout protection bit */
261 retval = target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
262 if (retval != ERROR_OK)
263 return retval;
264
265 retval = stm32x_wait_status_busy(bank, 10);
266 if (retval != ERROR_OK)
267 return retval;
268
269 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
270 if (retval != ERROR_OK)
271 return retval;
272
273 return ERROR_OK;
274 }
275
276 static int stm32x_protect_check(struct flash_bank *bank)
277 {
278 struct target *target = bank->target;
279 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
280
281 uint32_t protection;
282 int i, s;
283 int num_bits;
284 int set;
285
286 if (target->state != TARGET_HALTED)
287 {
288 LOG_ERROR("Target not halted");
289 return ERROR_TARGET_NOT_HALTED;
290 }
291
292 /* medium density - each bit refers to a 4bank protection
293 * high density - each bit refers to a 2bank protection */
294 int retval = target_read_u32(target, STM32_FLASH_WRPR, &protection);
295 if (retval != ERROR_OK)
296 return retval;
297
298 /* medium density - each protection bit is for 4 * 1K pages
299 * high density - each protection bit is for 2 * 2K pages */
300 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
301
302 if (stm32x_info->ppage_size == 2)
303 {
304 /* high density flash/connectivity line protection */
305
306 set = 1;
307
308 if (protection & (1 << 31))
309 set = 0;
310
311 /* bit 31 controls sector 62 - 255 protection for high density
312 * bit 31 controls sector 62 - 127 protection for connectivity line */
313 for (s = 62; s < bank->num_sectors; s++)
314 {
315 bank->sectors[s].is_protected = set;
316 }
317
318 if (bank->num_sectors > 61)
319 num_bits = 31;
320
321 for (i = 0; i < num_bits; i++)
322 {
323 set = 1;
324
325 if (protection & (1 << i))
326 set = 0;
327
328 for (s = 0; s < stm32x_info->ppage_size; s++)
329 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
330 }
331 }
332 else
333 {
334 /* low/medium density flash protection */
335 for (i = 0; i < num_bits; i++)
336 {
337 set = 1;
338
339 if (protection & (1 << i))
340 set = 0;
341
342 for (s = 0; s < stm32x_info->ppage_size; s++)
343 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
344 }
345 }
346
347 return ERROR_OK;
348 }
349
350 static int stm32x_erase(struct flash_bank *bank, int first, int last)
351 {
352 struct target *target = bank->target;
353 int i;
354
355 if (bank->target->state != TARGET_HALTED)
356 {
357 LOG_ERROR("Target not halted");
358 return ERROR_TARGET_NOT_HALTED;
359 }
360
361 if ((first == 0) && (last == (bank->num_sectors - 1)))
362 {
363 return stm32x_mass_erase(bank);
364 }
365
366 /* unlock flash registers */
367 int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
368 if (retval != ERROR_OK)
369 return retval;
370 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
371 if (retval != ERROR_OK)
372 return retval;
373
374 for (i = first; i <= last; i++)
375 {
376 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
377 if (retval != ERROR_OK)
378 return retval;
379 retval = target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
380 if (retval != ERROR_OK)
381 return retval;
382 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PER | FLASH_STRT);
383 if (retval != ERROR_OK)
384 return retval;
385
386 retval = stm32x_wait_status_busy(bank, 100);
387 if (retval != ERROR_OK)
388 return retval;
389
390 bank->sectors[i].is_erased = 1;
391 }
392
393 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
394 if (retval != ERROR_OK)
395 return retval;
396
397 return ERROR_OK;
398 }
399
400 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
401 {
402 struct stm32x_flash_bank *stm32x_info = NULL;
403 struct target *target = bank->target;
404 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
405 int i, reg, bit;
406 int status;
407 uint32_t protection;
408
409 stm32x_info = bank->driver_priv;
410
411 if (target->state != TARGET_HALTED)
412 {
413 LOG_ERROR("Target not halted");
414 return ERROR_TARGET_NOT_HALTED;
415 }
416
417 if ((first && (first % stm32x_info->ppage_size)) || ((last + 1) &&
418 (last + 1) % stm32x_info->ppage_size))
419 {
420 LOG_WARNING("Error: start and end sectors must be on a %d sector boundary",
421 stm32x_info->ppage_size);
422 return ERROR_FLASH_SECTOR_INVALID;
423 }
424
425 /* medium density - each bit refers to a 4bank protection
426 * high density - each bit refers to a 2bank protection */
427 int retval = target_read_u32(target, STM32_FLASH_WRPR, &protection);
428 if (retval != ERROR_OK)
429 return retval;
430
431 prot_reg[0] = (uint16_t)protection;
432 prot_reg[1] = (uint16_t)(protection >> 8);
433 prot_reg[2] = (uint16_t)(protection >> 16);
434 prot_reg[3] = (uint16_t)(protection >> 24);
435
436 if (stm32x_info->ppage_size == 2)
437 {
438 /* high density flash */
439
440 /* bit 7 controls sector 62 - 255 protection */
441 if (last > 61)
442 {
443 if (set)
444 prot_reg[3] &= ~(1 << 7);
445 else
446 prot_reg[3] |= (1 << 7);
447 }
448
449 if (first > 61)
450 first = 62;
451 if (last > 61)
452 last = 61;
453
454 for (i = first; i <= last; i++)
455 {
456 reg = (i / stm32x_info->ppage_size) / 8;
457 bit = (i / stm32x_info->ppage_size) - (reg * 8);
458
459 if (set)
460 prot_reg[reg] &= ~(1 << bit);
461 else
462 prot_reg[reg] |= (1 << bit);
463 }
464 }
465 else
466 {
467 /* medium density flash */
468 for (i = first; i <= last; i++)
469 {
470 reg = (i / stm32x_info->ppage_size) / 8;
471 bit = (i / stm32x_info->ppage_size) - (reg * 8);
472
473 if (set)
474 prot_reg[reg] &= ~(1 << bit);
475 else
476 prot_reg[reg] |= (1 << bit);
477 }
478 }
479
480 if ((status = stm32x_erase_options(bank)) != ERROR_OK)
481 return status;
482
483 stm32x_info->option_bytes.protection[0] = prot_reg[0];
484 stm32x_info->option_bytes.protection[1] = prot_reg[1];
485 stm32x_info->option_bytes.protection[2] = prot_reg[2];
486 stm32x_info->option_bytes.protection[3] = prot_reg[3];
487
488 return stm32x_write_options(bank);
489 }
490
491 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
492 uint32_t offset, uint32_t count)
493 {
494 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
495 struct target *target = bank->target;
496 uint32_t buffer_size = 16384;
497 struct working_area *source;
498 uint32_t address = bank->base + offset;
499 struct reg_param reg_params[4];
500 struct armv7m_algorithm armv7m_info;
501 int retval = ERROR_OK;
502
503 /* see contib/loaders/flash/stm32x.s for src */
504
505 static const uint8_t stm32x_flash_write_code[] = {
506 /* #define STM32_FLASH_CR_OFFSET 0x10 */
507 /* #define STM32_FLASH_SR_OFFSET 0x0C */
508 /* write: */
509 0xdf, 0xf8, 0x20, 0x40, /* ldr r4, STM32_FLASH_BASE */
510 /* write_half_word: */
511 0x01, 0x23, /* movs r3, #0x01 */
512 0x23, 0x61, /* str r3, [r4, #STM32_FLASH_CR_OFFSET] */
513 0x30, 0xf8, 0x02, 0x3b, /* ldrh r3, [r0], #0x02 */
514 0x21, 0xf8, 0x02, 0x3b, /* strh r3, [r1], #0x02 */
515 /* busy: */
516 0xe3, 0x68, /* ldr r3, [r4, #STM32_FLASH_SR_OFFSET] */
517 0x13, 0xf0, 0x01, 0x0f, /* tst r3, #0x01 */
518 0xfb, 0xd0, /* beq busy */
519 0x13, 0xf0, 0x14, 0x0f, /* tst r3, #0x14 */
520 0x01, 0xd1, /* bne exit */
521 0x01, 0x3a, /* subs r2, r2, #0x01 */
522 0xf0, 0xd1, /* bne write_half_word */
523 /* exit: */
524 0x00, 0xbe, /* bkpt #0x00 */
525 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */
526 };
527
528 /* flash write code */
529 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
530 &stm32x_info->write_algorithm) != ERROR_OK)
531 {
532 LOG_WARNING("no working area available, can't do block memory writes");
533 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
534 };
535
536 if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address,
537 sizeof(stm32x_flash_write_code),
538 (uint8_t*)stm32x_flash_write_code)) != ERROR_OK)
539 return retval;
540
541 /* memory buffer */
542 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
543 {
544 buffer_size /= 2;
545 if (buffer_size <= 256)
546 {
547 /* if we already allocated the writing code, but failed to get a
548 * buffer, free the algorithm */
549 if (stm32x_info->write_algorithm)
550 target_free_working_area(target, stm32x_info->write_algorithm);
551
552 LOG_WARNING("no large enough working area available, can't do block memory writes");
553 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
554 }
555 };
556
557 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
558 armv7m_info.core_mode = ARMV7M_MODE_ANY;
559
560 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
561 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
562 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
563 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
564
565 while (count > 0)
566 {
567 uint32_t thisrun_count = (count > (buffer_size / 2)) ?
568 (buffer_size / 2) : count;
569
570 if ((retval = target_write_buffer(target, source->address,
571 thisrun_count * 2, buffer)) != ERROR_OK)
572 break;
573
574 buf_set_u32(reg_params[0].value, 0, 32, source->address);
575 buf_set_u32(reg_params[1].value, 0, 32, address);
576 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
577
578 if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params,
579 stm32x_info->write_algorithm->address,
580 0,
581 10000, &armv7m_info)) != ERROR_OK)
582 {
583 LOG_ERROR("error executing stm32x flash write algorithm");
584 break;
585 }
586
587 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_PGERR)
588 {
589 LOG_ERROR("flash memory not erased before writing");
590 /* Clear but report errors */
591 target_write_u32(target, STM32_FLASH_SR, FLASH_PGERR);
592 retval = ERROR_FAIL;
593 break;
594 }
595
596 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_WRPRTERR)
597 {
598 LOG_ERROR("flash memory write protected");
599 /* Clear but report errors */
600 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR);
601 retval = ERROR_FAIL;
602 break;
603 }
604
605 buffer += thisrun_count * 2;
606 address += thisrun_count * 2;
607 count -= thisrun_count;
608 }
609
610 target_free_working_area(target, source);
611 target_free_working_area(target, stm32x_info->write_algorithm);
612
613 destroy_reg_param(&reg_params[0]);
614 destroy_reg_param(&reg_params[1]);
615 destroy_reg_param(&reg_params[2]);
616 destroy_reg_param(&reg_params[3]);
617
618 return retval;
619 }
620
621 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
622 uint32_t offset, uint32_t count)
623 {
624 struct target *target = bank->target;
625 uint32_t words_remaining = (count / 2);
626 uint32_t bytes_remaining = (count & 0x00000001);
627 uint32_t address = bank->base + offset;
628 uint32_t bytes_written = 0;
629 int retval;
630
631 if (bank->target->state != TARGET_HALTED)
632 {
633 LOG_ERROR("Target not halted");
634 return ERROR_TARGET_NOT_HALTED;
635 }
636
637 if (offset & 0x1)
638 {
639 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
640 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
641 }
642
643 /* unlock flash registers */
644 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
645 if (retval != ERROR_OK)
646 return retval;
647 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
648 if (retval != ERROR_OK)
649 return retval;
650
651 /* multiple half words (2-byte) to be programmed? */
652 if (words_remaining > 0)
653 {
654 /* try using a block write */
655 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
656 {
657 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
658 {
659 /* if block write failed (no sufficient working area),
660 * we use normal (slow) single dword accesses */
661 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
662 }
663 }
664 else
665 {
666 buffer += words_remaining * 2;
667 address += words_remaining * 2;
668 words_remaining = 0;
669 }
670 }
671
672 if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
673 return retval;
674
675 while (words_remaining > 0)
676 {
677 uint16_t value;
678 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
679
680 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
681 if (retval != ERROR_OK)
682 return retval;
683 retval = target_write_u16(target, address, value);
684 if (retval != ERROR_OK)
685 return retval;
686
687 retval = stm32x_wait_status_busy(bank, 5);
688 if (retval != ERROR_OK)
689 return retval;
690
691 bytes_written += 2;
692 words_remaining--;
693 address += 2;
694 }
695
696 if (bytes_remaining)
697 {
698 uint16_t value = 0xffff;
699 memcpy(&value, buffer + bytes_written, bytes_remaining);
700
701 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
702 if (retval != ERROR_OK)
703 return retval;
704 retval = target_write_u16(target, address, value);
705 if (retval != ERROR_OK)
706 return retval;
707
708 retval = stm32x_wait_status_busy(bank, 5);
709 if (retval != ERROR_OK)
710 return retval;
711 }
712
713 return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
714 }
715
716 static int stm32x_probe(struct flash_bank *bank)
717 {
718 struct target *target = bank->target;
719 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
720 int i;
721 uint16_t num_pages;
722 uint32_t device_id;
723 int page_size;
724
725 stm32x_info->probed = 0;
726
727 /* read stm32 device id register */
728 int retval = target_read_u32(target, 0xE0042000, &device_id);
729 if (retval != ERROR_OK)
730 return retval;
731 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
732
733 /* get flash size from target. */
734 retval = target_read_u16(target, 0x1FFFF7E0, &num_pages);
735 if (retval != ERROR_OK)
736 {
737 LOG_WARNING("failed reading flash size, default to max target family");
738 /* failed reading flash size, default to max target family */
739 num_pages = 0xffff;
740 }
741
742 if ((device_id & 0x7ff) == 0x410)
743 {
744 /* medium density - we have 1k pages
745 * 4 pages for a protection area */
746 page_size = 1024;
747 stm32x_info->ppage_size = 4;
748
749 /* check for early silicon */
750 if (num_pages == 0xffff)
751 {
752 /* number of sectors incorrect on revA */
753 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
754 num_pages = 128;
755 }
756 }
757 else if ((device_id & 0x7ff) == 0x412)
758 {
759 /* low density - we have 1k pages
760 * 4 pages for a protection area */
761 page_size = 1024;
762 stm32x_info->ppage_size = 4;
763
764 /* check for early silicon */
765 if (num_pages == 0xffff)
766 {
767 /* number of sectors incorrect on revA */
768 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
769 num_pages = 32;
770 }
771 }
772 else if ((device_id & 0x7ff) == 0x414)
773 {
774 /* high density - we have 2k pages
775 * 2 pages for a protection area */
776 page_size = 2048;
777 stm32x_info->ppage_size = 2;
778
779 /* check for early silicon */
780 if (num_pages == 0xffff)
781 {
782 /* number of sectors incorrect on revZ */
783 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
784 num_pages = 512;
785 }
786 }
787 else if ((device_id & 0x7ff) == 0x418)
788 {
789 /* connectivity line density - we have 2k pages
790 * 2 pages for a protection area */
791 page_size = 2048;
792 stm32x_info->ppage_size = 2;
793
794 /* check for early silicon */
795 if (num_pages == 0xffff)
796 {
797 /* number of sectors incorrect on revZ */
798 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
799 num_pages = 256;
800 }
801 }
802 else if ((device_id & 0x7ff) == 0x420)
803 {
804 /* value line density - we have 1k pages
805 * 4 pages for a protection area */
806 page_size = 1024;
807 stm32x_info->ppage_size = 4;
808
809 /* check for early silicon */
810 if (num_pages == 0xffff)
811 {
812 /* number of sectors may be incorrrect on early silicon */
813 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
814 num_pages = 128;
815 }
816 }
817 else
818 {
819 LOG_WARNING("Cannot identify target as a STM32 family.");
820 return ERROR_FAIL;
821 }
822
823 LOG_INFO("flash size = %dkbytes", num_pages);
824
825 /* calculate numbers of pages */
826 num_pages /= (page_size / 1024);
827
828 if (bank->sectors)
829 {
830 free(bank->sectors);
831 bank->sectors = NULL;
832 }
833
834 bank->base = 0x08000000;
835 bank->size = (num_pages * page_size);
836 bank->num_sectors = num_pages;
837 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
838
839 for (i = 0; i < num_pages; i++)
840 {
841 bank->sectors[i].offset = i * page_size;
842 bank->sectors[i].size = page_size;
843 bank->sectors[i].is_erased = -1;
844 bank->sectors[i].is_protected = 1;
845 }
846
847 stm32x_info->probed = 1;
848
849 return ERROR_OK;
850 }
851
852 static int stm32x_auto_probe(struct flash_bank *bank)
853 {
854 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
855 if (stm32x_info->probed)
856 return ERROR_OK;
857 return stm32x_probe(bank);
858 }
859
860 #if 0
861 COMMAND_HANDLER(stm32x_handle_part_id_command)
862 {
863 return ERROR_OK;
864 }
865 #endif
866
867 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
868 {
869 struct target *target = bank->target;
870 uint32_t device_id;
871 int printed;
872
873 /* read stm32 device id register */
874 int retval = target_read_u32(target, 0xE0042000, &device_id);
875 if (retval != ERROR_OK)
876 return retval;
877
878 if ((device_id & 0x7ff) == 0x410)
879 {
880 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
881 buf += printed;
882 buf_size -= printed;
883
884 switch (device_id >> 16)
885 {
886 case 0x0000:
887 snprintf(buf, buf_size, "A");
888 break;
889
890 case 0x2000:
891 snprintf(buf, buf_size, "B");
892 break;
893
894 case 0x2001:
895 snprintf(buf, buf_size, "Z");
896 break;
897
898 case 0x2003:
899 snprintf(buf, buf_size, "Y");
900 break;
901
902 default:
903 snprintf(buf, buf_size, "unknown");
904 break;
905 }
906 }
907 else if ((device_id & 0x7ff) == 0x412)
908 {
909 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
910 buf += printed;
911 buf_size -= printed;
912
913 switch (device_id >> 16)
914 {
915 case 0x1000:
916 snprintf(buf, buf_size, "A");
917 break;
918
919 default:
920 snprintf(buf, buf_size, "unknown");
921 break;
922 }
923 }
924 else if ((device_id & 0x7ff) == 0x414)
925 {
926 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
927 buf += printed;
928 buf_size -= printed;
929
930 switch (device_id >> 16)
931 {
932 case 0x1000:
933 snprintf(buf, buf_size, "A");
934 break;
935
936 case 0x1001:
937 snprintf(buf, buf_size, "Z");
938 break;
939
940 default:
941 snprintf(buf, buf_size, "unknown");
942 break;
943 }
944 }
945 else if ((device_id & 0x7ff) == 0x418)
946 {
947 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
948 buf += printed;
949 buf_size -= printed;
950
951 switch (device_id >> 16)
952 {
953 case 0x1000:
954 snprintf(buf, buf_size, "A");
955 break;
956
957 case 0x1001:
958 snprintf(buf, buf_size, "Z");
959 break;
960
961 default:
962 snprintf(buf, buf_size, "unknown");
963 break;
964 }
965 }
966 else if ((device_id & 0x7ff) == 0x420)
967 {
968 printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
969 buf += printed;
970 buf_size -= printed;
971
972 switch (device_id >> 16)
973 {
974 case 0x1000:
975 snprintf(buf, buf_size, "A");
976 break;
977
978 case 0x1001:
979 snprintf(buf, buf_size, "Z");
980 break;
981
982 default:
983 snprintf(buf, buf_size, "unknown");
984 break;
985 }
986 }
987 else
988 {
989 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
990 return ERROR_FAIL;
991 }
992
993 return ERROR_OK;
994 }
995
996 COMMAND_HANDLER(stm32x_handle_lock_command)
997 {
998 struct target *target = NULL;
999 struct stm32x_flash_bank *stm32x_info = NULL;
1000
1001 if (CMD_ARGC < 1)
1002 {
1003 command_print(CMD_CTX, "stm32x lock <bank>");
1004 return ERROR_OK;
1005 }
1006
1007 struct flash_bank *bank;
1008 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1009 if (ERROR_OK != retval)
1010 return retval;
1011
1012 stm32x_info = bank->driver_priv;
1013
1014 target = bank->target;
1015
1016 if (target->state != TARGET_HALTED)
1017 {
1018 LOG_ERROR("Target not halted");
1019 return ERROR_TARGET_NOT_HALTED;
1020 }
1021
1022 if (stm32x_erase_options(bank) != ERROR_OK)
1023 {
1024 command_print(CMD_CTX, "stm32x failed to erase options");
1025 return ERROR_OK;
1026 }
1027
1028 /* set readout protection */
1029 stm32x_info->option_bytes.RDP = 0;
1030
1031 if (stm32x_write_options(bank) != ERROR_OK)
1032 {
1033 command_print(CMD_CTX, "stm32x failed to lock device");
1034 return ERROR_OK;
1035 }
1036
1037 command_print(CMD_CTX, "stm32x locked");
1038
1039 return ERROR_OK;
1040 }
1041
1042 COMMAND_HANDLER(stm32x_handle_unlock_command)
1043 {
1044 struct target *target = NULL;
1045 struct stm32x_flash_bank *stm32x_info = NULL;
1046
1047 if (CMD_ARGC < 1)
1048 {
1049 command_print(CMD_CTX, "stm32x unlock <bank>");
1050 return ERROR_OK;
1051 }
1052
1053 struct flash_bank *bank;
1054 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1055 if (ERROR_OK != retval)
1056 return retval;
1057
1058 stm32x_info = bank->driver_priv;
1059
1060 target = bank->target;
1061
1062 if (target->state != TARGET_HALTED)
1063 {
1064 LOG_ERROR("Target not halted");
1065 return ERROR_TARGET_NOT_HALTED;
1066 }
1067
1068 if (stm32x_erase_options(bank) != ERROR_OK)
1069 {
1070 command_print(CMD_CTX, "stm32x failed to unlock device");
1071 return ERROR_OK;
1072 }
1073
1074 if (stm32x_write_options(bank) != ERROR_OK)
1075 {
1076 command_print(CMD_CTX, "stm32x failed to lock device");
1077 return ERROR_OK;
1078 }
1079
1080 command_print(CMD_CTX, "stm32x unlocked.\n"
1081 "INFO: a reset or power cycle is required "
1082 "for the new settings to take effect.");
1083
1084 return ERROR_OK;
1085 }
1086
1087 COMMAND_HANDLER(stm32x_handle_options_read_command)
1088 {
1089 uint32_t optionbyte;
1090 struct target *target = NULL;
1091 struct stm32x_flash_bank *stm32x_info = NULL;
1092
1093 if (CMD_ARGC < 1)
1094 {
1095 command_print(CMD_CTX, "stm32x options_read <bank>");
1096 return ERROR_OK;
1097 }
1098
1099 struct flash_bank *bank;
1100 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1101 if (ERROR_OK != retval)
1102 return retval;
1103
1104 stm32x_info = bank->driver_priv;
1105
1106 target = bank->target;
1107
1108 if (target->state != TARGET_HALTED)
1109 {
1110 LOG_ERROR("Target not halted");
1111 return ERROR_TARGET_NOT_HALTED;
1112 }
1113
1114 retval = target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
1115 if (retval != ERROR_OK)
1116 return retval;
1117 command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1118
1119 if (buf_get_u32((uint8_t*)&optionbyte, OPT_ERROR, 1))
1120 command_print(CMD_CTX, "Option Byte Complement Error");
1121
1122 if (buf_get_u32((uint8_t*)&optionbyte, OPT_READOUT, 1))
1123 command_print(CMD_CTX, "Readout Protection On");
1124 else
1125 command_print(CMD_CTX, "Readout Protection Off");
1126
1127 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDWDGSW, 1))
1128 command_print(CMD_CTX, "Software Watchdog");
1129 else
1130 command_print(CMD_CTX, "Hardware Watchdog");
1131
1132 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTOP, 1))
1133 command_print(CMD_CTX, "Stop: No reset generated");
1134 else
1135 command_print(CMD_CTX, "Stop: Reset generated");
1136
1137 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTDBY, 1))
1138 command_print(CMD_CTX, "Standby: No reset generated");
1139 else
1140 command_print(CMD_CTX, "Standby: Reset generated");
1141
1142 return ERROR_OK;
1143 }
1144
1145 COMMAND_HANDLER(stm32x_handle_options_write_command)
1146 {
1147 struct target *target = NULL;
1148 struct stm32x_flash_bank *stm32x_info = NULL;
1149 uint16_t optionbyte = 0xF8;
1150
1151 if (CMD_ARGC < 4)
1152 {
1153 command_print(CMD_CTX, "stm32x options_write <bank> <SWWDG | HWWDG> <RSTSTNDBY | NORSTSTNDBY> <RSTSTOP | NORSTSTOP>");
1154 return ERROR_OK;
1155 }
1156
1157 struct flash_bank *bank;
1158 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1159 if (ERROR_OK != retval)
1160 return retval;
1161
1162 stm32x_info = bank->driver_priv;
1163
1164 target = bank->target;
1165
1166 if (target->state != TARGET_HALTED)
1167 {
1168 LOG_ERROR("Target not halted");
1169 return ERROR_TARGET_NOT_HALTED;
1170 }
1171
1172 /* REVISIT: ignores some options which we will display...
1173 * and doesn't insist on the specified syntax.
1174 */
1175
1176 /* OPT_RDWDGSW */
1177 if (strcmp(CMD_ARGV[1], "SWWDG") == 0)
1178 {
1179 optionbyte |= (1 << 0);
1180 }
1181 else /* REVISIT must be "HWWDG" then ... */
1182 {
1183 optionbyte &= ~(1 << 0);
1184 }
1185
1186 /* OPT_RDRSTSTDBY */
1187 if (strcmp(CMD_ARGV[2], "NORSTSTNDBY") == 0)
1188 {
1189 optionbyte |= (1 << 1);
1190 }
1191 else /* REVISIT must be "RSTSTNDBY" then ... */
1192 {
1193 optionbyte &= ~(1 << 1);
1194 }
1195
1196 /* OPT_RDRSTSTOP */
1197 if (strcmp(CMD_ARGV[3], "NORSTSTOP") == 0)
1198 {
1199 optionbyte |= (1 << 2);
1200 }
1201 else /* REVISIT must be "RSTSTOP" then ... */
1202 {
1203 optionbyte &= ~(1 << 2);
1204 }
1205
1206 if (stm32x_erase_options(bank) != ERROR_OK)
1207 {
1208 command_print(CMD_CTX, "stm32x failed to erase options");
1209 return ERROR_OK;
1210 }
1211
1212 stm32x_info->option_bytes.user_options = optionbyte;
1213
1214 if (stm32x_write_options(bank) != ERROR_OK)
1215 {
1216 command_print(CMD_CTX, "stm32x failed to write options");
1217 return ERROR_OK;
1218 }
1219
1220 command_print(CMD_CTX, "stm32x write options complete.\n"
1221 "INFO: a reset or power cycle is required "
1222 "for the new settings to take effect.");
1223
1224 return ERROR_OK;
1225 }
1226
1227 static int stm32x_mass_erase(struct flash_bank *bank)
1228 {
1229 struct target *target = bank->target;
1230
1231 if (target->state != TARGET_HALTED)
1232 {
1233 LOG_ERROR("Target not halted");
1234 return ERROR_TARGET_NOT_HALTED;
1235 }
1236
1237 /* unlock option flash registers */
1238 int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
1239 if (retval != ERROR_OK)
1240 return retval;
1241 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
1242 if (retval != ERROR_OK)
1243 return retval;
1244
1245 /* mass erase flash memory */
1246 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
1247 if (retval != ERROR_OK)
1248 return retval;
1249 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_MER | FLASH_STRT);
1250 if (retval != ERROR_OK)
1251 return retval;
1252
1253 retval = stm32x_wait_status_busy(bank, 100);
1254 if (retval != ERROR_OK)
1255 return retval;
1256
1257 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
1258 if (retval != ERROR_OK)
1259 return retval;
1260
1261 return ERROR_OK;
1262 }
1263
1264 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1265 {
1266 int i;
1267
1268 if (CMD_ARGC < 1)
1269 {
1270 command_print(CMD_CTX, "stm32x mass_erase <bank>");
1271 return ERROR_OK;
1272 }
1273
1274 struct flash_bank *bank;
1275 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1276 if (ERROR_OK != retval)
1277 return retval;
1278
1279 retval = stm32x_mass_erase(bank);
1280 if (retval == ERROR_OK)
1281 {
1282 /* set all sectors as erased */
1283 for (i = 0; i < bank->num_sectors; i++)
1284 {
1285 bank->sectors[i].is_erased = 1;
1286 }
1287
1288 command_print(CMD_CTX, "stm32x mass erase complete");
1289 }
1290 else
1291 {
1292 command_print(CMD_CTX, "stm32x mass erase failed");
1293 }
1294
1295 return retval;
1296 }
1297
1298 static const struct command_registration stm32x_exec_command_handlers[] = {
1299 {
1300 .name = "lock",
1301 .handler = stm32x_handle_lock_command,
1302 .mode = COMMAND_EXEC,
1303 .usage = "bank_id",
1304 .help = "Lock entire flash device.",
1305 },
1306 {
1307 .name = "unlock",
1308 .handler = stm32x_handle_unlock_command,
1309 .mode = COMMAND_EXEC,
1310 .usage = "bank_id",
1311 .help = "Unlock entire protected flash device.",
1312 },
1313 {
1314 .name = "mass_erase",
1315 .handler = stm32x_handle_mass_erase_command,
1316 .mode = COMMAND_EXEC,
1317 .usage = "bank_id",
1318 .help = "Erase entire flash device.",
1319 },
1320 {
1321 .name = "options_read",
1322 .handler = stm32x_handle_options_read_command,
1323 .mode = COMMAND_EXEC,
1324 .usage = "bank_id",
1325 .help = "Read and display device option byte.",
1326 },
1327 {
1328 .name = "options_write",
1329 .handler = stm32x_handle_options_write_command,
1330 .mode = COMMAND_EXEC,
1331 .usage = "bank_id ('SWWDG'|'HWWDG') "
1332 "('RSTSTNDBY'|'NORSTSTNDBY') "
1333 "('RSTSTOP'|'NORSTSTOP')",
1334 .help = "Replace bits in device option byte.",
1335 },
1336 COMMAND_REGISTRATION_DONE
1337 };
1338
1339 static const struct command_registration stm32x_command_handlers[] = {
1340 {
1341 .name = "stm32x",
1342 .mode = COMMAND_ANY,
1343 .help = "stm32x flash command group",
1344 .chain = stm32x_exec_command_handlers,
1345 },
1346 COMMAND_REGISTRATION_DONE
1347 };
1348
1349 struct flash_driver stm32x_flash = {
1350 .name = "stm32x",
1351 .commands = stm32x_command_handlers,
1352 .flash_bank_command = stm32x_flash_bank_command,
1353 .erase = stm32x_erase,
1354 .protect = stm32x_protect,
1355 .write = stm32x_write,
1356 .read = default_flash_read,
1357 .probe = stm32x_probe,
1358 .auto_probe = stm32x_auto_probe,
1359 .erase_check = default_flash_mem_blank_check,
1360 .protect_check = stm32x_protect_check,
1361 .info = get_stm32x_info,
1362 };
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