Code Review / openocd.git / blob
? search:
summary | shortlog | log | commit | commitdiff | review | tree
history | raw | HEAD
stm32: return error when failing to read
[openocd.git] / src / flash / nor / stm32x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "imp.h"
28 #include "stm32x.h"
29 #include <helper/binarybuffer.h>
30 #include <target/algorithm.h>
31 #include <target/armv7m.h>
32
33
34 static int stm32x_mass_erase(struct flash_bank *bank);
35
36 /* flash bank stm32x <base> <size> 0 0 <target#>
37 */
38 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
39 {
40 struct stm32x_flash_bank *stm32x_info;
41
42 if (CMD_ARGC < 6)
43 {
44 LOG_WARNING("incomplete flash_bank stm32x configuration");
45 return ERROR_FLASH_BANK_INVALID;
46 }
47
48 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
49 bank->driver_priv = stm32x_info;
50
51 stm32x_info->write_algorithm = NULL;
52 stm32x_info->probed = 0;
53
54 return ERROR_OK;
55 }
56
57 static int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
58 {
59 struct target *target = bank->target;
60 return target_read_u32(target, STM32_FLASH_SR, status);
61 }
62
63 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
64 {
65 struct target *target = bank->target;
66 uint32_t status;
67 int retval = ERROR_OK;
68
69 /* wait for busy to clear */
70 for (;;)
71 {
72 retval = stm32x_get_flash_status(bank, &status);
73 if (retval != ERROR_OK)
74 return retval;
75 LOG_DEBUG("status: 0x%" PRIx32 "", status);
76 if ((status & FLASH_BSY) == 0)
77 break;
78 if (timeout-- <= 0)
79 {
80 LOG_ERROR("timed out waiting for flash");
81 return ERROR_FAIL;
82 }
83 alive_sleep(1);
84 }
85
86 if (status & FLASH_WRPRTERR)
87 {
88 LOG_ERROR("stm32x device protected");
89 retval = ERROR_FAIL;
90 }
91
92 if (status & FLASH_PGERR)
93 {
94 LOG_ERROR("stm32x device programming failed");
95 retval = ERROR_FAIL;
96 }
97
98 /* Clear but report errors */
99 if (status & (FLASH_WRPRTERR | FLASH_PGERR))
100 {
101 /* If this operation fails, we ignore it and report the original
102 * retval
103 */
104 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR | FLASH_PGERR);
105 }
106 return retval;
107 }
108
109 static int stm32x_read_options(struct flash_bank *bank)
110 {
111 uint32_t optiondata;
112 struct stm32x_flash_bank *stm32x_info = NULL;
113 struct target *target = bank->target;
114
115 stm32x_info = bank->driver_priv;
116
117 /* read current option bytes */
118 int retval = target_read_u32(target, STM32_FLASH_OBR, &optiondata);
119 if (retval != ERROR_OK)
120 return retval;
121
122 stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
123 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
124
125 if (optiondata & (1 << OPT_READOUT))
126 LOG_INFO("Device Security Bit Set");
127
128 /* each bit refers to a 4bank protection */
129 retval = target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
130 if (retval != ERROR_OK)
131 return retval;
132
133 stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
134 stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
135 stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
136 stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
137
138 return ERROR_OK;
139 }
140
141 static int stm32x_erase_options(struct flash_bank *bank)
142 {
143 struct stm32x_flash_bank *stm32x_info = NULL;
144 struct target *target = bank->target;
145
146 stm32x_info = bank->driver_priv;
147
148 /* read current options */
149 stm32x_read_options(bank);
150
151 /* unlock flash registers */
152 int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
153 if (retval != ERROR_OK)
154 return retval;
155
156 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
157 if (retval != ERROR_OK)
158 return retval;
159
160 /* unlock option flash registers */
161 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
162 if (retval != ERROR_OK)
163 return retval;
164 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
165 if (retval != ERROR_OK)
166 return retval;
167
168 /* erase option bytes */
169 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_OPTWRE);
170 if (retval != ERROR_OK)
171 return retval;
172 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
173 if (retval != ERROR_OK)
174 return retval;
175
176 retval = stm32x_wait_status_busy(bank, 10);
177 if (retval != ERROR_OK)
178 return retval;
179
180 /* clear readout protection and complementary option bytes
181 * this will also force a device unlock if set */
182 stm32x_info->option_bytes.RDP = 0x5AA5;
183
184 return ERROR_OK;
185 }
186
187 static int stm32x_write_options(struct flash_bank *bank)
188 {
189 struct stm32x_flash_bank *stm32x_info = NULL;
190 struct target *target = bank->target;
191
192 stm32x_info = bank->driver_priv;
193
194 /* unlock flash registers */
195 int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
196 if (retval != ERROR_OK)
197 return retval;
198 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
199 if (retval != ERROR_OK)
200 return retval;
201
202 /* unlock option flash registers */
203 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
204 if (retval != ERROR_OK)
205 return retval;
206 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
207 if (retval != ERROR_OK)
208 return retval;
209
210 /* program option bytes */
211 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG | FLASH_OPTWRE);
212 if (retval != ERROR_OK)
213 return retval;
214
215 /* write user option byte */
216 retval = target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
217 if (retval != ERROR_OK)
218 return retval;
219
220 retval = stm32x_wait_status_busy(bank, 10);
221 if (retval != ERROR_OK)
222 return retval;
223
224 /* write protection byte 1 */
225 retval = target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
226 if (retval != ERROR_OK)
227 return retval;
228
229 retval = stm32x_wait_status_busy(bank, 10);
230 if (retval != ERROR_OK)
231 return retval;
232
233 /* write protection byte 2 */
234 retval = target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
235 if (retval != ERROR_OK)
236 return retval;
237
238 retval = stm32x_wait_status_busy(bank, 10);
239 if (retval != ERROR_OK)
240 return retval;
241
242 /* write protection byte 3 */
243 retval = target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
244 if (retval != ERROR_OK)
245 return retval;
246
247 retval = stm32x_wait_status_busy(bank, 10);
248 if (retval != ERROR_OK)
249 return retval;
250
251 /* write protection byte 4 */
252 retval = target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
253 if (retval != ERROR_OK)
254 return retval;
255
256 retval = stm32x_wait_status_busy(bank, 10);
257 if (retval != ERROR_OK)
258 return retval;
259
260 /* write readout protection bit */
261 retval = target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
262 if (retval != ERROR_OK)
263 return retval;
264
265 retval = stm32x_wait_status_busy(bank, 10);
266 if (retval != ERROR_OK)
267 return retval;
268
269 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
270 if (retval != ERROR_OK)
271 return retval;
272
273 return ERROR_OK;
274 }
275
276 static int stm32x_protect_check(struct flash_bank *bank)
277 {
278 struct target *target = bank->target;
279 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
280
281 uint32_t protection;
282 int i, s;
283 int num_bits;
284 int set;
285
286 if (target->state != TARGET_HALTED)
287 {
288 LOG_ERROR("Target not halted");
289 return ERROR_TARGET_NOT_HALTED;
290 }
291
292 /* medium density - each bit refers to a 4bank protection
293 * high density - each bit refers to a 2bank protection */
294 int retval = target_read_u32(target, STM32_FLASH_WRPR, &protection);
295 if (retval != ERROR_OK)
296 return retval;
297
298 /* medium density - each protection bit is for 4 * 1K pages
299 * high density - each protection bit is for 2 * 2K pages */
300 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
301
302 if (stm32x_info->ppage_size == 2)
303 {
304 /* high density flash/connectivity line protection */
305
306 set = 1;
307
308 if (protection & (1 << 31))
309 set = 0;
310
311 /* bit 31 controls sector 62 - 255 protection for high density
312 * bit 31 controls sector 62 - 127 protection for connectivity line */
313 for (s = 62; s < bank->num_sectors; s++)
314 {
315 bank->sectors[s].is_protected = set;
316 }
317
318 if (bank->num_sectors > 61)
319 num_bits = 31;
320
321 for (i = 0; i < num_bits; i++)
322 {
323 set = 1;
324
325 if (protection & (1 << i))
326 set = 0;
327
328 for (s = 0; s < stm32x_info->ppage_size; s++)
329 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
330 }
331 }
332 else
333 {
334 /* low/medium density flash protection */
335 for (i = 0; i < num_bits; i++)
336 {
337 set = 1;
338
339 if (protection & (1 << i))
340 set = 0;
341
342 for (s = 0; s < stm32x_info->ppage_size; s++)
343 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
344 }
345 }
346
347 return ERROR_OK;
348 }
349
350 static int stm32x_erase(struct flash_bank *bank, int first, int last)
351 {
352 struct target *target = bank->target;
353 int i;
354
355 if (bank->target->state != TARGET_HALTED)
356 {
357 LOG_ERROR("Target not halted");
358 return ERROR_TARGET_NOT_HALTED;
359 }
360
361 if ((first == 0) && (last == (bank->num_sectors - 1)))
362 {
363 return stm32x_mass_erase(bank);
364 }
365
366 /* unlock flash registers */
367 int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
368 if (retval != ERROR_OK)
369 return retval;
370 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
371 if (retval != ERROR_OK)
372 return retval;
373
374 for (i = first; i <= last; i++)
375 {
376 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
377 if (retval != ERROR_OK)
378 return retval;
379 retval = target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
380 if (retval != ERROR_OK)
381 return retval;
382 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PER | FLASH_STRT);
383 if (retval != ERROR_OK)
384 return retval;
385
386 retval = stm32x_wait_status_busy(bank, 100);
387 if (retval != ERROR_OK)
388 return retval;
389
390 bank->sectors[i].is_erased = 1;
391 }
392
393 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
394 if (retval != ERROR_OK)
395 return retval;
396
397 return ERROR_OK;
398 }
399
400 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
401 {
402 struct stm32x_flash_bank *stm32x_info = NULL;
403 struct target *target = bank->target;
404 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
405 int i, reg, bit;
406 int status;
407 uint32_t protection;
408
409 stm32x_info = bank->driver_priv;
410
411 if (target->state != TARGET_HALTED)
412 {
413 LOG_ERROR("Target not halted");
414 return ERROR_TARGET_NOT_HALTED;
415 }
416
417 if ((first && (first % stm32x_info->ppage_size)) || ((last + 1) &&
418 (last + 1) % stm32x_info->ppage_size))
419 {
420 LOG_WARNING("Error: start and end sectors must be on a %d sector boundary",
421 stm32x_info->ppage_size);
422 return ERROR_FLASH_SECTOR_INVALID;
423 }
424
425 /* medium density - each bit refers to a 4bank protection
426 * high density - each bit refers to a 2bank protection */
427 int retval = target_read_u32(target, STM32_FLASH_WRPR, &protection);
428 if (retval != ERROR_OK)
429 return retval;
430
431 prot_reg[0] = (uint16_t)protection;
432 prot_reg[1] = (uint16_t)(protection >> 8);
433 prot_reg[2] = (uint16_t)(protection >> 16);
434 prot_reg[3] = (uint16_t)(protection >> 24);
435
436 if (stm32x_info->ppage_size == 2)
437 {
438 /* high density flash */
439
440 /* bit 7 controls sector 62 - 255 protection */
441 if (last > 61)
442 {
443 if (set)
444 prot_reg[3] &= ~(1 << 7);
445 else
446 prot_reg[3] |= (1 << 7);
447 }
448
449 if (first > 61)
450 first = 62;
451 if (last > 61)
452 last = 61;
453
454 for (i = first; i <= last; i++)
455 {
456 reg = (i / stm32x_info->ppage_size) / 8;
457 bit = (i / stm32x_info->ppage_size) - (reg * 8);
458
459 if (set)
460 prot_reg[reg] &= ~(1 << bit);
461 else
462 prot_reg[reg] |= (1 << bit);
463 }
464 }
465 else
466 {
467 /* medium density flash */
468 for (i = first; i <= last; i++)
469 {
470 reg = (i / stm32x_info->ppage_size) / 8;
471 bit = (i / stm32x_info->ppage_size) - (reg * 8);
472
473 if (set)
474 prot_reg[reg] &= ~(1 << bit);
475 else
476 prot_reg[reg] |= (1 << bit);
477 }
478 }
479
480 if ((status = stm32x_erase_options(bank)) != ERROR_OK)
481 return status;
482
483 stm32x_info->option_bytes.protection[0] = prot_reg[0];
484 stm32x_info->option_bytes.protection[1] = prot_reg[1];
485 stm32x_info->option_bytes.protection[2] = prot_reg[2];
486 stm32x_info->option_bytes.protection[3] = prot_reg[3];
487
488 return stm32x_write_options(bank);
489 }
490
491 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
492 uint32_t offset, uint32_t count)
493 {
494 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
495 struct target *target = bank->target;
496 uint32_t buffer_size = 16384;
497 struct working_area *source;
498 uint32_t address = bank->base + offset;
499 struct reg_param reg_params[4];
500 struct armv7m_algorithm armv7m_info;
501 int retval = ERROR_OK;
502
503 /* see contib/loaders/flash/stm32x.s for src */
504
505 static const uint8_t stm32x_flash_write_code[] = {
506 /* write: */
507 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
508 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
509 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
510 0x23, 0x60, /* str r3, [r4, #0] */
511 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
512 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
513 /* busy: */
514 0x2B, 0x68, /* ldr r3, [r5, #0] */
515 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
516 0xFB, 0xD0, /* beq busy */
517 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
518 0x01, 0xD1, /* bne exit */
519 0x01, 0x3A, /* subs r2, r2, #1 */
520 0xED, 0xD1, /* bne write */
521 /* exit: */
522 0x00, 0xBE, /* bkpt #0 */
523 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
524 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
525 };
526
527 /* flash write code */
528 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
529 &stm32x_info->write_algorithm) != ERROR_OK)
530 {
531 LOG_WARNING("no working area available, can't do block memory writes");
532 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
533 };
534
535 if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address,
536 sizeof(stm32x_flash_write_code),
537 (uint8_t*)stm32x_flash_write_code)) != ERROR_OK)
538 return retval;
539
540 /* memory buffer */
541 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
542 {
543 buffer_size /= 2;
544 if (buffer_size <= 256)
545 {
546 /* if we already allocated the writing code, but failed to get a
547 * buffer, free the algorithm */
548 if (stm32x_info->write_algorithm)
549 target_free_working_area(target, stm32x_info->write_algorithm);
550
551 LOG_WARNING("no large enough working area available, can't do block memory writes");
552 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
553 }
554 };
555
556 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
557 armv7m_info.core_mode = ARMV7M_MODE_ANY;
558
559 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
560 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
561 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
562 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
563
564 while (count > 0)
565 {
566 uint32_t thisrun_count = (count > (buffer_size / 2)) ?
567 (buffer_size / 2) : count;
568
569 if ((retval = target_write_buffer(target, source->address,
570 thisrun_count * 2, buffer)) != ERROR_OK)
571 break;
572
573 buf_set_u32(reg_params[0].value, 0, 32, source->address);
574 buf_set_u32(reg_params[1].value, 0, 32, address);
575 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
576
577 if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params,
578 stm32x_info->write_algorithm->address,
579 0,
580 10000, &armv7m_info)) != ERROR_OK)
581 {
582 LOG_ERROR("error executing stm32x flash write algorithm");
583 break;
584 }
585
586 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_PGERR)
587 {
588 LOG_ERROR("flash memory not erased before writing");
589 /* Clear but report errors */
590 target_write_u32(target, STM32_FLASH_SR, FLASH_PGERR);
591 retval = ERROR_FAIL;
592 break;
593 }
594
595 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_WRPRTERR)
596 {
597 LOG_ERROR("flash memory write protected");
598 /* Clear but report errors */
599 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR);
600 retval = ERROR_FAIL;
601 break;
602 }
603
604 buffer += thisrun_count * 2;
605 address += thisrun_count * 2;
606 count -= thisrun_count;
607 }
608
609 target_free_working_area(target, source);
610 target_free_working_area(target, stm32x_info->write_algorithm);
611
612 destroy_reg_param(&reg_params[0]);
613 destroy_reg_param(&reg_params[1]);
614 destroy_reg_param(&reg_params[2]);
615 destroy_reg_param(&reg_params[3]);
616
617 return retval;
618 }
619
620 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
621 uint32_t offset, uint32_t count)
622 {
623 struct target *target = bank->target;
624 uint32_t words_remaining = (count / 2);
625 uint32_t bytes_remaining = (count & 0x00000001);
626 uint32_t address = bank->base + offset;
627 uint32_t bytes_written = 0;
628 int retval;
629
630 if (bank->target->state != TARGET_HALTED)
631 {
632 LOG_ERROR("Target not halted");
633 return ERROR_TARGET_NOT_HALTED;
634 }
635
636 if (offset & 0x1)
637 {
638 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
639 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
640 }
641
642 /* unlock flash registers */
643 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
644 if (retval != ERROR_OK)
645 return retval;
646 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
647 if (retval != ERROR_OK)
648 return retval;
649
650 /* multiple half words (2-byte) to be programmed? */
651 if (words_remaining > 0)
652 {
653 /* try using a block write */
654 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
655 {
656 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
657 {
658 /* if block write failed (no sufficient working area),
659 * we use normal (slow) single dword accesses */
660 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
661 }
662 }
663 else
664 {
665 buffer += words_remaining * 2;
666 address += words_remaining * 2;
667 words_remaining = 0;
668 }
669 }
670
671 while (words_remaining > 0)
672 {
673 uint16_t value;
674 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
675
676 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
677 if (retval != ERROR_OK)
678 return retval;
679 retval = target_write_u16(target, address, value);
680 if (retval != ERROR_OK)
681 return retval;
682
683 retval = stm32x_wait_status_busy(bank, 5);
684 if (retval != ERROR_OK)
685 return retval;
686
687 bytes_written += 2;
688 words_remaining--;
689 address += 2;
690 }
691
692 if (bytes_remaining)
693 {
694 uint16_t value = 0xffff;
695 memcpy(&value, buffer + bytes_written, bytes_remaining);
696
697 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
698 if (retval != ERROR_OK)
699 return retval;
700 retval = target_write_u16(target, address, value);
701 if (retval != ERROR_OK)
702 return retval;
703
704 retval = stm32x_wait_status_busy(bank, 5);
705 if (retval != ERROR_OK)
706 return retval;
707 }
708
709 return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
710 }
711
712 static int stm32x_probe(struct flash_bank *bank)
713 {
714 struct target *target = bank->target;
715 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
716 int i;
717 uint16_t num_pages;
718 uint32_t device_id;
719 int page_size;
720
721 stm32x_info->probed = 0;
722
723 /* read stm32 device id register */
724 int retval = target_read_u32(target, 0xE0042000, &device_id);
725 if (retval != ERROR_OK)
726 return retval;
727 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
728
729 /* get flash size from target. */
730 retval = target_read_u16(target, 0x1FFFF7E0, &num_pages);
731 if (retval != ERROR_OK)
732 {
733 LOG_WARNING("failed reading flash size, default to max target family");
734 /* failed reading flash size, default to max target family */
735 num_pages = 0xffff;
736 }
737
738 if ((device_id & 0x7ff) == 0x410)
739 {
740 /* medium density - we have 1k pages
741 * 4 pages for a protection area */
742 page_size = 1024;
743 stm32x_info->ppage_size = 4;
744
745 /* check for early silicon */
746 if (num_pages == 0xffff)
747 {
748 /* number of sectors incorrect on revA */
749 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
750 num_pages = 128;
751 }
752 }
753 else if ((device_id & 0x7ff) == 0x412)
754 {
755 /* low density - we have 1k pages
756 * 4 pages for a protection area */
757 page_size = 1024;
758 stm32x_info->ppage_size = 4;
759
760 /* check for early silicon */
761 if (num_pages == 0xffff)
762 {
763 /* number of sectors incorrect on revA */
764 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
765 num_pages = 32;
766 }
767 }
768 else if ((device_id & 0x7ff) == 0x414)
769 {
770 /* high density - we have 2k pages
771 * 2 pages for a protection area */
772 page_size = 2048;
773 stm32x_info->ppage_size = 2;
774
775 /* check for early silicon */
776 if (num_pages == 0xffff)
777 {
778 /* number of sectors incorrect on revZ */
779 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
780 num_pages = 512;
781 }
782 }
783 else if ((device_id & 0x7ff) == 0x418)
784 {
785 /* connectivity line density - we have 2k pages
786 * 2 pages for a protection area */
787 page_size = 2048;
788 stm32x_info->ppage_size = 2;
789
790 /* check for early silicon */
791 if (num_pages == 0xffff)
792 {
793 /* number of sectors incorrect on revZ */
794 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
795 num_pages = 256;
796 }
797 }
798 else if ((device_id & 0x7ff) == 0x420)
799 {
800 /* value line density - we have 1k pages
801 * 4 pages for a protection area */
802 page_size = 1024;
803 stm32x_info->ppage_size = 4;
804
805 /* check for early silicon */
806 if (num_pages == 0xffff)
807 {
808 /* number of sectors may be incorrrect on early silicon */
809 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
810 num_pages = 128;
811 }
812 }
813 else
814 {
815 LOG_WARNING("Cannot identify target as a STM32 family.");
816 return ERROR_FAIL;
817 }
818
819 LOG_INFO("flash size = %dkbytes", num_pages);
820
821 /* calculate numbers of pages */
822 num_pages /= (page_size / 1024);
823
824 if (bank->sectors)
825 {
826 free(bank->sectors);
827 bank->sectors = NULL;
828 }
829
830 bank->base = 0x08000000;
831 bank->size = (num_pages * page_size);
832 bank->num_sectors = num_pages;
833 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
834
835 for (i = 0; i < num_pages; i++)
836 {
837 bank->sectors[i].offset = i * page_size;
838 bank->sectors[i].size = page_size;
839 bank->sectors[i].is_erased = -1;
840 bank->sectors[i].is_protected = 1;
841 }
842
843 stm32x_info->probed = 1;
844
845 return ERROR_OK;
846 }
847
848 static int stm32x_auto_probe(struct flash_bank *bank)
849 {
850 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
851 if (stm32x_info->probed)
852 return ERROR_OK;
853 return stm32x_probe(bank);
854 }
855
856 #if 0
857 COMMAND_HANDLER(stm32x_handle_part_id_command)
858 {
859 return ERROR_OK;
860 }
861 #endif
862
863 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
864 {
865 struct target *target = bank->target;
866 uint32_t device_id;
867 int printed;
868
869 /* read stm32 device id register */
870 int retval = target_read_u32(target, 0xE0042000, &device_id);
871 if (retval != ERROR_OK)
872 return retval;
873
874 if ((device_id & 0x7ff) == 0x410)
875 {
876 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
877 buf += printed;
878 buf_size -= printed;
879
880 switch (device_id >> 16)
881 {
882 case 0x0000:
883 snprintf(buf, buf_size, "A");
884 break;
885
886 case 0x2000:
887 snprintf(buf, buf_size, "B");
888 break;
889
890 case 0x2001:
891 snprintf(buf, buf_size, "Z");
892 break;
893
894 case 0x2003:
895 snprintf(buf, buf_size, "Y");
896 break;
897
898 default:
899 snprintf(buf, buf_size, "unknown");
900 break;
901 }
902 }
903 else if ((device_id & 0x7ff) == 0x412)
904 {
905 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
906 buf += printed;
907 buf_size -= printed;
908
909 switch (device_id >> 16)
910 {
911 case 0x1000:
912 snprintf(buf, buf_size, "A");
913 break;
914
915 default:
916 snprintf(buf, buf_size, "unknown");
917 break;
918 }
919 }
920 else if ((device_id & 0x7ff) == 0x414)
921 {
922 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
923 buf += printed;
924 buf_size -= printed;
925
926 switch (device_id >> 16)
927 {
928 case 0x1000:
929 snprintf(buf, buf_size, "A");
930 break;
931
932 case 0x1001:
933 snprintf(buf, buf_size, "Z");
934 break;
935
936 default:
937 snprintf(buf, buf_size, "unknown");
938 break;
939 }
940 }
941 else if ((device_id & 0x7ff) == 0x418)
942 {
943 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
944 buf += printed;
945 buf_size -= printed;
946
947 switch (device_id >> 16)
948 {
949 case 0x1000:
950 snprintf(buf, buf_size, "A");
951 break;
952
953 case 0x1001:
954 snprintf(buf, buf_size, "Z");
955 break;
956
957 default:
958 snprintf(buf, buf_size, "unknown");
959 break;
960 }
961 }
962 else if ((device_id & 0x7ff) == 0x420)
963 {
964 printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
965 buf += printed;
966 buf_size -= printed;
967
968 switch (device_id >> 16)
969 {
970 case 0x1000:
971 snprintf(buf, buf_size, "A");
972 break;
973
974 case 0x1001:
975 snprintf(buf, buf_size, "Z");
976 break;
977
978 default:
979 snprintf(buf, buf_size, "unknown");
980 break;
981 }
982 }
983 else
984 {
985 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
986 return ERROR_FAIL;
987 }
988
989 return ERROR_OK;
990 }
991
992 COMMAND_HANDLER(stm32x_handle_lock_command)
993 {
994 struct target *target = NULL;
995 struct stm32x_flash_bank *stm32x_info = NULL;
996
997 if (CMD_ARGC < 1)
998 {
999 command_print(CMD_CTX, "stm32x lock <bank>");
1000 return ERROR_OK;
1001 }
1002
1003 struct flash_bank *bank;
1004 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1005 if (ERROR_OK != retval)
1006 return retval;
1007
1008 stm32x_info = bank->driver_priv;
1009
1010 target = bank->target;
1011
1012 if (target->state != TARGET_HALTED)
1013 {
1014 LOG_ERROR("Target not halted");
1015 return ERROR_TARGET_NOT_HALTED;
1016 }
1017
1018 if (stm32x_erase_options(bank) != ERROR_OK)
1019 {
1020 command_print(CMD_CTX, "stm32x failed to erase options");
1021 return ERROR_OK;
1022 }
1023
1024 /* set readout protection */
1025 stm32x_info->option_bytes.RDP = 0;
1026
1027 if (stm32x_write_options(bank) != ERROR_OK)
1028 {
1029 command_print(CMD_CTX, "stm32x failed to lock device");
1030 return ERROR_OK;
1031 }
1032
1033 command_print(CMD_CTX, "stm32x locked");
1034
1035 return ERROR_OK;
1036 }
1037
1038 COMMAND_HANDLER(stm32x_handle_unlock_command)
1039 {
1040 struct target *target = NULL;
1041 struct stm32x_flash_bank *stm32x_info = NULL;
1042
1043 if (CMD_ARGC < 1)
1044 {
1045 command_print(CMD_CTX, "stm32x unlock <bank>");
1046 return ERROR_OK;
1047 }
1048
1049 struct flash_bank *bank;
1050 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1051 if (ERROR_OK != retval)
1052 return retval;
1053
1054 stm32x_info = bank->driver_priv;
1055
1056 target = bank->target;
1057
1058 if (target->state != TARGET_HALTED)
1059 {
1060 LOG_ERROR("Target not halted");
1061 return ERROR_TARGET_NOT_HALTED;
1062 }
1063
1064 if (stm32x_erase_options(bank) != ERROR_OK)
1065 {
1066 command_print(CMD_CTX, "stm32x failed to unlock device");
1067 return ERROR_OK;
1068 }
1069
1070 if (stm32x_write_options(bank) != ERROR_OK)
1071 {
1072 command_print(CMD_CTX, "stm32x failed to lock device");
1073 return ERROR_OK;
1074 }
1075
1076 command_print(CMD_CTX, "stm32x unlocked.\n"
1077 "INFO: a reset or power cycle is required "
1078 "for the new settings to take effect.");
1079
1080 return ERROR_OK;
1081 }
1082
1083 COMMAND_HANDLER(stm32x_handle_options_read_command)
1084 {
1085 uint32_t optionbyte;
1086 struct target *target = NULL;
1087 struct stm32x_flash_bank *stm32x_info = NULL;
1088
1089 if (CMD_ARGC < 1)
1090 {
1091 command_print(CMD_CTX, "stm32x options_read <bank>");
1092 return ERROR_OK;
1093 }
1094
1095 struct flash_bank *bank;
1096 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1097 if (ERROR_OK != retval)
1098 return retval;
1099
1100 stm32x_info = bank->driver_priv;
1101
1102 target = bank->target;
1103
1104 if (target->state != TARGET_HALTED)
1105 {
1106 LOG_ERROR("Target not halted");
1107 return ERROR_TARGET_NOT_HALTED;
1108 }
1109
1110 retval = target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
1111 if (retval != ERROR_OK)
1112 return retval;
1113 command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1114
1115 if (buf_get_u32((uint8_t*)&optionbyte, OPT_ERROR, 1))
1116 command_print(CMD_CTX, "Option Byte Complement Error");
1117
1118 if (buf_get_u32((uint8_t*)&optionbyte, OPT_READOUT, 1))
1119 command_print(CMD_CTX, "Readout Protection On");
1120 else
1121 command_print(CMD_CTX, "Readout Protection Off");
1122
1123 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDWDGSW, 1))
1124 command_print(CMD_CTX, "Software Watchdog");
1125 else
1126 command_print(CMD_CTX, "Hardware Watchdog");
1127
1128 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTOP, 1))
1129 command_print(CMD_CTX, "Stop: No reset generated");
1130 else
1131 command_print(CMD_CTX, "Stop: Reset generated");
1132
1133 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTDBY, 1))
1134 command_print(CMD_CTX, "Standby: No reset generated");
1135 else
1136 command_print(CMD_CTX, "Standby: Reset generated");
1137
1138 return ERROR_OK;
1139 }
1140
1141 COMMAND_HANDLER(stm32x_handle_options_write_command)
1142 {
1143 struct target *target = NULL;
1144 struct stm32x_flash_bank *stm32x_info = NULL;
1145 uint16_t optionbyte = 0xF8;
1146
1147 if (CMD_ARGC < 4)
1148 {
1149 command_print(CMD_CTX, "stm32x options_write <bank> <SWWDG | HWWDG> <RSTSTNDBY | NORSTSTNDBY> <RSTSTOP | NORSTSTOP>");
1150 return ERROR_OK;
1151 }
1152
1153 struct flash_bank *bank;
1154 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1155 if (ERROR_OK != retval)
1156 return retval;
1157
1158 stm32x_info = bank->driver_priv;
1159
1160 target = bank->target;
1161
1162 if (target->state != TARGET_HALTED)
1163 {
1164 LOG_ERROR("Target not halted");
1165 return ERROR_TARGET_NOT_HALTED;
1166 }
1167
1168 /* REVISIT: ignores some options which we will display...
1169 * and doesn't insist on the specified syntax.
1170 */
1171
1172 /* OPT_RDWDGSW */
1173 if (strcmp(CMD_ARGV[1], "SWWDG") == 0)
1174 {
1175 optionbyte |= (1 << 0);
1176 }
1177 else /* REVISIT must be "HWWDG" then ... */
1178 {
1179 optionbyte &= ~(1 << 0);
1180 }
1181
1182 /* OPT_RDRSTSTDBY */
1183 if (strcmp(CMD_ARGV[2], "NORSTSTNDBY") == 0)
1184 {
1185 optionbyte |= (1 << 1);
1186 }
1187 else /* REVISIT must be "RSTSTNDBY" then ... */
1188 {
1189 optionbyte &= ~(1 << 1);
1190 }
1191
1192 /* OPT_RDRSTSTOP */
1193 if (strcmp(CMD_ARGV[3], "NORSTSTOP") == 0)
1194 {
1195 optionbyte |= (1 << 2);
1196 }
1197 else /* REVISIT must be "RSTSTOP" then ... */
1198 {
1199 optionbyte &= ~(1 << 2);
1200 }
1201
1202 if (stm32x_erase_options(bank) != ERROR_OK)
1203 {
1204 command_print(CMD_CTX, "stm32x failed to erase options");
1205 return ERROR_OK;
1206 }
1207
1208 stm32x_info->option_bytes.user_options = optionbyte;
1209
1210 if (stm32x_write_options(bank) != ERROR_OK)
1211 {
1212 command_print(CMD_CTX, "stm32x failed to write options");
1213 return ERROR_OK;
1214 }
1215
1216 command_print(CMD_CTX, "stm32x write options complete.\n"
1217 "INFO: a reset or power cycle is required "
1218 "for the new settings to take effect.");
1219
1220 return ERROR_OK;
1221 }
1222
1223 static int stm32x_mass_erase(struct flash_bank *bank)
1224 {
1225 struct target *target = bank->target;
1226
1227 if (target->state != TARGET_HALTED)
1228 {
1229 LOG_ERROR("Target not halted");
1230 return ERROR_TARGET_NOT_HALTED;
1231 }
1232
1233 /* unlock option flash registers */
1234 int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
1235 if (retval != ERROR_OK)
1236 return retval;
1237 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
1238 if (retval != ERROR_OK)
1239 return retval;
1240
1241 /* mass erase flash memory */
1242 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
1243 if (retval != ERROR_OK)
1244 return retval;
1245 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_MER | FLASH_STRT);
1246 if (retval != ERROR_OK)
1247 return retval;
1248
1249 retval = stm32x_wait_status_busy(bank, 100);
1250 if (retval != ERROR_OK)
1251 return retval;
1252
1253 retval = target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
1254 if (retval != ERROR_OK)
1255 return retval;
1256
1257 return ERROR_OK;
1258 }
1259
1260 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1261 {
1262 int i;
1263
1264 if (CMD_ARGC < 1)
1265 {
1266 command_print(CMD_CTX, "stm32x mass_erase <bank>");
1267 return ERROR_OK;
1268 }
1269
1270 struct flash_bank *bank;
1271 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1272 if (ERROR_OK != retval)
1273 return retval;
1274
1275 retval = stm32x_mass_erase(bank);
1276 if (retval == ERROR_OK)
1277 {
1278 /* set all sectors as erased */
1279 for (i = 0; i < bank->num_sectors; i++)
1280 {
1281 bank->sectors[i].is_erased = 1;
1282 }
1283
1284 command_print(CMD_CTX, "stm32x mass erase complete");
1285 }
1286 else
1287 {
1288 command_print(CMD_CTX, "stm32x mass erase failed");
1289 }
1290
1291 return retval;
1292 }
1293
1294 static const struct command_registration stm32x_exec_command_handlers[] = {
1295 {
1296 .name = "lock",
1297 .handler = stm32x_handle_lock_command,
1298 .mode = COMMAND_EXEC,
1299 .usage = "bank_id",
1300 .help = "Lock entire flash device.",
1301 },
1302 {
1303 .name = "unlock",
1304 .handler = stm32x_handle_unlock_command,
1305 .mode = COMMAND_EXEC,
1306 .usage = "bank_id",
1307 .help = "Unlock entire protected flash device.",
1308 },
1309 {
1310 .name = "mass_erase",
1311 .handler = stm32x_handle_mass_erase_command,
1312 .mode = COMMAND_EXEC,
1313 .usage = "bank_id",
1314 .help = "Erase entire flash device.",
1315 },
1316 {
1317 .name = "options_read",
1318 .handler = stm32x_handle_options_read_command,
1319 .mode = COMMAND_EXEC,
1320 .usage = "bank_id",
1321 .help = "Read and display device option byte.",
1322 },
1323 {
1324 .name = "options_write",
1325 .handler = stm32x_handle_options_write_command,
1326 .mode = COMMAND_EXEC,
1327 .usage = "bank_id ('SWWDG'|'HWWDG') "
1328 "('RSTSTNDBY'|'NORSTSTNDBY') "
1329 "('RSTSTOP'|'NORSTSTOP')",
1330 .help = "Replace bits in device option byte.",
1331 },
1332 COMMAND_REGISTRATION_DONE
1333 };
1334
1335 static const struct command_registration stm32x_command_handlers[] = {
1336 {
1337 .name = "stm32x",
1338 .mode = COMMAND_ANY,
1339 .help = "stm32x flash command group",
1340 .chain = stm32x_exec_command_handlers,
1341 },
1342 COMMAND_REGISTRATION_DONE
1343 };
1344
1345 struct flash_driver stm32x_flash = {
1346 .name = "stm32x",
1347 .commands = stm32x_command_handlers,
1348 .flash_bank_command = stm32x_flash_bank_command,
1349 .erase = stm32x_erase,
1350 .protect = stm32x_protect,
1351 .write = stm32x_write,
1352 .read = default_flash_read,
1353 .probe = stm32x_probe,
1354 .auto_probe = stm32x_auto_probe,
1355 .erase_check = default_flash_mem_blank_check,
1356 .protect_check = stm32x_protect_check,
1357 .info = get_stm32x_info,
1358 };
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)