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stm32: sharpen error handling for timeouts
[openocd.git] / src / flash / nor / stm32x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "imp.h"
28 #include "stm32x.h"
29 #include <helper/binarybuffer.h>
30 #include <target/algorithm.h>
31 #include <target/armv7m.h>
32
33
34 static int stm32x_mass_erase(struct flash_bank *bank);
35
36 /* flash bank stm32x <base> <size> 0 0 <target#>
37 */
38 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
39 {
40 struct stm32x_flash_bank *stm32x_info;
41
42 if (CMD_ARGC < 6)
43 {
44 LOG_WARNING("incomplete flash_bank stm32x configuration");
45 return ERROR_FLASH_BANK_INVALID;
46 }
47
48 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
49 bank->driver_priv = stm32x_info;
50
51 stm32x_info->write_algorithm = NULL;
52 stm32x_info->probed = 0;
53
54 return ERROR_OK;
55 }
56
57 static int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
58 {
59 struct target *target = bank->target;
60 return target_read_u32(target, STM32_FLASH_SR, status);
61 }
62
63 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
64 {
65 struct target *target = bank->target;
66 uint32_t status;
67 int retval = ERROR_OK;
68
69 /* wait for busy to clear */
70 for (;;)
71 {
72 retval = stm32x_get_flash_status(bank, &status);
73 if (retval != ERROR_OK)
74 return retval;
75 LOG_DEBUG("status: 0x%" PRIx32 "", status);
76 if ((status & FLASH_BSY) == 0)
77 break;
78 if (timeout-- <= 0)
79 {
80 LOG_ERROR("timed out waiting for flash");
81 return ERROR_FAIL;
82 }
83 alive_sleep(1);
84 }
85
86 if (status & FLASH_WRPRTERR)
87 {
88 LOG_ERROR("stm32x device protected");
89 retval = ERROR_FAIL;
90 }
91
92 if (status & FLASH_PGERR)
93 {
94 LOG_ERROR("stm32x device programming failed");
95 retval = ERROR_FAIL;
96 }
97
98 /* Clear but report errors */
99 if (status & (FLASH_WRPRTERR | FLASH_PGERR))
100 {
101 /* If this operation fails, we ignore it and report the original
102 * retval
103 */
104 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR | FLASH_PGERR);
105 }
106 return retval;
107 }
108
109 static int stm32x_read_options(struct flash_bank *bank)
110 {
111 uint32_t optiondata;
112 struct stm32x_flash_bank *stm32x_info = NULL;
113 struct target *target = bank->target;
114
115 stm32x_info = bank->driver_priv;
116
117 /* read current option bytes */
118 target_read_u32(target, STM32_FLASH_OBR, &optiondata);
119
120 stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
121 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
122
123 if (optiondata & (1 << OPT_READOUT))
124 LOG_INFO("Device Security Bit Set");
125
126 /* each bit refers to a 4bank protection */
127 target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
128
129 stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
130 stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
131 stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
132 stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
133
134 return ERROR_OK;
135 }
136
137 static int stm32x_erase_options(struct flash_bank *bank)
138 {
139 struct stm32x_flash_bank *stm32x_info = NULL;
140 struct target *target = bank->target;
141
142 stm32x_info = bank->driver_priv;
143
144 /* read current options */
145 stm32x_read_options(bank);
146
147 /* unlock flash registers */
148 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
149 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
150
151 /* unlock option flash registers */
152 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
153 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
154
155 /* erase option bytes */
156 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_OPTWRE);
157 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
158
159 int retval = stm32x_wait_status_busy(bank, 10);
160 if (retval != ERROR_OK)
161 return retval;
162
163 /* clear readout protection and complementary option bytes
164 * this will also force a device unlock if set */
165 stm32x_info->option_bytes.RDP = 0x5AA5;
166
167 return ERROR_OK;
168 }
169
170 static int stm32x_write_options(struct flash_bank *bank)
171 {
172 struct stm32x_flash_bank *stm32x_info = NULL;
173 struct target *target = bank->target;
174
175 stm32x_info = bank->driver_priv;
176
177 /* unlock flash registers */
178 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
179 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
180
181 /* unlock option flash registers */
182 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
183 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
184
185 /* program option bytes */
186 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG | FLASH_OPTWRE);
187
188 /* write user option byte */
189 target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
190
191 int retval = stm32x_wait_status_busy(bank, 10);
192 if (retval != ERROR_OK)
193 return retval;
194
195 /* write protection byte 1 */
196 target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
197
198 retval = stm32x_wait_status_busy(bank, 10);
199 if (retval != ERROR_OK)
200 return retval;
201
202 /* write protection byte 2 */
203 target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
204
205 retval = stm32x_wait_status_busy(bank, 10);
206 if (retval != ERROR_OK)
207 return retval;
208
209 /* write protection byte 3 */
210 target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
211
212 retval = stm32x_wait_status_busy(bank, 10);
213 if (retval != ERROR_OK)
214 return retval;
215
216 /* write protection byte 4 */
217 target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
218
219 retval = stm32x_wait_status_busy(bank, 10);
220 if (retval != ERROR_OK)
221 return retval;
222
223 /* write readout protection bit */
224 target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
225
226 retval = stm32x_wait_status_busy(bank, 10);
227 if (retval != ERROR_OK)
228 return retval;
229
230 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
231
232 return ERROR_OK;
233 }
234
235 static int stm32x_protect_check(struct flash_bank *bank)
236 {
237 struct target *target = bank->target;
238 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
239
240 uint32_t protection;
241 int i, s;
242 int num_bits;
243 int set;
244
245 if (target->state != TARGET_HALTED)
246 {
247 LOG_ERROR("Target not halted");
248 return ERROR_TARGET_NOT_HALTED;
249 }
250
251 /* medium density - each bit refers to a 4bank protection
252 * high density - each bit refers to a 2bank protection */
253 target_read_u32(target, STM32_FLASH_WRPR, &protection);
254
255 /* medium density - each protection bit is for 4 * 1K pages
256 * high density - each protection bit is for 2 * 2K pages */
257 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
258
259 if (stm32x_info->ppage_size == 2)
260 {
261 /* high density flash/connectivity line protection */
262
263 set = 1;
264
265 if (protection & (1 << 31))
266 set = 0;
267
268 /* bit 31 controls sector 62 - 255 protection for high density
269 * bit 31 controls sector 62 - 127 protection for connectivity line */
270 for (s = 62; s < bank->num_sectors; s++)
271 {
272 bank->sectors[s].is_protected = set;
273 }
274
275 if (bank->num_sectors > 61)
276 num_bits = 31;
277
278 for (i = 0; i < num_bits; i++)
279 {
280 set = 1;
281
282 if (protection & (1 << i))
283 set = 0;
284
285 for (s = 0; s < stm32x_info->ppage_size; s++)
286 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
287 }
288 }
289 else
290 {
291 /* low/medium density flash protection */
292 for (i = 0; i < num_bits; i++)
293 {
294 set = 1;
295
296 if (protection & (1 << i))
297 set = 0;
298
299 for (s = 0; s < stm32x_info->ppage_size; s++)
300 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
301 }
302 }
303
304 return ERROR_OK;
305 }
306
307 static int stm32x_erase(struct flash_bank *bank, int first, int last)
308 {
309 struct target *target = bank->target;
310 int i;
311
312 if (bank->target->state != TARGET_HALTED)
313 {
314 LOG_ERROR("Target not halted");
315 return ERROR_TARGET_NOT_HALTED;
316 }
317
318 if ((first == 0) && (last == (bank->num_sectors - 1)))
319 {
320 return stm32x_mass_erase(bank);
321 }
322
323 /* unlock flash registers */
324 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
325 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
326
327 for (i = first; i <= last; i++)
328 {
329 target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
330 target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
331 target_write_u32(target, STM32_FLASH_CR, FLASH_PER | FLASH_STRT);
332
333 int retval = stm32x_wait_status_busy(bank, 100);
334 if (retval != ERROR_OK)
335 return retval;
336
337 bank->sectors[i].is_erased = 1;
338 }
339
340 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
341
342 return ERROR_OK;
343 }
344
345 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
346 {
347 struct stm32x_flash_bank *stm32x_info = NULL;
348 struct target *target = bank->target;
349 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
350 int i, reg, bit;
351 int status;
352 uint32_t protection;
353
354 stm32x_info = bank->driver_priv;
355
356 if (target->state != TARGET_HALTED)
357 {
358 LOG_ERROR("Target not halted");
359 return ERROR_TARGET_NOT_HALTED;
360 }
361
362 if ((first && (first % stm32x_info->ppage_size)) || ((last + 1) &&
363 (last + 1) % stm32x_info->ppage_size))
364 {
365 LOG_WARNING("Error: start and end sectors must be on a %d sector boundary",
366 stm32x_info->ppage_size);
367 return ERROR_FLASH_SECTOR_INVALID;
368 }
369
370 /* medium density - each bit refers to a 4bank protection
371 * high density - each bit refers to a 2bank protection */
372 target_read_u32(target, STM32_FLASH_WRPR, &protection);
373
374 prot_reg[0] = (uint16_t)protection;
375 prot_reg[1] = (uint16_t)(protection >> 8);
376 prot_reg[2] = (uint16_t)(protection >> 16);
377 prot_reg[3] = (uint16_t)(protection >> 24);
378
379 if (stm32x_info->ppage_size == 2)
380 {
381 /* high density flash */
382
383 /* bit 7 controls sector 62 - 255 protection */
384 if (last > 61)
385 {
386 if (set)
387 prot_reg[3] &= ~(1 << 7);
388 else
389 prot_reg[3] |= (1 << 7);
390 }
391
392 if (first > 61)
393 first = 62;
394 if (last > 61)
395 last = 61;
396
397 for (i = first; i <= last; i++)
398 {
399 reg = (i / stm32x_info->ppage_size) / 8;
400 bit = (i / stm32x_info->ppage_size) - (reg * 8);
401
402 if (set)
403 prot_reg[reg] &= ~(1 << bit);
404 else
405 prot_reg[reg] |= (1 << bit);
406 }
407 }
408 else
409 {
410 /* medium density flash */
411 for (i = first; i <= last; i++)
412 {
413 reg = (i / stm32x_info->ppage_size) / 8;
414 bit = (i / stm32x_info->ppage_size) - (reg * 8);
415
416 if (set)
417 prot_reg[reg] &= ~(1 << bit);
418 else
419 prot_reg[reg] |= (1 << bit);
420 }
421 }
422
423 if ((status = stm32x_erase_options(bank)) != ERROR_OK)
424 return status;
425
426 stm32x_info->option_bytes.protection[0] = prot_reg[0];
427 stm32x_info->option_bytes.protection[1] = prot_reg[1];
428 stm32x_info->option_bytes.protection[2] = prot_reg[2];
429 stm32x_info->option_bytes.protection[3] = prot_reg[3];
430
431 return stm32x_write_options(bank);
432 }
433
434 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
435 uint32_t offset, uint32_t count)
436 {
437 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
438 struct target *target = bank->target;
439 uint32_t buffer_size = 16384;
440 struct working_area *source;
441 uint32_t address = bank->base + offset;
442 struct reg_param reg_params[4];
443 struct armv7m_algorithm armv7m_info;
444 int retval = ERROR_OK;
445
446 /* see contib/loaders/flash/stm32x.s for src */
447
448 static const uint8_t stm32x_flash_write_code[] = {
449 /* write: */
450 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
451 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
452 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
453 0x23, 0x60, /* str r3, [r4, #0] */
454 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
455 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
456 /* busy: */
457 0x2B, 0x68, /* ldr r3, [r5, #0] */
458 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
459 0xFB, 0xD0, /* beq busy */
460 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
461 0x01, 0xD1, /* bne exit */
462 0x01, 0x3A, /* subs r2, r2, #1 */
463 0xED, 0xD1, /* bne write */
464 /* exit: */
465 0x00, 0xBE, /* bkpt #0 */
466 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
467 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
468 };
469
470 /* flash write code */
471 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
472 &stm32x_info->write_algorithm) != ERROR_OK)
473 {
474 LOG_WARNING("no working area available, can't do block memory writes");
475 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
476 };
477
478 if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address,
479 sizeof(stm32x_flash_write_code),
480 (uint8_t*)stm32x_flash_write_code)) != ERROR_OK)
481 return retval;
482
483 /* memory buffer */
484 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
485 {
486 buffer_size /= 2;
487 if (buffer_size <= 256)
488 {
489 /* if we already allocated the writing code, but failed to get a
490 * buffer, free the algorithm */
491 if (stm32x_info->write_algorithm)
492 target_free_working_area(target, stm32x_info->write_algorithm);
493
494 LOG_WARNING("no large enough working area available, can't do block memory writes");
495 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
496 }
497 };
498
499 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
500 armv7m_info.core_mode = ARMV7M_MODE_ANY;
501
502 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
503 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
504 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
505 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
506
507 while (count > 0)
508 {
509 uint32_t thisrun_count = (count > (buffer_size / 2)) ?
510 (buffer_size / 2) : count;
511
512 if ((retval = target_write_buffer(target, source->address,
513 thisrun_count * 2, buffer)) != ERROR_OK)
514 break;
515
516 buf_set_u32(reg_params[0].value, 0, 32, source->address);
517 buf_set_u32(reg_params[1].value, 0, 32, address);
518 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
519
520 if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params,
521 stm32x_info->write_algorithm->address,
522 0,
523 10000, &armv7m_info)) != ERROR_OK)
524 {
525 LOG_ERROR("error executing stm32x flash write algorithm");
526 break;
527 }
528
529 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_PGERR)
530 {
531 LOG_ERROR("flash memory not erased before writing");
532 /* Clear but report errors */
533 target_write_u32(target, STM32_FLASH_SR, FLASH_PGERR);
534 retval = ERROR_FAIL;
535 break;
536 }
537
538 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_WRPRTERR)
539 {
540 LOG_ERROR("flash memory write protected");
541 /* Clear but report errors */
542 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR);
543 retval = ERROR_FAIL;
544 break;
545 }
546
547 buffer += thisrun_count * 2;
548 address += thisrun_count * 2;
549 count -= thisrun_count;
550 }
551
552 target_free_working_area(target, source);
553 target_free_working_area(target, stm32x_info->write_algorithm);
554
555 destroy_reg_param(&reg_params[0]);
556 destroy_reg_param(&reg_params[1]);
557 destroy_reg_param(&reg_params[2]);
558 destroy_reg_param(&reg_params[3]);
559
560 return retval;
561 }
562
563 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
564 uint32_t offset, uint32_t count)
565 {
566 struct target *target = bank->target;
567 uint32_t words_remaining = (count / 2);
568 uint32_t bytes_remaining = (count & 0x00000001);
569 uint32_t address = bank->base + offset;
570 uint32_t bytes_written = 0;
571 int retval;
572
573 if (bank->target->state != TARGET_HALTED)
574 {
575 LOG_ERROR("Target not halted");
576 return ERROR_TARGET_NOT_HALTED;
577 }
578
579 if (offset & 0x1)
580 {
581 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
582 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
583 }
584
585 /* unlock flash registers */
586 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
587 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
588
589 /* multiple half words (2-byte) to be programmed? */
590 if (words_remaining > 0)
591 {
592 /* try using a block write */
593 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
594 {
595 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
596 {
597 /* if block write failed (no sufficient working area),
598 * we use normal (slow) single dword accesses */
599 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
600 }
601 }
602 else
603 {
604 buffer += words_remaining * 2;
605 address += words_remaining * 2;
606 words_remaining = 0;
607 }
608 }
609
610 while (words_remaining > 0)
611 {
612 uint16_t value;
613 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
614
615 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
616 target_write_u16(target, address, value);
617
618 retval = stm32x_wait_status_busy(bank, 5);
619 if (retval != ERROR_OK)
620 return retval;
621
622 bytes_written += 2;
623 words_remaining--;
624 address += 2;
625 }
626
627 if (bytes_remaining)
628 {
629 uint16_t value = 0xffff;
630 memcpy(&value, buffer + bytes_written, bytes_remaining);
631
632 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
633 target_write_u16(target, address, value);
634
635 retval = stm32x_wait_status_busy(bank, 5);
636 if (retval != ERROR_OK)
637 return retval;
638 }
639
640 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
641
642 return ERROR_OK;
643 }
644
645 static int stm32x_probe(struct flash_bank *bank)
646 {
647 struct target *target = bank->target;
648 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
649 int i;
650 uint16_t num_pages;
651 uint32_t device_id;
652 int page_size;
653
654 stm32x_info->probed = 0;
655
656 /* read stm32 device id register */
657 target_read_u32(target, 0xE0042000, &device_id);
658 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
659
660 /* get flash size from target */
661 if (target_read_u16(target, 0x1FFFF7E0, &num_pages) != ERROR_OK)
662 {
663 /* failed reading flash size, default to max target family */
664 num_pages = 0xffff;
665 }
666
667 if ((device_id & 0x7ff) == 0x410)
668 {
669 /* medium density - we have 1k pages
670 * 4 pages for a protection area */
671 page_size = 1024;
672 stm32x_info->ppage_size = 4;
673
674 /* check for early silicon */
675 if (num_pages == 0xffff)
676 {
677 /* number of sectors incorrect on revA */
678 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
679 num_pages = 128;
680 }
681 }
682 else if ((device_id & 0x7ff) == 0x412)
683 {
684 /* low density - we have 1k pages
685 * 4 pages for a protection area */
686 page_size = 1024;
687 stm32x_info->ppage_size = 4;
688
689 /* check for early silicon */
690 if (num_pages == 0xffff)
691 {
692 /* number of sectors incorrect on revA */
693 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
694 num_pages = 32;
695 }
696 }
697 else if ((device_id & 0x7ff) == 0x414)
698 {
699 /* high density - we have 2k pages
700 * 2 pages for a protection area */
701 page_size = 2048;
702 stm32x_info->ppage_size = 2;
703
704 /* check for early silicon */
705 if (num_pages == 0xffff)
706 {
707 /* number of sectors incorrect on revZ */
708 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
709 num_pages = 512;
710 }
711 }
712 else if ((device_id & 0x7ff) == 0x418)
713 {
714 /* connectivity line density - we have 2k pages
715 * 2 pages for a protection area */
716 page_size = 2048;
717 stm32x_info->ppage_size = 2;
718
719 /* check for early silicon */
720 if (num_pages == 0xffff)
721 {
722 /* number of sectors incorrect on revZ */
723 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
724 num_pages = 256;
725 }
726 }
727 else if ((device_id & 0x7ff) == 0x420)
728 {
729 /* value line density - we have 1k pages
730 * 4 pages for a protection area */
731 page_size = 1024;
732 stm32x_info->ppage_size = 4;
733
734 /* check for early silicon */
735 if (num_pages == 0xffff)
736 {
737 /* number of sectors may be incorrrect on early silicon */
738 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
739 num_pages = 128;
740 }
741 }
742 else
743 {
744 LOG_WARNING("Cannot identify target as a STM32 family.");
745 return ERROR_FAIL;
746 }
747
748 LOG_INFO("flash size = %dkbytes", num_pages);
749
750 /* calculate numbers of pages */
751 num_pages /= (page_size / 1024);
752
753 if (bank->sectors)
754 {
755 free(bank->sectors);
756 bank->sectors = NULL;
757 }
758
759 bank->base = 0x08000000;
760 bank->size = (num_pages * page_size);
761 bank->num_sectors = num_pages;
762 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
763
764 for (i = 0; i < num_pages; i++)
765 {
766 bank->sectors[i].offset = i * page_size;
767 bank->sectors[i].size = page_size;
768 bank->sectors[i].is_erased = -1;
769 bank->sectors[i].is_protected = 1;
770 }
771
772 stm32x_info->probed = 1;
773
774 return ERROR_OK;
775 }
776
777 static int stm32x_auto_probe(struct flash_bank *bank)
778 {
779 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
780 if (stm32x_info->probed)
781 return ERROR_OK;
782 return stm32x_probe(bank);
783 }
784
785 #if 0
786 COMMAND_HANDLER(stm32x_handle_part_id_command)
787 {
788 return ERROR_OK;
789 }
790 #endif
791
792 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
793 {
794 struct target *target = bank->target;
795 uint32_t device_id;
796 int printed;
797
798 /* read stm32 device id register */
799 target_read_u32(target, 0xE0042000, &device_id);
800
801 if ((device_id & 0x7ff) == 0x410)
802 {
803 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
804 buf += printed;
805 buf_size -= printed;
806
807 switch (device_id >> 16)
808 {
809 case 0x0000:
810 snprintf(buf, buf_size, "A");
811 break;
812
813 case 0x2000:
814 snprintf(buf, buf_size, "B");
815 break;
816
817 case 0x2001:
818 snprintf(buf, buf_size, "Z");
819 break;
820
821 case 0x2003:
822 snprintf(buf, buf_size, "Y");
823 break;
824
825 default:
826 snprintf(buf, buf_size, "unknown");
827 break;
828 }
829 }
830 else if ((device_id & 0x7ff) == 0x412)
831 {
832 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
833 buf += printed;
834 buf_size -= printed;
835
836 switch (device_id >> 16)
837 {
838 case 0x1000:
839 snprintf(buf, buf_size, "A");
840 break;
841
842 default:
843 snprintf(buf, buf_size, "unknown");
844 break;
845 }
846 }
847 else if ((device_id & 0x7ff) == 0x414)
848 {
849 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
850 buf += printed;
851 buf_size -= printed;
852
853 switch (device_id >> 16)
854 {
855 case 0x1000:
856 snprintf(buf, buf_size, "A");
857 break;
858
859 case 0x1001:
860 snprintf(buf, buf_size, "Z");
861 break;
862
863 default:
864 snprintf(buf, buf_size, "unknown");
865 break;
866 }
867 }
868 else if ((device_id & 0x7ff) == 0x418)
869 {
870 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
871 buf += printed;
872 buf_size -= printed;
873
874 switch (device_id >> 16)
875 {
876 case 0x1000:
877 snprintf(buf, buf_size, "A");
878 break;
879
880 case 0x1001:
881 snprintf(buf, buf_size, "Z");
882 break;
883
884 default:
885 snprintf(buf, buf_size, "unknown");
886 break;
887 }
888 }
889 else if ((device_id & 0x7ff) == 0x420)
890 {
891 printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
892 buf += printed;
893 buf_size -= printed;
894
895 switch (device_id >> 16)
896 {
897 case 0x1000:
898 snprintf(buf, buf_size, "A");
899 break;
900
901 case 0x1001:
902 snprintf(buf, buf_size, "Z");
903 break;
904
905 default:
906 snprintf(buf, buf_size, "unknown");
907 break;
908 }
909 }
910 else
911 {
912 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
913 return ERROR_FAIL;
914 }
915
916 return ERROR_OK;
917 }
918
919 COMMAND_HANDLER(stm32x_handle_lock_command)
920 {
921 struct target *target = NULL;
922 struct stm32x_flash_bank *stm32x_info = NULL;
923
924 if (CMD_ARGC < 1)
925 {
926 command_print(CMD_CTX, "stm32x lock <bank>");
927 return ERROR_OK;
928 }
929
930 struct flash_bank *bank;
931 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
932 if (ERROR_OK != retval)
933 return retval;
934
935 stm32x_info = bank->driver_priv;
936
937 target = bank->target;
938
939 if (target->state != TARGET_HALTED)
940 {
941 LOG_ERROR("Target not halted");
942 return ERROR_TARGET_NOT_HALTED;
943 }
944
945 if (stm32x_erase_options(bank) != ERROR_OK)
946 {
947 command_print(CMD_CTX, "stm32x failed to erase options");
948 return ERROR_OK;
949 }
950
951 /* set readout protection */
952 stm32x_info->option_bytes.RDP = 0;
953
954 if (stm32x_write_options(bank) != ERROR_OK)
955 {
956 command_print(CMD_CTX, "stm32x failed to lock device");
957 return ERROR_OK;
958 }
959
960 command_print(CMD_CTX, "stm32x locked");
961
962 return ERROR_OK;
963 }
964
965 COMMAND_HANDLER(stm32x_handle_unlock_command)
966 {
967 struct target *target = NULL;
968 struct stm32x_flash_bank *stm32x_info = NULL;
969
970 if (CMD_ARGC < 1)
971 {
972 command_print(CMD_CTX, "stm32x unlock <bank>");
973 return ERROR_OK;
974 }
975
976 struct flash_bank *bank;
977 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
978 if (ERROR_OK != retval)
979 return retval;
980
981 stm32x_info = bank->driver_priv;
982
983 target = bank->target;
984
985 if (target->state != TARGET_HALTED)
986 {
987 LOG_ERROR("Target not halted");
988 return ERROR_TARGET_NOT_HALTED;
989 }
990
991 if (stm32x_erase_options(bank) != ERROR_OK)
992 {
993 command_print(CMD_CTX, "stm32x failed to unlock device");
994 return ERROR_OK;
995 }
996
997 if (stm32x_write_options(bank) != ERROR_OK)
998 {
999 command_print(CMD_CTX, "stm32x failed to lock device");
1000 return ERROR_OK;
1001 }
1002
1003 command_print(CMD_CTX, "stm32x unlocked.\n"
1004 "INFO: a reset or power cycle is required "
1005 "for the new settings to take effect.");
1006
1007 return ERROR_OK;
1008 }
1009
1010 COMMAND_HANDLER(stm32x_handle_options_read_command)
1011 {
1012 uint32_t optionbyte;
1013 struct target *target = NULL;
1014 struct stm32x_flash_bank *stm32x_info = NULL;
1015
1016 if (CMD_ARGC < 1)
1017 {
1018 command_print(CMD_CTX, "stm32x options_read <bank>");
1019 return ERROR_OK;
1020 }
1021
1022 struct flash_bank *bank;
1023 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1024 if (ERROR_OK != retval)
1025 return retval;
1026
1027 stm32x_info = bank->driver_priv;
1028
1029 target = bank->target;
1030
1031 if (target->state != TARGET_HALTED)
1032 {
1033 LOG_ERROR("Target not halted");
1034 return ERROR_TARGET_NOT_HALTED;
1035 }
1036
1037 target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
1038 command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1039
1040 if (buf_get_u32((uint8_t*)&optionbyte, OPT_ERROR, 1))
1041 command_print(CMD_CTX, "Option Byte Complement Error");
1042
1043 if (buf_get_u32((uint8_t*)&optionbyte, OPT_READOUT, 1))
1044 command_print(CMD_CTX, "Readout Protection On");
1045 else
1046 command_print(CMD_CTX, "Readout Protection Off");
1047
1048 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDWDGSW, 1))
1049 command_print(CMD_CTX, "Software Watchdog");
1050 else
1051 command_print(CMD_CTX, "Hardware Watchdog");
1052
1053 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTOP, 1))
1054 command_print(CMD_CTX, "Stop: No reset generated");
1055 else
1056 command_print(CMD_CTX, "Stop: Reset generated");
1057
1058 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTDBY, 1))
1059 command_print(CMD_CTX, "Standby: No reset generated");
1060 else
1061 command_print(CMD_CTX, "Standby: Reset generated");
1062
1063 return ERROR_OK;
1064 }
1065
1066 COMMAND_HANDLER(stm32x_handle_options_write_command)
1067 {
1068 struct target *target = NULL;
1069 struct stm32x_flash_bank *stm32x_info = NULL;
1070 uint16_t optionbyte = 0xF8;
1071
1072 if (CMD_ARGC < 4)
1073 {
1074 command_print(CMD_CTX, "stm32x options_write <bank> <SWWDG | HWWDG> <RSTSTNDBY | NORSTSTNDBY> <RSTSTOP | NORSTSTOP>");
1075 return ERROR_OK;
1076 }
1077
1078 struct flash_bank *bank;
1079 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1080 if (ERROR_OK != retval)
1081 return retval;
1082
1083 stm32x_info = bank->driver_priv;
1084
1085 target = bank->target;
1086
1087 if (target->state != TARGET_HALTED)
1088 {
1089 LOG_ERROR("Target not halted");
1090 return ERROR_TARGET_NOT_HALTED;
1091 }
1092
1093 /* REVISIT: ignores some options which we will display...
1094 * and doesn't insist on the specified syntax.
1095 */
1096
1097 /* OPT_RDWDGSW */
1098 if (strcmp(CMD_ARGV[1], "SWWDG") == 0)
1099 {
1100 optionbyte |= (1 << 0);
1101 }
1102 else /* REVISIT must be "HWWDG" then ... */
1103 {
1104 optionbyte &= ~(1 << 0);
1105 }
1106
1107 /* OPT_RDRSTSTDBY */
1108 if (strcmp(CMD_ARGV[2], "NORSTSTNDBY") == 0)
1109 {
1110 optionbyte |= (1 << 1);
1111 }
1112 else /* REVISIT must be "RSTSTNDBY" then ... */
1113 {
1114 optionbyte &= ~(1 << 1);
1115 }
1116
1117 /* OPT_RDRSTSTOP */
1118 if (strcmp(CMD_ARGV[3], "NORSTSTOP") == 0)
1119 {
1120 optionbyte |= (1 << 2);
1121 }
1122 else /* REVISIT must be "RSTSTOP" then ... */
1123 {
1124 optionbyte &= ~(1 << 2);
1125 }
1126
1127 if (stm32x_erase_options(bank) != ERROR_OK)
1128 {
1129 command_print(CMD_CTX, "stm32x failed to erase options");
1130 return ERROR_OK;
1131 }
1132
1133 stm32x_info->option_bytes.user_options = optionbyte;
1134
1135 if (stm32x_write_options(bank) != ERROR_OK)
1136 {
1137 command_print(CMD_CTX, "stm32x failed to write options");
1138 return ERROR_OK;
1139 }
1140
1141 command_print(CMD_CTX, "stm32x write options complete.\n"
1142 "INFO: a reset or power cycle is required "
1143 "for the new settings to take effect.");
1144
1145 return ERROR_OK;
1146 }
1147
1148 static int stm32x_mass_erase(struct flash_bank *bank)
1149 {
1150 struct target *target = bank->target;
1151
1152 if (target->state != TARGET_HALTED)
1153 {
1154 LOG_ERROR("Target not halted");
1155 return ERROR_TARGET_NOT_HALTED;
1156 }
1157
1158 /* unlock option flash registers */
1159 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
1160 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
1161
1162 /* mass erase flash memory */
1163 target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
1164 target_write_u32(target, STM32_FLASH_CR, FLASH_MER | FLASH_STRT);
1165
1166 int retval = stm32x_wait_status_busy(bank, 100);
1167 if (retval != ERROR_OK)
1168 return retval;
1169
1170 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
1171
1172 return ERROR_OK;
1173 }
1174
1175 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1176 {
1177 int i;
1178
1179 if (CMD_ARGC < 1)
1180 {
1181 command_print(CMD_CTX, "stm32x mass_erase <bank>");
1182 return ERROR_OK;
1183 }
1184
1185 struct flash_bank *bank;
1186 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1187 if (ERROR_OK != retval)
1188 return retval;
1189
1190 retval = stm32x_mass_erase(bank);
1191 if (retval == ERROR_OK)
1192 {
1193 /* set all sectors as erased */
1194 for (i = 0; i < bank->num_sectors; i++)
1195 {
1196 bank->sectors[i].is_erased = 1;
1197 }
1198
1199 command_print(CMD_CTX, "stm32x mass erase complete");
1200 }
1201 else
1202 {
1203 command_print(CMD_CTX, "stm32x mass erase failed");
1204 }
1205
1206 return retval;
1207 }
1208
1209 static const struct command_registration stm32x_exec_command_handlers[] = {
1210 {
1211 .name = "lock",
1212 .handler = stm32x_handle_lock_command,
1213 .mode = COMMAND_EXEC,
1214 .usage = "bank_id",
1215 .help = "Lock entire flash device.",
1216 },
1217 {
1218 .name = "unlock",
1219 .handler = stm32x_handle_unlock_command,
1220 .mode = COMMAND_EXEC,
1221 .usage = "bank_id",
1222 .help = "Unlock entire protected flash device.",
1223 },
1224 {
1225 .name = "mass_erase",
1226 .handler = stm32x_handle_mass_erase_command,
1227 .mode = COMMAND_EXEC,
1228 .usage = "bank_id",
1229 .help = "Erase entire flash device.",
1230 },
1231 {
1232 .name = "options_read",
1233 .handler = stm32x_handle_options_read_command,
1234 .mode = COMMAND_EXEC,
1235 .usage = "bank_id",
1236 .help = "Read and display device option byte.",
1237 },
1238 {
1239 .name = "options_write",
1240 .handler = stm32x_handle_options_write_command,
1241 .mode = COMMAND_EXEC,
1242 .usage = "bank_id ('SWWDG'|'HWWDG') "
1243 "('RSTSTNDBY'|'NORSTSTNDBY') "
1244 "('RSTSTOP'|'NORSTSTOP')",
1245 .help = "Replace bits in device option byte.",
1246 },
1247 COMMAND_REGISTRATION_DONE
1248 };
1249
1250 static const struct command_registration stm32x_command_handlers[] = {
1251 {
1252 .name = "stm32x",
1253 .mode = COMMAND_ANY,
1254 .help = "stm32x flash command group",
1255 .chain = stm32x_exec_command_handlers,
1256 },
1257 COMMAND_REGISTRATION_DONE
1258 };
1259
1260 struct flash_driver stm32x_flash = {
1261 .name = "stm32x",
1262 .commands = stm32x_command_handlers,
1263 .flash_bank_command = stm32x_flash_bank_command,
1264 .erase = stm32x_erase,
1265 .protect = stm32x_protect,
1266 .write = stm32x_write,
1267 .read = default_flash_read,
1268 .probe = stm32x_probe,
1269 .auto_probe = stm32x_auto_probe,
1270 .erase_check = default_flash_mem_blank_check,
1271 .protect_check = stm32x_protect_check,
1272 .info = get_stm32x_info,
1273 };
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