1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
29 #include <helper/binarybuffer.h>
30 #include <target/algorithm.h>
31 #include <target/armv7m.h>
34 static int stm32x_mass_erase(struct flash_bank
*bank
);
36 /* flash bank stm32x <base> <size> 0 0 <target#>
38 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command
)
40 struct stm32x_flash_bank
*stm32x_info
;
44 LOG_WARNING("incomplete flash_bank stm32x configuration");
45 return ERROR_FLASH_BANK_INVALID
;
48 stm32x_info
= malloc(sizeof(struct stm32x_flash_bank
));
49 bank
->driver_priv
= stm32x_info
;
51 stm32x_info
->write_algorithm
= NULL
;
52 stm32x_info
->probed
= 0;
57 static int stm32x_get_flash_status(struct flash_bank
*bank
, uint32_t *status
)
59 struct target
*target
= bank
->target
;
60 return target_read_u32(target
, STM32_FLASH_SR
, status
);
63 static int stm32x_wait_status_busy(struct flash_bank
*bank
, int timeout
)
65 struct target
*target
= bank
->target
;
67 int retval
= ERROR_OK
;
69 /* wait for busy to clear */
72 retval
= stm32x_get_flash_status(bank
, &status
);
73 if (retval
!= ERROR_OK
)
75 LOG_DEBUG("status: 0x%" PRIx32
"", status
);
76 if ((status
& FLASH_BSY
) == 0)
80 LOG_ERROR("timed out waiting for flash");
86 if (status
& FLASH_WRPRTERR
)
88 LOG_ERROR("stm32x device protected");
92 if (status
& FLASH_PGERR
)
94 LOG_ERROR("stm32x device programming failed");
98 /* Clear but report errors */
99 if (status
& (FLASH_WRPRTERR
| FLASH_PGERR
))
101 /* If this operation fails, we ignore it and report the original
104 target_write_u32(target
, STM32_FLASH_SR
, FLASH_WRPRTERR
| FLASH_PGERR
);
109 static int stm32x_read_options(struct flash_bank
*bank
)
112 struct stm32x_flash_bank
*stm32x_info
= NULL
;
113 struct target
*target
= bank
->target
;
115 stm32x_info
= bank
->driver_priv
;
117 /* read current option bytes */
118 target_read_u32(target
, STM32_FLASH_OBR
, &optiondata
);
120 stm32x_info
->option_bytes
.user_options
= (uint16_t)0xFFF8 | ((optiondata
>> 2) & 0x07);
121 stm32x_info
->option_bytes
.RDP
= (optiondata
& (1 << OPT_READOUT
)) ? 0xFFFF : 0x5AA5;
123 if (optiondata
& (1 << OPT_READOUT
))
124 LOG_INFO("Device Security Bit Set");
126 /* each bit refers to a 4bank protection */
127 target_read_u32(target
, STM32_FLASH_WRPR
, &optiondata
);
129 stm32x_info
->option_bytes
.protection
[0] = (uint16_t)optiondata
;
130 stm32x_info
->option_bytes
.protection
[1] = (uint16_t)(optiondata
>> 8);
131 stm32x_info
->option_bytes
.protection
[2] = (uint16_t)(optiondata
>> 16);
132 stm32x_info
->option_bytes
.protection
[3] = (uint16_t)(optiondata
>> 24);
137 static int stm32x_erase_options(struct flash_bank
*bank
)
139 struct stm32x_flash_bank
*stm32x_info
= NULL
;
140 struct target
*target
= bank
->target
;
142 stm32x_info
= bank
->driver_priv
;
144 /* read current options */
145 stm32x_read_options(bank
);
147 /* unlock flash registers */
148 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
149 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
151 /* unlock option flash registers */
152 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY1
);
153 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY2
);
155 /* erase option bytes */
156 target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTER
| FLASH_OPTWRE
);
157 target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTER
| FLASH_STRT
| FLASH_OPTWRE
);
159 int retval
= stm32x_wait_status_busy(bank
, 10);
160 if (retval
!= ERROR_OK
)
163 /* clear readout protection and complementary option bytes
164 * this will also force a device unlock if set */
165 stm32x_info
->option_bytes
.RDP
= 0x5AA5;
170 static int stm32x_write_options(struct flash_bank
*bank
)
172 struct stm32x_flash_bank
*stm32x_info
= NULL
;
173 struct target
*target
= bank
->target
;
175 stm32x_info
= bank
->driver_priv
;
177 /* unlock flash registers */
178 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
179 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
181 /* unlock option flash registers */
182 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY1
);
183 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY2
);
185 /* program option bytes */
186 target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTPG
| FLASH_OPTWRE
);
188 /* write user option byte */
189 target_write_u16(target
, STM32_OB_USER
, stm32x_info
->option_bytes
.user_options
);
191 int retval
= stm32x_wait_status_busy(bank
, 10);
192 if (retval
!= ERROR_OK
)
195 /* write protection byte 1 */
196 target_write_u16(target
, STM32_OB_WRP0
, stm32x_info
->option_bytes
.protection
[0]);
198 retval
= stm32x_wait_status_busy(bank
, 10);
199 if (retval
!= ERROR_OK
)
202 /* write protection byte 2 */
203 target_write_u16(target
, STM32_OB_WRP1
, stm32x_info
->option_bytes
.protection
[1]);
205 retval
= stm32x_wait_status_busy(bank
, 10);
206 if (retval
!= ERROR_OK
)
209 /* write protection byte 3 */
210 target_write_u16(target
, STM32_OB_WRP2
, stm32x_info
->option_bytes
.protection
[2]);
212 retval
= stm32x_wait_status_busy(bank
, 10);
213 if (retval
!= ERROR_OK
)
216 /* write protection byte 4 */
217 target_write_u16(target
, STM32_OB_WRP3
, stm32x_info
->option_bytes
.protection
[3]);
219 retval
= stm32x_wait_status_busy(bank
, 10);
220 if (retval
!= ERROR_OK
)
223 /* write readout protection bit */
224 target_write_u16(target
, STM32_OB_RDP
, stm32x_info
->option_bytes
.RDP
);
226 retval
= stm32x_wait_status_busy(bank
, 10);
227 if (retval
!= ERROR_OK
)
230 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
235 static int stm32x_protect_check(struct flash_bank
*bank
)
237 struct target
*target
= bank
->target
;
238 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
245 if (target
->state
!= TARGET_HALTED
)
247 LOG_ERROR("Target not halted");
248 return ERROR_TARGET_NOT_HALTED
;
251 /* medium density - each bit refers to a 4bank protection
252 * high density - each bit refers to a 2bank protection */
253 target_read_u32(target
, STM32_FLASH_WRPR
, &protection
);
255 /* medium density - each protection bit is for 4 * 1K pages
256 * high density - each protection bit is for 2 * 2K pages */
257 num_bits
= (bank
->num_sectors
/ stm32x_info
->ppage_size
);
259 if (stm32x_info
->ppage_size
== 2)
261 /* high density flash/connectivity line protection */
265 if (protection
& (1 << 31))
268 /* bit 31 controls sector 62 - 255 protection for high density
269 * bit 31 controls sector 62 - 127 protection for connectivity line */
270 for (s
= 62; s
< bank
->num_sectors
; s
++)
272 bank
->sectors
[s
].is_protected
= set
;
275 if (bank
->num_sectors
> 61)
278 for (i
= 0; i
< num_bits
; i
++)
282 if (protection
& (1 << i
))
285 for (s
= 0; s
< stm32x_info
->ppage_size
; s
++)
286 bank
->sectors
[(i
* stm32x_info
->ppage_size
) + s
].is_protected
= set
;
291 /* low/medium density flash protection */
292 for (i
= 0; i
< num_bits
; i
++)
296 if (protection
& (1 << i
))
299 for (s
= 0; s
< stm32x_info
->ppage_size
; s
++)
300 bank
->sectors
[(i
* stm32x_info
->ppage_size
) + s
].is_protected
= set
;
307 static int stm32x_erase(struct flash_bank
*bank
, int first
, int last
)
309 struct target
*target
= bank
->target
;
312 if (bank
->target
->state
!= TARGET_HALTED
)
314 LOG_ERROR("Target not halted");
315 return ERROR_TARGET_NOT_HALTED
;
318 if ((first
== 0) && (last
== (bank
->num_sectors
- 1)))
320 return stm32x_mass_erase(bank
);
323 /* unlock flash registers */
324 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
325 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
327 for (i
= first
; i
<= last
; i
++)
329 target_write_u32(target
, STM32_FLASH_CR
, FLASH_PER
);
330 target_write_u32(target
, STM32_FLASH_AR
, bank
->base
+ bank
->sectors
[i
].offset
);
331 target_write_u32(target
, STM32_FLASH_CR
, FLASH_PER
| FLASH_STRT
);
333 int retval
= stm32x_wait_status_busy(bank
, 100);
334 if (retval
!= ERROR_OK
)
337 bank
->sectors
[i
].is_erased
= 1;
340 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
345 static int stm32x_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
347 struct stm32x_flash_bank
*stm32x_info
= NULL
;
348 struct target
*target
= bank
->target
;
349 uint16_t prot_reg
[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
354 stm32x_info
= bank
->driver_priv
;
356 if (target
->state
!= TARGET_HALTED
)
358 LOG_ERROR("Target not halted");
359 return ERROR_TARGET_NOT_HALTED
;
362 if ((first
&& (first
% stm32x_info
->ppage_size
)) || ((last
+ 1) &&
363 (last
+ 1) % stm32x_info
->ppage_size
))
365 LOG_WARNING("Error: start and end sectors must be on a %d sector boundary",
366 stm32x_info
->ppage_size
);
367 return ERROR_FLASH_SECTOR_INVALID
;
370 /* medium density - each bit refers to a 4bank protection
371 * high density - each bit refers to a 2bank protection */
372 target_read_u32(target
, STM32_FLASH_WRPR
, &protection
);
374 prot_reg
[0] = (uint16_t)protection
;
375 prot_reg
[1] = (uint16_t)(protection
>> 8);
376 prot_reg
[2] = (uint16_t)(protection
>> 16);
377 prot_reg
[3] = (uint16_t)(protection
>> 24);
379 if (stm32x_info
->ppage_size
== 2)
381 /* high density flash */
383 /* bit 7 controls sector 62 - 255 protection */
387 prot_reg
[3] &= ~(1 << 7);
389 prot_reg
[3] |= (1 << 7);
397 for (i
= first
; i
<= last
; i
++)
399 reg
= (i
/ stm32x_info
->ppage_size
) / 8;
400 bit
= (i
/ stm32x_info
->ppage_size
) - (reg
* 8);
403 prot_reg
[reg
] &= ~(1 << bit
);
405 prot_reg
[reg
] |= (1 << bit
);
410 /* medium density flash */
411 for (i
= first
; i
<= last
; i
++)
413 reg
= (i
/ stm32x_info
->ppage_size
) / 8;
414 bit
= (i
/ stm32x_info
->ppage_size
) - (reg
* 8);
417 prot_reg
[reg
] &= ~(1 << bit
);
419 prot_reg
[reg
] |= (1 << bit
);
423 if ((status
= stm32x_erase_options(bank
)) != ERROR_OK
)
426 stm32x_info
->option_bytes
.protection
[0] = prot_reg
[0];
427 stm32x_info
->option_bytes
.protection
[1] = prot_reg
[1];
428 stm32x_info
->option_bytes
.protection
[2] = prot_reg
[2];
429 stm32x_info
->option_bytes
.protection
[3] = prot_reg
[3];
431 return stm32x_write_options(bank
);
434 static int stm32x_write_block(struct flash_bank
*bank
, uint8_t *buffer
,
435 uint32_t offset
, uint32_t count
)
437 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
438 struct target
*target
= bank
->target
;
439 uint32_t buffer_size
= 16384;
440 struct working_area
*source
;
441 uint32_t address
= bank
->base
+ offset
;
442 struct reg_param reg_params
[4];
443 struct armv7m_algorithm armv7m_info
;
444 int retval
= ERROR_OK
;
446 /* see contib/loaders/flash/stm32x.s for src */
448 static const uint8_t stm32x_flash_write_code
[] = {
450 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
451 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
452 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
453 0x23, 0x60, /* str r3, [r4, #0] */
454 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
455 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
457 0x2B, 0x68, /* ldr r3, [r5, #0] */
458 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
459 0xFB, 0xD0, /* beq busy */
460 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
461 0x01, 0xD1, /* bne exit */
462 0x01, 0x3A, /* subs r2, r2, #1 */
463 0xED, 0xD1, /* bne write */
465 0x00, 0xBE, /* bkpt #0 */
466 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
467 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
470 /* flash write code */
471 if (target_alloc_working_area(target
, sizeof(stm32x_flash_write_code
),
472 &stm32x_info
->write_algorithm
) != ERROR_OK
)
474 LOG_WARNING("no working area available, can't do block memory writes");
475 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
478 if ((retval
= target_write_buffer(target
, stm32x_info
->write_algorithm
->address
,
479 sizeof(stm32x_flash_write_code
),
480 (uint8_t*)stm32x_flash_write_code
)) != ERROR_OK
)
484 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
)
487 if (buffer_size
<= 256)
489 /* if we already allocated the writing code, but failed to get a
490 * buffer, free the algorithm */
491 if (stm32x_info
->write_algorithm
)
492 target_free_working_area(target
, stm32x_info
->write_algorithm
);
494 LOG_WARNING("no large enough working area available, can't do block memory writes");
495 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
499 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
500 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
502 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
503 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
504 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
505 init_reg_param(®_params
[3], "r3", 32, PARAM_IN
);
509 uint32_t thisrun_count
= (count
> (buffer_size
/ 2)) ?
510 (buffer_size
/ 2) : count
;
512 if ((retval
= target_write_buffer(target
, source
->address
,
513 thisrun_count
* 2, buffer
)) != ERROR_OK
)
516 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
517 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
518 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
);
520 if ((retval
= target_run_algorithm(target
, 0, NULL
, 4, reg_params
,
521 stm32x_info
->write_algorithm
->address
,
523 10000, &armv7m_info
)) != ERROR_OK
)
525 LOG_ERROR("error executing stm32x flash write algorithm");
529 if (buf_get_u32(reg_params
[3].value
, 0, 32) & FLASH_PGERR
)
531 LOG_ERROR("flash memory not erased before writing");
532 /* Clear but report errors */
533 target_write_u32(target
, STM32_FLASH_SR
, FLASH_PGERR
);
538 if (buf_get_u32(reg_params
[3].value
, 0, 32) & FLASH_WRPRTERR
)
540 LOG_ERROR("flash memory write protected");
541 /* Clear but report errors */
542 target_write_u32(target
, STM32_FLASH_SR
, FLASH_WRPRTERR
);
547 buffer
+= thisrun_count
* 2;
548 address
+= thisrun_count
* 2;
549 count
-= thisrun_count
;
552 target_free_working_area(target
, source
);
553 target_free_working_area(target
, stm32x_info
->write_algorithm
);
555 destroy_reg_param(®_params
[0]);
556 destroy_reg_param(®_params
[1]);
557 destroy_reg_param(®_params
[2]);
558 destroy_reg_param(®_params
[3]);
563 static int stm32x_write(struct flash_bank
*bank
, uint8_t *buffer
,
564 uint32_t offset
, uint32_t count
)
566 struct target
*target
= bank
->target
;
567 uint32_t words_remaining
= (count
/ 2);
568 uint32_t bytes_remaining
= (count
& 0x00000001);
569 uint32_t address
= bank
->base
+ offset
;
570 uint32_t bytes_written
= 0;
573 if (bank
->target
->state
!= TARGET_HALTED
)
575 LOG_ERROR("Target not halted");
576 return ERROR_TARGET_NOT_HALTED
;
581 LOG_WARNING("offset 0x%" PRIx32
" breaks required 2-byte alignment", offset
);
582 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
585 /* unlock flash registers */
586 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
587 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
589 /* multiple half words (2-byte) to be programmed? */
590 if (words_remaining
> 0)
592 /* try using a block write */
593 if ((retval
= stm32x_write_block(bank
, buffer
, offset
, words_remaining
)) != ERROR_OK
)
595 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
597 /* if block write failed (no sufficient working area),
598 * we use normal (slow) single dword accesses */
599 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
604 buffer
+= words_remaining
* 2;
605 address
+= words_remaining
* 2;
610 while (words_remaining
> 0)
613 memcpy(&value
, buffer
+ bytes_written
, sizeof(uint16_t));
615 target_write_u32(target
, STM32_FLASH_CR
, FLASH_PG
);
616 target_write_u16(target
, address
, value
);
618 retval
= stm32x_wait_status_busy(bank
, 5);
619 if (retval
!= ERROR_OK
)
629 uint16_t value
= 0xffff;
630 memcpy(&value
, buffer
+ bytes_written
, bytes_remaining
);
632 target_write_u32(target
, STM32_FLASH_CR
, FLASH_PG
);
633 target_write_u16(target
, address
, value
);
635 retval
= stm32x_wait_status_busy(bank
, 5);
636 if (retval
!= ERROR_OK
)
640 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
645 static int stm32x_probe(struct flash_bank
*bank
)
647 struct target
*target
= bank
->target
;
648 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
654 stm32x_info
->probed
= 0;
656 /* read stm32 device id register */
657 target_read_u32(target
, 0xE0042000, &device_id
);
658 LOG_INFO("device id = 0x%08" PRIx32
"", device_id
);
660 /* get flash size from target */
661 if (target_read_u16(target
, 0x1FFFF7E0, &num_pages
) != ERROR_OK
)
663 /* failed reading flash size, default to max target family */
667 if ((device_id
& 0x7ff) == 0x410)
669 /* medium density - we have 1k pages
670 * 4 pages for a protection area */
672 stm32x_info
->ppage_size
= 4;
674 /* check for early silicon */
675 if (num_pages
== 0xffff)
677 /* number of sectors incorrect on revA */
678 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
682 else if ((device_id
& 0x7ff) == 0x412)
684 /* low density - we have 1k pages
685 * 4 pages for a protection area */
687 stm32x_info
->ppage_size
= 4;
689 /* check for early silicon */
690 if (num_pages
== 0xffff)
692 /* number of sectors incorrect on revA */
693 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
697 else if ((device_id
& 0x7ff) == 0x414)
699 /* high density - we have 2k pages
700 * 2 pages for a protection area */
702 stm32x_info
->ppage_size
= 2;
704 /* check for early silicon */
705 if (num_pages
== 0xffff)
707 /* number of sectors incorrect on revZ */
708 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
712 else if ((device_id
& 0x7ff) == 0x418)
714 /* connectivity line density - we have 2k pages
715 * 2 pages for a protection area */
717 stm32x_info
->ppage_size
= 2;
719 /* check for early silicon */
720 if (num_pages
== 0xffff)
722 /* number of sectors incorrect on revZ */
723 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
727 else if ((device_id
& 0x7ff) == 0x420)
729 /* value line density - we have 1k pages
730 * 4 pages for a protection area */
732 stm32x_info
->ppage_size
= 4;
734 /* check for early silicon */
735 if (num_pages
== 0xffff)
737 /* number of sectors may be incorrrect on early silicon */
738 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
744 LOG_WARNING("Cannot identify target as a STM32 family.");
748 LOG_INFO("flash size = %dkbytes", num_pages
);
750 /* calculate numbers of pages */
751 num_pages
/= (page_size
/ 1024);
756 bank
->sectors
= NULL
;
759 bank
->base
= 0x08000000;
760 bank
->size
= (num_pages
* page_size
);
761 bank
->num_sectors
= num_pages
;
762 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_pages
);
764 for (i
= 0; i
< num_pages
; i
++)
766 bank
->sectors
[i
].offset
= i
* page_size
;
767 bank
->sectors
[i
].size
= page_size
;
768 bank
->sectors
[i
].is_erased
= -1;
769 bank
->sectors
[i
].is_protected
= 1;
772 stm32x_info
->probed
= 1;
777 static int stm32x_auto_probe(struct flash_bank
*bank
)
779 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
780 if (stm32x_info
->probed
)
782 return stm32x_probe(bank
);
786 COMMAND_HANDLER(stm32x_handle_part_id_command
)
792 static int get_stm32x_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
794 struct target
*target
= bank
->target
;
798 /* read stm32 device id register */
799 target_read_u32(target
, 0xE0042000, &device_id
);
801 if ((device_id
& 0x7ff) == 0x410)
803 printed
= snprintf(buf
, buf_size
, "stm32x (Medium Density) - Rev: ");
807 switch (device_id
>> 16)
810 snprintf(buf
, buf_size
, "A");
814 snprintf(buf
, buf_size
, "B");
818 snprintf(buf
, buf_size
, "Z");
822 snprintf(buf
, buf_size
, "Y");
826 snprintf(buf
, buf_size
, "unknown");
830 else if ((device_id
& 0x7ff) == 0x412)
832 printed
= snprintf(buf
, buf_size
, "stm32x (Low Density) - Rev: ");
836 switch (device_id
>> 16)
839 snprintf(buf
, buf_size
, "A");
843 snprintf(buf
, buf_size
, "unknown");
847 else if ((device_id
& 0x7ff) == 0x414)
849 printed
= snprintf(buf
, buf_size
, "stm32x (High Density) - Rev: ");
853 switch (device_id
>> 16)
856 snprintf(buf
, buf_size
, "A");
860 snprintf(buf
, buf_size
, "Z");
864 snprintf(buf
, buf_size
, "unknown");
868 else if ((device_id
& 0x7ff) == 0x418)
870 printed
= snprintf(buf
, buf_size
, "stm32x (Connectivity) - Rev: ");
874 switch (device_id
>> 16)
877 snprintf(buf
, buf_size
, "A");
881 snprintf(buf
, buf_size
, "Z");
885 snprintf(buf
, buf_size
, "unknown");
889 else if ((device_id
& 0x7ff) == 0x420)
891 printed
= snprintf(buf
, buf_size
, "stm32x (Value) - Rev: ");
895 switch (device_id
>> 16)
898 snprintf(buf
, buf_size
, "A");
902 snprintf(buf
, buf_size
, "Z");
906 snprintf(buf
, buf_size
, "unknown");
912 snprintf(buf
, buf_size
, "Cannot identify target as a stm32x\n");
919 COMMAND_HANDLER(stm32x_handle_lock_command
)
921 struct target
*target
= NULL
;
922 struct stm32x_flash_bank
*stm32x_info
= NULL
;
926 command_print(CMD_CTX
, "stm32x lock <bank>");
930 struct flash_bank
*bank
;
931 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
932 if (ERROR_OK
!= retval
)
935 stm32x_info
= bank
->driver_priv
;
937 target
= bank
->target
;
939 if (target
->state
!= TARGET_HALTED
)
941 LOG_ERROR("Target not halted");
942 return ERROR_TARGET_NOT_HALTED
;
945 if (stm32x_erase_options(bank
) != ERROR_OK
)
947 command_print(CMD_CTX
, "stm32x failed to erase options");
951 /* set readout protection */
952 stm32x_info
->option_bytes
.RDP
= 0;
954 if (stm32x_write_options(bank
) != ERROR_OK
)
956 command_print(CMD_CTX
, "stm32x failed to lock device");
960 command_print(CMD_CTX
, "stm32x locked");
965 COMMAND_HANDLER(stm32x_handle_unlock_command
)
967 struct target
*target
= NULL
;
968 struct stm32x_flash_bank
*stm32x_info
= NULL
;
972 command_print(CMD_CTX
, "stm32x unlock <bank>");
976 struct flash_bank
*bank
;
977 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
978 if (ERROR_OK
!= retval
)
981 stm32x_info
= bank
->driver_priv
;
983 target
= bank
->target
;
985 if (target
->state
!= TARGET_HALTED
)
987 LOG_ERROR("Target not halted");
988 return ERROR_TARGET_NOT_HALTED
;
991 if (stm32x_erase_options(bank
) != ERROR_OK
)
993 command_print(CMD_CTX
, "stm32x failed to unlock device");
997 if (stm32x_write_options(bank
) != ERROR_OK
)
999 command_print(CMD_CTX
, "stm32x failed to lock device");
1003 command_print(CMD_CTX
, "stm32x unlocked.\n"
1004 "INFO: a reset or power cycle is required "
1005 "for the new settings to take effect.");
1010 COMMAND_HANDLER(stm32x_handle_options_read_command
)
1012 uint32_t optionbyte
;
1013 struct target
*target
= NULL
;
1014 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1018 command_print(CMD_CTX
, "stm32x options_read <bank>");
1022 struct flash_bank
*bank
;
1023 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1024 if (ERROR_OK
!= retval
)
1027 stm32x_info
= bank
->driver_priv
;
1029 target
= bank
->target
;
1031 if (target
->state
!= TARGET_HALTED
)
1033 LOG_ERROR("Target not halted");
1034 return ERROR_TARGET_NOT_HALTED
;
1037 target_read_u32(target
, STM32_FLASH_OBR
, &optionbyte
);
1038 command_print(CMD_CTX
, "Option Byte: 0x%" PRIx32
"", optionbyte
);
1040 if (buf_get_u32((uint8_t*)&optionbyte
, OPT_ERROR
, 1))
1041 command_print(CMD_CTX
, "Option Byte Complement Error");
1043 if (buf_get_u32((uint8_t*)&optionbyte
, OPT_READOUT
, 1))
1044 command_print(CMD_CTX
, "Readout Protection On");
1046 command_print(CMD_CTX
, "Readout Protection Off");
1048 if (buf_get_u32((uint8_t*)&optionbyte
, OPT_RDWDGSW
, 1))
1049 command_print(CMD_CTX
, "Software Watchdog");
1051 command_print(CMD_CTX
, "Hardware Watchdog");
1053 if (buf_get_u32((uint8_t*)&optionbyte
, OPT_RDRSTSTOP
, 1))
1054 command_print(CMD_CTX
, "Stop: No reset generated");
1056 command_print(CMD_CTX
, "Stop: Reset generated");
1058 if (buf_get_u32((uint8_t*)&optionbyte
, OPT_RDRSTSTDBY
, 1))
1059 command_print(CMD_CTX
, "Standby: No reset generated");
1061 command_print(CMD_CTX
, "Standby: Reset generated");
1066 COMMAND_HANDLER(stm32x_handle_options_write_command
)
1068 struct target
*target
= NULL
;
1069 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1070 uint16_t optionbyte
= 0xF8;
1074 command_print(CMD_CTX
, "stm32x options_write <bank> <SWWDG | HWWDG> <RSTSTNDBY | NORSTSTNDBY> <RSTSTOP | NORSTSTOP>");
1078 struct flash_bank
*bank
;
1079 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1080 if (ERROR_OK
!= retval
)
1083 stm32x_info
= bank
->driver_priv
;
1085 target
= bank
->target
;
1087 if (target
->state
!= TARGET_HALTED
)
1089 LOG_ERROR("Target not halted");
1090 return ERROR_TARGET_NOT_HALTED
;
1093 /* REVISIT: ignores some options which we will display...
1094 * and doesn't insist on the specified syntax.
1098 if (strcmp(CMD_ARGV
[1], "SWWDG") == 0)
1100 optionbyte
|= (1 << 0);
1102 else /* REVISIT must be "HWWDG" then ... */
1104 optionbyte
&= ~(1 << 0);
1107 /* OPT_RDRSTSTDBY */
1108 if (strcmp(CMD_ARGV
[2], "NORSTSTNDBY") == 0)
1110 optionbyte
|= (1 << 1);
1112 else /* REVISIT must be "RSTSTNDBY" then ... */
1114 optionbyte
&= ~(1 << 1);
1118 if (strcmp(CMD_ARGV
[3], "NORSTSTOP") == 0)
1120 optionbyte
|= (1 << 2);
1122 else /* REVISIT must be "RSTSTOP" then ... */
1124 optionbyte
&= ~(1 << 2);
1127 if (stm32x_erase_options(bank
) != ERROR_OK
)
1129 command_print(CMD_CTX
, "stm32x failed to erase options");
1133 stm32x_info
->option_bytes
.user_options
= optionbyte
;
1135 if (stm32x_write_options(bank
) != ERROR_OK
)
1137 command_print(CMD_CTX
, "stm32x failed to write options");
1141 command_print(CMD_CTX
, "stm32x write options complete.\n"
1142 "INFO: a reset or power cycle is required "
1143 "for the new settings to take effect.");
1148 static int stm32x_mass_erase(struct flash_bank
*bank
)
1150 struct target
*target
= bank
->target
;
1152 if (target
->state
!= TARGET_HALTED
)
1154 LOG_ERROR("Target not halted");
1155 return ERROR_TARGET_NOT_HALTED
;
1158 /* unlock option flash registers */
1159 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
1160 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
1162 /* mass erase flash memory */
1163 target_write_u32(target
, STM32_FLASH_CR
, FLASH_MER
);
1164 target_write_u32(target
, STM32_FLASH_CR
, FLASH_MER
| FLASH_STRT
);
1166 int retval
= stm32x_wait_status_busy(bank
, 100);
1167 if (retval
!= ERROR_OK
)
1170 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
1175 COMMAND_HANDLER(stm32x_handle_mass_erase_command
)
1181 command_print(CMD_CTX
, "stm32x mass_erase <bank>");
1185 struct flash_bank
*bank
;
1186 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1187 if (ERROR_OK
!= retval
)
1190 retval
= stm32x_mass_erase(bank
);
1191 if (retval
== ERROR_OK
)
1193 /* set all sectors as erased */
1194 for (i
= 0; i
< bank
->num_sectors
; i
++)
1196 bank
->sectors
[i
].is_erased
= 1;
1199 command_print(CMD_CTX
, "stm32x mass erase complete");
1203 command_print(CMD_CTX
, "stm32x mass erase failed");
1209 static const struct command_registration stm32x_exec_command_handlers
[] = {
1212 .handler
= stm32x_handle_lock_command
,
1213 .mode
= COMMAND_EXEC
,
1215 .help
= "Lock entire flash device.",
1219 .handler
= stm32x_handle_unlock_command
,
1220 .mode
= COMMAND_EXEC
,
1222 .help
= "Unlock entire protected flash device.",
1225 .name
= "mass_erase",
1226 .handler
= stm32x_handle_mass_erase_command
,
1227 .mode
= COMMAND_EXEC
,
1229 .help
= "Erase entire flash device.",
1232 .name
= "options_read",
1233 .handler
= stm32x_handle_options_read_command
,
1234 .mode
= COMMAND_EXEC
,
1236 .help
= "Read and display device option byte.",
1239 .name
= "options_write",
1240 .handler
= stm32x_handle_options_write_command
,
1241 .mode
= COMMAND_EXEC
,
1242 .usage
= "bank_id ('SWWDG'|'HWWDG') "
1243 "('RSTSTNDBY'|'NORSTSTNDBY') "
1244 "('RSTSTOP'|'NORSTSTOP')",
1245 .help
= "Replace bits in device option byte.",
1247 COMMAND_REGISTRATION_DONE
1250 static const struct command_registration stm32x_command_handlers
[] = {
1253 .mode
= COMMAND_ANY
,
1254 .help
= "stm32x flash command group",
1255 .chain
= stm32x_exec_command_handlers
,
1257 COMMAND_REGISTRATION_DONE
1260 struct flash_driver stm32x_flash
= {
1262 .commands
= stm32x_command_handlers
,
1263 .flash_bank_command
= stm32x_flash_bank_command
,
1264 .erase
= stm32x_erase
,
1265 .protect
= stm32x_protect
,
1266 .write
= stm32x_write
,
1267 .read
= default_flash_read
,
1268 .probe
= stm32x_probe
,
1269 .auto_probe
= stm32x_auto_probe
,
1270 .erase_check
= default_flash_mem_blank_check
,
1271 .protect_check
= stm32x_protect_check
,
1272 .info
= get_stm32x_info
,
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