src/flash/nor/stmqspi.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2016 - 2018 by Andreas Bolsch                           *
   5  *   andreas.bolsch@mni.thm.de                                             *
   6  ***************************************************************************/
   7
   8 #ifndef OPENOCD_FLASH_NOR_STMQSPI_H
   9 #define OPENOCD_FLASH_NOR_STMQSPI_H
  10
  11 #include "spi.h"
  12
  13 /* QSPI register offsets */
  14 #define QSPI_CR                 (0x00)  /* Control register */
  15 #define QSPI_DCR                (0x04)  /* Device configuration register */
  16 #define QSPI_SR                 (0x08)  /* Status register */
  17 #define QSPI_FCR                (0x0C)  /* Flag clear register */
  18 #define QSPI_DLR                (0x10)  /* Data length register */
  19 #define QSPI_CCR                (0x14)  /* Communication configuration register */
  20 #define QSPI_AR                 (0x18)  /* Address register */
  21 #define QSPI_ABR                (0x1C)  /* Alternate bytes register */
  22 #define QSPI_DR                 (0x20)  /* Data register */
  23
  24 /* common bits in QSPI_CR and OCTOSPI_CR */
  25 #define SPI_FSEL_FLASH  7               /* Select flash 2 */
  26 #define SPI_DUAL_FLASH  6               /* Dual flash mode */
  27 #define SPI_ABORT               1               /* Abort bit */
  28
  29 /* common bits in QSPI_DCR and OCTOSPI_DCR1 */
  30 #define SPI_FSIZE_POS   16              /* bit position of FSIZE */
  31 #define SPI_FSIZE_LEN   5               /* width of FSIZE field */
  32
  33 /* common bits in QSPI_SR/FCR and OCTOSPI_SR/FCR */
  34 #define SPI_BUSY                5               /* Busy flag */
  35 #define SPI_FTF                 2               /* FIFO threshold flag */
  36 #define SPI_TCF                 1               /* Transfer complete flag */
  37
  38 /* fields in QSPI_CCR */
  39 #define QSPI_DDRM                       31                                      /* position of DDRM bit */
  40 #define SPI_DMODE_POS           24                                      /* bit position of DMODE */
  41 #define QSPI_DCYC_POS           18                                      /* bit position of DCYC */
  42 #define QSPI_DCYC_LEN           5                                       /* width of DCYC field */
  43 #define QSPI_DCYC_MASK          ((BIT(QSPI_DCYC_LEN) - 1) << QSPI_DCYC_POS)
  44 #define SPI_ADSIZE_POS          12                                      /* bit position of ADSIZE */
  45
  46 #define QSPI_WRITE_MODE         0x00000000U                     /* indirect write mode */
  47 #define QSPI_READ_MODE          0x04000000U                     /* indirect read mode */
  48 #define QSPI_MM_MODE            0x0C000000U                     /* memory mapped mode */
  49 #define QSPI_ALTB_MODE          0x0003C000U                     /* alternate byte mode */
  50 #define QSPI_4LINE_MODE         0x03000F00U                     /* 4 lines for data, addr, instr */
  51 #define QSPI_NO_DATA            (~0x03000000U)          /* no data */
  52 #define QSPI_NO_ALTB            (~QSPI_ALTB_MODE)       /* no alternate */
  53 #define QSPI_NO_ADDR            (~0x00000C00U)          /* no address */
  54 #define QSPI_ADDR3                      (0x2U << SPI_ADSIZE_POS)        /* 3 byte address */
  55 #define QSPI_ADDR4                      (0x3U << SPI_ADSIZE_POS)        /* 4 byte address */
  56
  57 /* OCTOSPI register offsets */
  58 #define OCTOSPI_CR              (0x000) /* Control register */
  59 #define OCTOSPI_DCR1    (0x008) /* Device configuration register 1 */
  60 #define OCTOSPI_DCR2    (0x00C) /* Device configuration register 2 */
  61 #define OCTOSPI_DCR3    (0x010) /* Device configuration register 3 */
  62 #define OCTOSPI_SR              (0x020) /* Status register */
  63 #define OCTOSPI_FCR             (0x024) /* Flag clear register */
  64 #define OCTOSPI_DLR             (0x040) /* Data length register */
  65 #define OCTOSPI_AR              (0x048) /* Address register */
  66 #define OCTOSPI_DR              (0x050) /* Data register */
  67 #define OCTOSPI_CCR             (0x100) /* Communication configuration register */
  68 #define OCTOSPI_TCR             (0x108) /* Timing configuration register */
  69 #define OCTOSPI_IR              (0x110) /* Instruction register */
  70 #define OCTOSPI_WCCR    (0x180) /* Write communication configuration register */
  71 #define OCTOSPI_WIR             (0x190) /* Write instruction register */
  72 #define OCTOSPI_MAGIC   (0x3FC) /* Magic ID register, deleted from RM, why? */
  73
  74 #define OCTO_MAGIC_ID   0xA3C5DD01      /* Magic ID, deleted from RM, why? */
  75
  76 /* additional bits in OCTOSPI_CR */
  77 #define OCTOSPI_WRITE_MODE      0x00000000U                     /* indirect write mode */
  78 #define OCTOSPI_READ_MODE       0x10000000U                     /* indirect read mode */
  79 #define OCTOSPI_MM_MODE         0x30000000U                     /* memory mapped mode */
  80
  81 /* additional fields in OCTOSPI_DCR1 */
  82 #define OCTOSPI_MTYP_POS        (24)                            /* bit position of MTYP */
  83 #define OCTOSPI_MTYP_LEN        (3)                                     /* width of MTYP field */
  84 #define OCTOSPI_MTYP_MASK       ((BIT(OCTOSPI_MTYP_LEN) - 1) << OCTOSPI_MTYP_POS)
  85
  86 /* fields in OCTOSPI_CCR */
  87 #define OCTOSPI_ALTB_MODE       0x001F0000U                             /* alternate byte mode */
  88 #define OCTOSPI_8LINE_MODE      0x0F003F3FU                             /* 8 lines DTR for data, addr, instr */
  89 #define OCTOSPI_NO_DATA         (~0x0F000000U)                  /* no data */
  90 #define OCTOSPI_NO_ALTB         (~OCTOSPI_ALTB_MODE)    /* no alternate */
  91 #define OCTOSPI_NO_ADDR         (~0x00000F00U)                  /* no address */
  92 #define OCTOSPI_ADDR3           (0x2U << SPI_ADSIZE_POS)        /* 3 byte address */
  93 #define OCTOSPI_ADDR4           (0x3U << SPI_ADSIZE_POS)        /* 4 byte address */
  94 #define OCTOSPI_DQSEN           29                                              /* DQS enable */
  95 #define OCTOSPI_DDTR            27                                              /* DTR for data */
  96 #define OCTOSPI_NO_DDTR         (~BIT(OCTOSPI_DDTR))    /* no DTR for data, but maybe still DQS */
  97 #define OCTOSPI_ISIZE_MASK      (0x30)                                  /* ISIZE field */
  98
  99 /* fields in OCTOSPI_TCR */
 100 #define OCTOSPI_DCYC_POS        0                                       /* bit position of DCYC */
 101 #define OCTOSPI_DCYC_LEN        5                                       /* width of DCYC field */
 102 #define OCTOSPI_DCYC_MASK       ((BIT(OCTOSPI_DCYC_LEN) - 1) << OCTOSPI_DCYC_POS)
 103
 104 #define IS_OCTOSPI                      (stmqspi_info->octo)
 105 #define SPI_CR                          (IS_OCTOSPI ? OCTOSPI_CR : QSPI_CR)
 106 #define SPI_DCR                         (IS_OCTOSPI ? OCTOSPI_DCR1 : QSPI_DCR)
 107 #define SPI_SR                          (IS_OCTOSPI ? OCTOSPI_SR : QSPI_SR)
 108 #define SPI_FCR                         (IS_OCTOSPI ? OCTOSPI_FCR : QSPI_FCR)
 109 #define SPI_DLR                         (IS_OCTOSPI ? OCTOSPI_DLR : QSPI_DLR)
 110 #define SPI_AR                          (IS_OCTOSPI ? OCTOSPI_AR : QSPI_AR)
 111 #define SPI_DR                          (IS_OCTOSPI ? OCTOSPI_DR : QSPI_DR)
 112 #define SPI_CCR                         (IS_OCTOSPI ? OCTOSPI_CCR : QSPI_CCR)
 113
 114 #endif /* OPENOCD_FLASH_NOR_STMQSPI_H */