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flash/nor: improved API of flash_driver.info & fixed buffer overruns
[openocd.git] / src / flash / nor / stmsmi.c
1 /***************************************************************************
2 * Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com> *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
16 ***************************************************************************/
17
18 /* STM Serial Memory Interface (SMI) controller is a SPI bus controller
19 * specifically designed for SPI memories.
20 * Only SPI "mode 3" (CPOL=1 and CPHA=1) is supported.
21 * Two working modes are available:
22 * - SW mode: the SPI is controlled by SW. Any custom commands can be sent
23 * on the bus.
24 * - HW mode: the SPI but is under SMI control. Memory content is directly
25 * accessible in CPU memory space. CPU can read, write and execute memory
26 * content. */
27
28 /* ATTENTION:
29 * To have flash memory mapped in CPU memory space, the SMI controller
30 * have to be in "HW mode". This requires following constraints:
31 * 1) The command "reset init" have to initialize SMI controller and put
32 * it in HW mode;
33 * 2) every command in this file have to return to prompt in HW mode. */
34
35 #ifdef HAVE_CONFIG_H
36 #include "config.h"
37 #endif
38
39 #include "imp.h"
40 #include "spi.h"
41 #include <jtag/jtag.h>
42 #include <helper/time_support.h>
43
44 #define SMI_READ_REG(a) \
45 ({ \
46 int _ret; \
47 uint32_t _value; \
48 \
49 _ret = target_read_u32(target, io_base + (a), &_value); \
50 if (_ret != ERROR_OK) \
51 return _ret; \
52 _value; \
53 })
54
55 #define SMI_WRITE_REG(a, v) \
56 { \
57 int _retval; \
58 \
59 _retval = target_write_u32(target, io_base + (a), (v)); \
60 if (_retval != ERROR_OK) \
61 return _retval; \
62 }
63
64 #define SMI_POLL_TFF(timeout) \
65 { \
66 int _retval; \
67 \
68 _retval = poll_tff(target, io_base, timeout); \
69 if (_retval != ERROR_OK) \
70 return _retval; \
71 }
72
73 #define SMI_SET_SW_MODE() SMI_WRITE_REG(SMI_CR1, \
74 SMI_READ_REG(SMI_CR1) | SMI_SW_MODE)
75 #define SMI_SET_HWWB_MODE() SMI_WRITE_REG(SMI_CR1, \
76 (SMI_READ_REG(SMI_CR1) | SMI_WB_MODE) & ~SMI_SW_MODE)
77 #define SMI_SET_HW_MODE() SMI_WRITE_REG(SMI_CR1, \
78 SMI_READ_REG(SMI_CR1) & ~(SMI_SW_MODE | SMI_WB_MODE))
79 #define SMI_CLEAR_TFF() SMI_WRITE_REG(SMI_SR, ~SMI_TFF)
80
81 #define SMI_BANK_SIZE (0x01000000)
82
83 #define SMI_CR1 (0x00) /* Control register 1 */
84 #define SMI_CR2 (0x04) /* Control register 2 */
85 #define SMI_SR (0x08) /* Status register */
86 #define SMI_TR (0x0c) /* TX */
87 #define SMI_RR (0x10) /* RX */
88
89 /* fields in SMI_CR1 */
90 #define SMI_SW_MODE 0x10000000 /* set to enable SW Mode */
91 #define SMI_WB_MODE 0x20000000 /* Write Burst Mode */
92
93 /* fields in SMI_CR2 */
94 #define SMI_TX_LEN_1 0x00000001 /* data length = 1 byte */
95 #define SMI_TX_LEN_4 0x00000004 /* data length = 4 byte */
96 #define SMI_RX_LEN_3 0x00000030 /* data length = 3 byte */
97 #define SMI_SEND 0x00000080 /* Send data */
98 #define SMI_RSR 0x00000400 /* reads status reg */
99 #define SMI_WE 0x00000800 /* Write Enable */
100 #define SMI_SEL_BANK0 0x00000000 /* Select Bank0 */
101 #define SMI_SEL_BANK1 0x00001000 /* Select Bank1 */
102 #define SMI_SEL_BANK2 0x00002000 /* Select Bank2 */
103 #define SMI_SEL_BANK3 0x00003000 /* Select Bank3 */
104
105 /* fields in SMI_SR */
106 #define SMI_TFF 0x00000100 /* Transfer Finished Flag */
107
108 /* Commands */
109 #define SMI_READ_ID 0x0000009F /* Read Flash Identification */
110
111 /* Timeout in ms */
112 #define SMI_CMD_TIMEOUT (100)
113 #define SMI_PROBE_TIMEOUT (100)
114 #define SMI_MAX_TIMEOUT (3000)
115
116 struct stmsmi_flash_bank {
117 bool probed;
118 uint32_t io_base;
119 uint32_t bank_num;
120 const struct flash_device *dev;
121 };
122
123 struct stmsmi_target {
124 char *name;
125 uint32_t tap_idcode;
126 uint32_t smi_base;
127 uint32_t io_base;
128 };
129
130 static const struct stmsmi_target target_devices[] = {
131 /* name, tap_idcode, smi_base, io_base */
132 { "SPEAr3xx/6xx", 0x07926041, 0xf8000000, 0xfc000000 },
133 { "STR75x", 0x4f1f0041, 0x80000000, 0x90000000 },
134 { NULL, 0, 0, 0 }
135 };
136
137 FLASH_BANK_COMMAND_HANDLER(stmsmi_flash_bank_command)
138 {
139 struct stmsmi_flash_bank *stmsmi_info;
140
141 LOG_DEBUG("%s", __func__);
142
143 if (CMD_ARGC < 6)
144 return ERROR_COMMAND_SYNTAX_ERROR;
145
146 stmsmi_info = malloc(sizeof(struct stmsmi_flash_bank));
147 if (stmsmi_info == NULL) {
148 LOG_ERROR("not enough memory");
149 return ERROR_FAIL;
150 }
151
152 bank->driver_priv = stmsmi_info;
153 stmsmi_info->probed = false;
154
155 return ERROR_OK;
156 }
157
158 /* Poll transmit finished flag */
159 /* timeout in ms */
160 static int poll_tff(struct target *target, uint32_t io_base, int timeout)
161 {
162 int64_t endtime;
163
164 if (SMI_READ_REG(SMI_SR) & SMI_TFF)
165 return ERROR_OK;
166
167 endtime = timeval_ms() + timeout;
168 do {
169 alive_sleep(1);
170 if (SMI_READ_REG(SMI_SR) & SMI_TFF)
171 return ERROR_OK;
172 } while (timeval_ms() < endtime);
173
174 LOG_ERROR("Timeout while polling TFF");
175 return ERROR_FLASH_OPERATION_FAILED;
176 }
177
178 /* Read the status register of the external SPI flash chip.
179 * The operation is triggered by setting SMI_RSR bit.
180 * SMI sends the proper SPI command (0x05) and returns value in SMI_SR */
181 static int read_status_reg(struct flash_bank *bank, uint32_t *status)
182 {
183 struct target *target = bank->target;
184 struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
185 uint32_t io_base = stmsmi_info->io_base;
186
187 /* clear transmit finished flag */
188 SMI_CLEAR_TFF();
189
190 /* Read status */
191 SMI_WRITE_REG(SMI_CR2, stmsmi_info->bank_num | SMI_RSR);
192
193 /* Poll transmit finished flag */
194 SMI_POLL_TFF(SMI_CMD_TIMEOUT);
195
196 /* clear transmit finished flag */
197 SMI_CLEAR_TFF();
198
199 *status = SMI_READ_REG(SMI_SR) & 0x0000ffff;
200
201 /* clean-up SMI_CR2 */
202 SMI_WRITE_REG(SMI_CR2, 0); /* AB: Required ? */
203
204 return ERROR_OK;
205 }
206
207 /* check for WIP (write in progress) bit in status register */
208 /* timeout in ms */
209 static int wait_till_ready(struct flash_bank *bank, int timeout)
210 {
211 uint32_t status;
212 int retval;
213 int64_t endtime;
214
215 endtime = timeval_ms() + timeout;
216 do {
217 /* read flash status register */
218 retval = read_status_reg(bank, &status);
219 if (retval != ERROR_OK)
220 return retval;
221
222 if ((status & SPIFLASH_BSY_BIT) == 0)
223 return ERROR_OK;
224 alive_sleep(1);
225 } while (timeval_ms() < endtime);
226
227 LOG_ERROR("timeout");
228 return ERROR_FAIL;
229 }
230
231 /* Send "write enable" command to SPI flash chip.
232 * The operation is triggered by setting SMI_WE bit, and SMI sends
233 * the proper SPI command (0x06) */
234 static int smi_write_enable(struct flash_bank *bank)
235 {
236 struct target *target = bank->target;
237 struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
238 uint32_t io_base = stmsmi_info->io_base;
239 uint32_t status;
240 int retval;
241
242 /* Enter in HW mode */
243 SMI_SET_HW_MODE(); /* AB: is this correct ?*/
244
245 /* clear transmit finished flag */
246 SMI_CLEAR_TFF();
247
248 /* Send write enable command */
249 SMI_WRITE_REG(SMI_CR2, stmsmi_info->bank_num | SMI_WE);
250
251 /* Poll transmit finished flag */
252 SMI_POLL_TFF(SMI_CMD_TIMEOUT);
253
254 /* read flash status register */
255 retval = read_status_reg(bank, &status);
256 if (retval != ERROR_OK)
257 return retval;
258
259 /* Check write enabled */
260 if ((status & SPIFLASH_WE_BIT) == 0) {
261 LOG_ERROR("Cannot enable write to flash. Status=0x%08" PRIx32, status);
262 return ERROR_FAIL;
263 }
264
265 return ERROR_OK;
266 }
267
268 static uint32_t erase_command(struct stmsmi_flash_bank *stmsmi_info,
269 uint32_t offset)
270 {
271 uint8_t cmd_bytes[] = {
272 stmsmi_info->dev->erase_cmd,
273 offset >> 16,
274 offset >> 8,
275 offset
276 };
277
278 return le_to_h_u32(cmd_bytes);
279 }
280
281 static int smi_erase_sector(struct flash_bank *bank, int sector)
282 {
283 struct target *target = bank->target;
284 struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
285 uint32_t io_base = stmsmi_info->io_base;
286 uint32_t cmd;
287 int retval;
288
289 retval = smi_write_enable(bank);
290 if (retval != ERROR_OK)
291 return retval;
292
293 /* Switch to SW mode to send sector erase command */
294 SMI_SET_SW_MODE();
295
296 /* clear transmit finished flag */
297 SMI_CLEAR_TFF();
298
299 /* send SPI command "block erase" */
300 cmd = erase_command(stmsmi_info, bank->sectors[sector].offset);
301 SMI_WRITE_REG(SMI_TR, cmd);
302 SMI_WRITE_REG(SMI_CR2, stmsmi_info->bank_num | SMI_SEND | SMI_TX_LEN_4);
303
304 /* Poll transmit finished flag */
305 SMI_POLL_TFF(SMI_CMD_TIMEOUT);
306
307 /* poll WIP for end of self timed Sector Erase cycle */
308 retval = wait_till_ready(bank, SMI_MAX_TIMEOUT);
309 if (retval != ERROR_OK)
310 return retval;
311
312 return ERROR_OK;
313 }
314
315 static int stmsmi_erase(struct flash_bank *bank, unsigned int first,
316 unsigned int last)
317 {
318 struct target *target = bank->target;
319 struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
320 uint32_t io_base = stmsmi_info->io_base;
321 int retval = ERROR_OK;
322
323 LOG_DEBUG("%s: from sector %u to sector %u", __func__, first, last);
324
325 if (target->state != TARGET_HALTED) {
326 LOG_ERROR("Target not halted");
327 return ERROR_TARGET_NOT_HALTED;
328 }
329
330 if ((last < first) || (last >= bank->num_sectors)) {
331 LOG_ERROR("Flash sector invalid");
332 return ERROR_FLASH_SECTOR_INVALID;
333 }
334
335 if (!(stmsmi_info->probed)) {
336 LOG_ERROR("Flash bank not probed");
337 return ERROR_FLASH_BANK_NOT_PROBED;
338 }
339
340 for (unsigned int sector = first; sector <= last; sector++) {
341 if (bank->sectors[sector].is_protected) {
342 LOG_ERROR("Flash sector %u protected", sector);
343 return ERROR_FAIL;
344 }
345 }
346
347 if (stmsmi_info->dev->erase_cmd == 0x00)
348 return ERROR_FLASH_OPER_UNSUPPORTED;
349
350 for (unsigned int sector = first; sector <= last; sector++) {
351 retval = smi_erase_sector(bank, sector);
352 if (retval != ERROR_OK)
353 break;
354 keep_alive();
355 }
356
357 /* Switch to HW mode before return to prompt */
358 SMI_SET_HW_MODE();
359 return retval;
360 }
361
362 static int stmsmi_protect(struct flash_bank *bank, int set,
363 unsigned int first, unsigned int last)
364 {
365 for (unsigned int sector = first; sector <= last; sector++)
366 bank->sectors[sector].is_protected = set;
367 return ERROR_OK;
368 }
369
370 static int smi_write_buffer(struct flash_bank *bank, const uint8_t *buffer,
371 uint32_t address, uint32_t len)
372 {
373 struct target *target = bank->target;
374 struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
375 uint32_t io_base = stmsmi_info->io_base;
376 int retval;
377
378 LOG_DEBUG("%s: address=0x%08" PRIx32 " len=0x%08" PRIx32,
379 __func__, address, len);
380
381 retval = smi_write_enable(bank);
382 if (retval != ERROR_OK)
383 return retval;
384
385 /* HW mode, write burst mode */
386 SMI_SET_HWWB_MODE();
387
388 retval = target_write_buffer(target, address, len, buffer);
389 if (retval != ERROR_OK)
390 return retval;
391
392 return ERROR_OK;
393 }
394
395 static int stmsmi_write(struct flash_bank *bank, const uint8_t *buffer,
396 uint32_t offset, uint32_t count)
397 {
398 struct target *target = bank->target;
399 struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
400 uint32_t io_base = stmsmi_info->io_base;
401 uint32_t cur_count, page_size, page_offset;
402 int retval = ERROR_OK;
403
404 LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
405 __func__, offset, count);
406
407 if (target->state != TARGET_HALTED) {
408 LOG_ERROR("Target not halted");
409 return ERROR_TARGET_NOT_HALTED;
410 }
411
412 if (offset + count > stmsmi_info->dev->size_in_bytes) {
413 LOG_WARNING("Write pasts end of flash. Extra data discarded.");
414 count = stmsmi_info->dev->size_in_bytes - offset;
415 }
416
417 /* Check sector protection */
418 for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
419 /* Start offset in or before this sector? */
420 /* End offset in or behind this sector? */
421 if ((offset <
422 (bank->sectors[sector].offset + bank->sectors[sector].size))
423 && ((offset + count - 1) >= bank->sectors[sector].offset)
424 && bank->sectors[sector].is_protected) {
425 LOG_ERROR("Flash sector %u protected", sector);
426 return ERROR_FAIL;
427 }
428 }
429
430 /* if no valid page_size, use reasonable default */
431 page_size = stmsmi_info->dev->pagesize ?
432 stmsmi_info->dev->pagesize : SPIFLASH_DEF_PAGESIZE;
433
434 /* unaligned buffer head */
435 if (count > 0 && (offset & 3) != 0) {
436 cur_count = 4 - (offset & 3);
437 if (cur_count > count)
438 cur_count = count;
439 retval = smi_write_buffer(bank, buffer, bank->base + offset,
440 cur_count);
441 if (retval != ERROR_OK)
442 goto err;
443 offset += cur_count;
444 buffer += cur_count;
445 count -= cur_count;
446 }
447
448 page_offset = offset % page_size;
449 /* central part, aligned words */
450 while (count >= 4) {
451 /* clip block at page boundary */
452 if (page_offset + count > page_size)
453 cur_count = page_size - page_offset;
454 else
455 cur_count = count & ~3;
456
457 retval = smi_write_buffer(bank, buffer, bank->base + offset,
458 cur_count);
459 if (retval != ERROR_OK)
460 goto err;
461
462 page_offset = 0;
463 buffer += cur_count;
464 offset += cur_count;
465 count -= cur_count;
466
467 keep_alive();
468 }
469
470 /* buffer tail */
471 if (count > 0)
472 retval = smi_write_buffer(bank, buffer, bank->base + offset, count);
473
474 err:
475 /* Switch to HW mode before return to prompt */
476 SMI_SET_HW_MODE();
477 return retval;
478 }
479
480 /* Return ID of flash device */
481 /* On exit, SW mode is kept */
482 static int read_flash_id(struct flash_bank *bank, uint32_t *id)
483 {
484 struct target *target = bank->target;
485 struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
486 uint32_t io_base = stmsmi_info->io_base;
487 int retval;
488
489 if (target->state != TARGET_HALTED) {
490 LOG_ERROR("Target not halted");
491 return ERROR_TARGET_NOT_HALTED;
492 }
493
494 /* poll WIP */
495 retval = wait_till_ready(bank, SMI_PROBE_TIMEOUT);
496 if (retval != ERROR_OK)
497 return retval;
498
499 /* enter in SW mode */
500 SMI_SET_SW_MODE();
501
502 /* clear transmit finished flag */
503 SMI_CLEAR_TFF();
504
505 /* Send SPI command "read ID" */
506 SMI_WRITE_REG(SMI_TR, SMI_READ_ID);
507 SMI_WRITE_REG(SMI_CR2,
508 stmsmi_info->bank_num | SMI_SEND | SMI_RX_LEN_3 | SMI_TX_LEN_1);
509
510 /* Poll transmit finished flag */
511 SMI_POLL_TFF(SMI_CMD_TIMEOUT);
512
513 /* clear transmit finished flag */
514 SMI_CLEAR_TFF();
515
516 /* read ID from Receive Register */
517 *id = SMI_READ_REG(SMI_RR) & 0x00ffffff;
518 return ERROR_OK;
519 }
520
521 static int stmsmi_probe(struct flash_bank *bank)
522 {
523 struct target *target = bank->target;
524 struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
525 uint32_t io_base, sectorsize;
526 struct flash_sector *sectors;
527 uint32_t id = 0; /* silence uninitialized warning */
528 const struct stmsmi_target *target_device;
529 int retval;
530
531 if (stmsmi_info->probed)
532 free(bank->sectors);
533 stmsmi_info->probed = false;
534
535 for (target_device = target_devices ; target_device->name ; ++target_device)
536 if (target_device->tap_idcode == target->tap->idcode)
537 break;
538 if (!target_device->name) {
539 LOG_ERROR("Device ID 0x%" PRIx32 " is not known as SMI capable",
540 target->tap->idcode);
541 return ERROR_FAIL;
542 }
543
544 switch (bank->base - target_device->smi_base) {
545 case 0:
546 stmsmi_info->bank_num = SMI_SEL_BANK0;
547 break;
548 case SMI_BANK_SIZE:
549 stmsmi_info->bank_num = SMI_SEL_BANK1;
550 break;
551 case 2*SMI_BANK_SIZE:
552 stmsmi_info->bank_num = SMI_SEL_BANK2;
553 break;
554 case 3*SMI_BANK_SIZE:
555 stmsmi_info->bank_num = SMI_SEL_BANK3;
556 break;
557 default:
558 LOG_ERROR("Invalid SMI base address " TARGET_ADDR_FMT, bank->base);
559 return ERROR_FAIL;
560 }
561 io_base = target_device->io_base;
562 stmsmi_info->io_base = io_base;
563
564 LOG_DEBUG("Valid SMI on device %s at address " TARGET_ADDR_FMT,
565 target_device->name, bank->base);
566
567 /* read and decode flash ID; returns in SW mode */
568 retval = read_flash_id(bank, &id);
569 SMI_SET_HW_MODE();
570 if (retval != ERROR_OK)
571 return retval;
572
573 stmsmi_info->dev = NULL;
574 for (const struct flash_device *p = flash_devices; p->name ; p++)
575 if (p->device_id == id) {
576 stmsmi_info->dev = p;
577 break;
578 }
579
580 if (!stmsmi_info->dev) {
581 LOG_ERROR("Unknown flash device (ID 0x%08" PRIx32 ")", id);
582 return ERROR_FAIL;
583 }
584
585 LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32 ")",
586 stmsmi_info->dev->name, stmsmi_info->dev->device_id);
587
588 /* Set correct size value */
589 bank->size = stmsmi_info->dev->size_in_bytes;
590 if (bank->size <= (1UL << 16))
591 LOG_WARNING("device needs 2-byte addresses - not implemented");
592 if (bank->size > (1UL << 24))
593 LOG_WARNING("device needs paging or 4-byte addresses - not implemented");
594
595 /* if no sectors, treat whole bank as single sector */
596 sectorsize = stmsmi_info->dev->sectorsize ?
597 stmsmi_info->dev->sectorsize : stmsmi_info->dev->size_in_bytes;
598
599 /* create and fill sectors array */
600 bank->num_sectors =
601 stmsmi_info->dev->size_in_bytes / sectorsize;
602 sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
603 if (sectors == NULL) {
604 LOG_ERROR("not enough memory");
605 return ERROR_FAIL;
606 }
607
608 for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
609 sectors[sector].offset = sector * sectorsize;
610 sectors[sector].size = sectorsize;
611 sectors[sector].is_erased = -1;
612 sectors[sector].is_protected = 1;
613 }
614
615 bank->sectors = sectors;
616 stmsmi_info->probed = true;
617 return ERROR_OK;
618 }
619
620 static int stmsmi_auto_probe(struct flash_bank *bank)
621 {
622 struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
623 if (stmsmi_info->probed)
624 return ERROR_OK;
625 return stmsmi_probe(bank);
626 }
627
628 static int stmsmi_protect_check(struct flash_bank *bank)
629 {
630 /* Nothing to do. Protection is only handled in SW. */
631 return ERROR_OK;
632 }
633
634 static int get_stmsmi_info(struct flash_bank *bank, struct command_invocation *cmd)
635 {
636 struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
637
638 if (!(stmsmi_info->probed)) {
639 command_print_sameline(cmd, "\nSMI flash bank not probed yet\n");
640 return ERROR_OK;
641 }
642
643 command_print_sameline(cmd, "\nSMI flash information:\n"
644 " Device \'%s\' (ID 0x%08" PRIx32 ")\n",
645 stmsmi_info->dev->name, stmsmi_info->dev->device_id);
646
647 return ERROR_OK;
648 }
649
650 const struct flash_driver stmsmi_flash = {
651 .name = "stmsmi",
652 .flash_bank_command = stmsmi_flash_bank_command,
653 .erase = stmsmi_erase,
654 .protect = stmsmi_protect,
655 .write = stmsmi_write,
656 .read = default_flash_read,
657 .probe = stmsmi_probe,
658 .auto_probe = stmsmi_auto_probe,
659 .erase_check = default_flash_blank_check,
660 .protect_check = stmsmi_protect_check,
661 .info = get_stmsmi_info,
662 .free_driver_priv = default_flash_free_driver_priv,
663 };
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+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)