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[openocd.git] / src / flash / nor / str7x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2010 Øyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 #ifdef HAVE_CONFIG_H
27 #include "config.h"
28 #endif
29
30 #include "imp.h"
31 #include <target/arm.h>
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34
35
36 /* Flash registers */
37
38 #define FLASH_CR0 0x00000000
39 #define FLASH_CR1 0x00000004
40 #define FLASH_DR0 0x00000008
41 #define FLASH_DR1 0x0000000C
42 #define FLASH_AR 0x00000010
43 #define FLASH_ER 0x00000014
44 #define FLASH_NVWPAR 0x0000DFB0
45 #define FLASH_NVAPR0 0x0000DFB8
46 #define FLASH_NVAPR1 0x0000DFBC
47
48 /* FLASH_CR0 register bits */
49
50 #define FLASH_WMS 0x80000000
51 #define FLASH_SUSP 0x40000000
52 #define FLASH_WPG 0x20000000
53 #define FLASH_DWPG 0x10000000
54 #define FLASH_SER 0x08000000
55 #define FLASH_SPR 0x01000000
56 #define FLASH_BER 0x04000000
57 #define FLASH_MER 0x02000000
58 #define FLASH_LOCK 0x00000010
59 #define FLASH_BSYA1 0x00000004
60 #define FLASH_BSYA0 0x00000002
61
62 /* FLASH_CR1 register bits */
63
64 #define FLASH_B1S 0x02000000
65 #define FLASH_B0S 0x01000000
66 #define FLASH_B1F1 0x00020000
67 #define FLASH_B1F0 0x00010000
68 #define FLASH_B0F7 0x00000080
69 #define FLASH_B0F6 0x00000040
70 #define FLASH_B0F5 0x00000020
71 #define FLASH_B0F4 0x00000010
72 #define FLASH_B0F3 0x00000008
73 #define FLASH_B0F2 0x00000004
74 #define FLASH_B0F1 0x00000002
75 #define FLASH_B0F0 0x00000001
76
77 /* FLASH_ER register bits */
78
79 #define FLASH_WPF 0x00000100
80 #define FLASH_RESER 0x00000080
81 #define FLASH_SEQER 0x00000040
82 #define FLASH_10ER 0x00000008
83 #define FLASH_PGER 0x00000004
84 #define FLASH_ERER 0x00000002
85 #define FLASH_ERR 0x00000001
86
87
88 struct str7x_flash_bank
89 {
90 uint32_t *sector_bits;
91 uint32_t disable_bit;
92 uint32_t busy_bits;
93 uint32_t register_base;
94 struct working_area *write_algorithm;
95 };
96
97 struct str7x_mem_layout {
98 uint32_t sector_start;
99 uint32_t sector_size;
100 uint32_t sector_bit;
101 };
102
103 enum str7x_status_codes
104 {
105 STR7X_CMD_SUCCESS = 0,
106 STR7X_INVALID_COMMAND = 1,
107 STR7X_SRC_ADDR_ERROR = 2,
108 STR7X_DST_ADDR_ERROR = 3,
109 STR7X_SRC_ADDR_NOT_MAPPED = 4,
110 STR7X_DST_ADDR_NOT_MAPPED = 5,
111 STR7X_COUNT_ERROR = 6,
112 STR7X_INVALID_SECTOR = 7,
113 STR7X_SECTOR_NOT_BLANK = 8,
114 STR7X_SECTOR_NOT_PREPARED = 9,
115 STR7X_COMPARE_ERROR = 10,
116 STR7X_BUSY = 11
117 };
118
119 static struct str7x_mem_layout mem_layout_str7bank0[] = {
120 {0x00000000, 0x02000, 0x01},
121 {0x00002000, 0x02000, 0x02},
122 {0x00004000, 0x02000, 0x04},
123 {0x00006000, 0x02000, 0x08},
124 {0x00008000, 0x08000, 0x10},
125 {0x00010000, 0x10000, 0x20},
126 {0x00020000, 0x10000, 0x40},
127 {0x00030000, 0x10000, 0x80}
128 };
129
130 static struct str7x_mem_layout mem_layout_str7bank1[] = {
131 {0x00000000, 0x02000, 0x10000},
132 {0x00002000, 0x02000, 0x20000}
133 };
134
135 static int str7x_get_flash_adr(struct flash_bank *bank, uint32_t reg)
136 {
137 struct str7x_flash_bank *str7x_info = bank->driver_priv;
138 return (str7x_info->register_base | reg);
139 }
140
141 static int str7x_build_block_list(struct flash_bank *bank)
142 {
143 struct str7x_flash_bank *str7x_info = bank->driver_priv;
144
145 int i;
146 int num_sectors;
147 int b0_sectors = 0, b1_sectors = 0;
148
149 switch (bank->size)
150 {
151 case 16 * 1024:
152 b1_sectors = 2;
153 break;
154 case 64 * 1024:
155 b0_sectors = 5;
156 break;
157 case 128 * 1024:
158 b0_sectors = 6;
159 break;
160 case 256 * 1024:
161 b0_sectors = 8;
162 break;
163 default:
164 LOG_ERROR("BUG: unknown bank->size encountered");
165 exit(-1);
166 }
167
168 num_sectors = b0_sectors + b1_sectors;
169
170 bank->num_sectors = num_sectors;
171 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
172 str7x_info->sector_bits = malloc(sizeof(uint32_t) * num_sectors);
173
174 num_sectors = 0;
175
176 for (i = 0; i < b0_sectors; i++)
177 {
178 bank->sectors[num_sectors].offset = mem_layout_str7bank0[i].sector_start;
179 bank->sectors[num_sectors].size = mem_layout_str7bank0[i].sector_size;
180 bank->sectors[num_sectors].is_erased = -1;
181 /* the reset_init handler marks all the sectors unprotected,
182 * matching hardware after reset; keep the driver in sync
183 */
184 bank->sectors[num_sectors].is_protected = 0;
185 str7x_info->sector_bits[num_sectors++] = mem_layout_str7bank0[i].sector_bit;
186 }
187
188 for (i = 0; i < b1_sectors; i++)
189 {
190 bank->sectors[num_sectors].offset = mem_layout_str7bank1[i].sector_start;
191 bank->sectors[num_sectors].size = mem_layout_str7bank1[i].sector_size;
192 bank->sectors[num_sectors].is_erased = -1;
193 /* the reset_init handler marks all the sectors unprotected,
194 * matching hardware after reset; keep the driver in sync
195 */
196 bank->sectors[num_sectors].is_protected = 0;
197 str7x_info->sector_bits[num_sectors++] = mem_layout_str7bank1[i].sector_bit;
198 }
199
200 return ERROR_OK;
201 }
202
203 /* flash bank str7x <base> <size> 0 0 <target#> <str71_variant>
204 */
205 FLASH_BANK_COMMAND_HANDLER(str7x_flash_bank_command)
206 {
207 struct str7x_flash_bank *str7x_info;
208
209 if (CMD_ARGC < 7)
210 {
211 LOG_WARNING("incomplete flash_bank str7x configuration");
212 return ERROR_FLASH_BANK_INVALID;
213 }
214
215 str7x_info = malloc(sizeof(struct str7x_flash_bank));
216 bank->driver_priv = str7x_info;
217
218 /* set default bits for str71x flash */
219 str7x_info->busy_bits = (FLASH_LOCK | FLASH_BSYA1 | FLASH_BSYA0);
220 str7x_info->disable_bit = (1 << 1);
221
222 if (strcmp(CMD_ARGV[6], "STR71x") == 0)
223 {
224 str7x_info->register_base = 0x40100000;
225 }
226 else if (strcmp(CMD_ARGV[6], "STR73x") == 0)
227 {
228 str7x_info->register_base = 0x80100000;
229 str7x_info->busy_bits = (FLASH_LOCK | FLASH_BSYA0);
230 }
231 else if (strcmp(CMD_ARGV[6], "STR75x") == 0)
232 {
233 str7x_info->register_base = 0x20100000;
234 str7x_info->disable_bit = (1 << 0);
235 }
236 else
237 {
238 LOG_ERROR("unknown STR7x variant: '%s'", CMD_ARGV[6]);
239 free(str7x_info);
240 return ERROR_FLASH_BANK_INVALID;
241 }
242
243 str7x_build_block_list(bank);
244
245 str7x_info->write_algorithm = NULL;
246
247 return ERROR_OK;
248 }
249
250 /* wait for flash to become idle or report errors.
251
252 FIX!!! what's the maximum timeout??? The documentation doesn't
253 state any maximum time.... by inspection it seems > 1000ms is to be
254 expected.
255
256 10000ms is long enough that it should cover anything, yet not
257 quite be equivalent to an infinite loop.
258
259 */
260 static int str7x_waitbusy(struct flash_bank *bank)
261 {
262 int err;
263 int i;
264 struct target *target = bank->target;
265 struct str7x_flash_bank *str7x_info = bank->driver_priv;
266
267 for (i = 0 ; i < 10000; i++)
268 {
269 uint32_t retval;
270 err = target_read_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), &retval);
271 if (err != ERROR_OK)
272 return err;
273
274 if ((retval & str7x_info->busy_bits) == 0)
275 return ERROR_OK;
276
277 alive_sleep(1);
278 }
279 LOG_ERROR("Timed out waiting for str7x flash");
280 return ERROR_FAIL;
281 }
282
283
284 static int str7x_result(struct flash_bank *bank)
285 {
286 struct target *target = bank->target;
287 uint32_t flash_flags;
288
289 int retval;
290 retval = target_read_u32(target, str7x_get_flash_adr(bank, FLASH_ER), &flash_flags);
291 if (retval != ERROR_OK)
292 return retval;
293
294 if (flash_flags & FLASH_WPF)
295 {
296 LOG_ERROR("str7x hw write protection set");
297 retval = ERROR_FAIL;
298 }
299 if (flash_flags & FLASH_RESER)
300 {
301 LOG_ERROR("str7x suspended program erase not resumed");
302 retval = ERROR_FAIL;
303 }
304 if (flash_flags & FLASH_10ER)
305 {
306 LOG_ERROR("str7x trying to set bit to 1 when it is already 0");
307 retval = ERROR_FAIL;
308 }
309 if (flash_flags & FLASH_PGER)
310 {
311 LOG_ERROR("str7x program error");
312 retval = ERROR_FAIL;
313 }
314 if (flash_flags & FLASH_ERER)
315 {
316 LOG_ERROR("str7x erase error");
317 retval = ERROR_FAIL;
318 }
319 if (retval == ERROR_OK)
320 {
321 if (flash_flags & FLASH_ERR)
322 {
323 /* this should always be set if one of the others are set... */
324 LOG_ERROR("str7x write operation failed / bad setup");
325 retval = ERROR_FAIL;
326 }
327 }
328
329 return retval;
330 }
331
332 static int str7x_protect_check(struct flash_bank *bank)
333 {
334 struct str7x_flash_bank *str7x_info = bank->driver_priv;
335 struct target *target = bank->target;
336
337 int i;
338 uint32_t flash_flags;
339
340 if (bank->target->state != TARGET_HALTED)
341 {
342 LOG_ERROR("Target not halted");
343 return ERROR_TARGET_NOT_HALTED;
344 }
345
346 int retval;
347 retval = target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVWPAR), &flash_flags);
348 if (retval != ERROR_OK)
349 return retval;
350
351 for (i = 0; i < bank->num_sectors; i++)
352 {
353 if (flash_flags & str7x_info->sector_bits[i])
354 bank->sectors[i].is_protected = 0;
355 else
356 bank->sectors[i].is_protected = 1;
357 }
358
359 return ERROR_OK;
360 }
361
362 static int str7x_erase(struct flash_bank *bank, int first, int last)
363 {
364 struct str7x_flash_bank *str7x_info = bank->driver_priv;
365 struct target *target = bank->target;
366
367 int i;
368 uint32_t cmd;
369 uint32_t sectors = 0;
370 int err;
371
372 if (bank->target->state != TARGET_HALTED)
373 {
374 LOG_ERROR("Target not halted");
375 return ERROR_TARGET_NOT_HALTED;
376 }
377
378 for (i = first; i <= last; i++)
379 {
380 sectors |= str7x_info->sector_bits[i];
381 }
382
383 LOG_DEBUG("sectors: 0x%" PRIx32 "", sectors);
384
385 /* clear FLASH_ER register */
386 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
387 if (err != ERROR_OK)
388 return err;
389
390 cmd = FLASH_SER;
391 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
392 if (err != ERROR_OK)
393 return err;
394
395 cmd = sectors;
396 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR1), cmd);
397 if (err != ERROR_OK)
398 return err;
399
400 cmd = FLASH_SER | FLASH_WMS;
401 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
402 if (err != ERROR_OK)
403 return err;
404
405 err = str7x_waitbusy(bank);
406 if (err != ERROR_OK)
407 return err;
408
409 err = str7x_result(bank);
410 if (err != ERROR_OK)
411 return err;
412
413 for (i = first; i <= last; i++)
414 bank->sectors[i].is_erased = 1;
415
416 return ERROR_OK;
417 }
418
419 static int str7x_protect(struct flash_bank *bank, int set, int first, int last)
420 {
421 struct str7x_flash_bank *str7x_info = bank->driver_priv;
422 struct target *target = bank->target;
423 int i;
424 uint32_t cmd;
425 uint32_t protect_blocks;
426
427 if (bank->target->state != TARGET_HALTED)
428 {
429 LOG_ERROR("Target not halted");
430 return ERROR_TARGET_NOT_HALTED;
431 }
432
433 protect_blocks = 0xFFFFFFFF;
434
435 if (set)
436 {
437 for (i = first; i <= last; i++)
438 protect_blocks &= ~(str7x_info->sector_bits[i]);
439 }
440
441 /* clear FLASH_ER register */
442 int err;
443 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
444 if (err != ERROR_OK)
445 return err;
446
447 cmd = FLASH_SPR;
448 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
449 if (err != ERROR_OK)
450 return err;
451
452 cmd = str7x_get_flash_adr(bank, FLASH_NVWPAR);
453 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), cmd);
454 if (err != ERROR_OK)
455 return err;
456
457 cmd = protect_blocks;
458 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), cmd);
459 if (err != ERROR_OK)
460 return err;
461
462 cmd = FLASH_SPR | FLASH_WMS;
463 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
464 if (err != ERROR_OK)
465 return err;
466
467 err = str7x_waitbusy(bank);
468 if (err != ERROR_OK)
469 return err;
470
471 err = str7x_result(bank);
472 if (err != ERROR_OK)
473 return err;
474
475 return ERROR_OK;
476 }
477
478 static int str7x_write_block(struct flash_bank *bank, uint8_t *buffer,
479 uint32_t offset, uint32_t count)
480 {
481 struct str7x_flash_bank *str7x_info = bank->driver_priv;
482 struct target *target = bank->target;
483 uint32_t buffer_size = 32768;
484 struct working_area *source;
485 uint32_t address = bank->base + offset;
486 struct reg_param reg_params[6];
487 struct arm_algorithm armv4_5_info;
488 int retval = ERROR_OK;
489
490 /* see contib/loaders/flash/str7x.s for src */
491
492 static const uint32_t str7x_flash_write_code[] = {
493 /* write: */
494 0xe3a04201, /* mov r4, #0x10000000 */
495 0xe5824000, /* str r4, [r2, #0x0] */
496 0xe5821010, /* str r1, [r2, #0x10] */
497 0xe4904004, /* ldr r4, [r0], #4 */
498 0xe5824008, /* str r4, [r2, #0x8] */
499 0xe4904004, /* ldr r4, [r0], #4 */
500 0xe582400c, /* str r4, [r2, #0xc] */
501 0xe3a04209, /* mov r4, #0x90000000 */
502 0xe5824000, /* str r4, [r2, #0x0] */
503 /* busy: */
504 0xe5924000, /* ldr r4, [r2, #0x0] */
505 0xe1140005, /* tst r4, r5 */
506 0x1afffffc, /* bne busy */
507 0xe5924014, /* ldr r4, [r2, #0x14] */
508 0xe31400ff, /* tst r4, #0xff */
509 0x03140c01, /* tsteq r4, #0x100 */
510 0x1a000002, /* bne exit */
511 0xe2811008, /* add r1, r1, #0x8 */
512 0xe2533001, /* subs r3, r3, #1 */
513 0x1affffec, /* bne write */
514 /* exit: */
515 0xeafffffe, /* b exit */
516 };
517
518 /* flash write code */
519 if (target_alloc_working_area_try(target, sizeof(str7x_flash_write_code),
520 &str7x_info->write_algorithm) != ERROR_OK)
521 {
522 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
523 };
524
525 target_write_buffer(target, str7x_info->write_algorithm->address,
526 sizeof(str7x_flash_write_code),
527 (uint8_t*)str7x_flash_write_code);
528
529 /* memory buffer */
530 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
531 {
532 buffer_size /= 2;
533 if (buffer_size <= 256)
534 {
535 /* if we already allocated the writing code, but failed to get a
536 * buffer, free the algorithm */
537 if (str7x_info->write_algorithm)
538 target_free_working_area(target, str7x_info->write_algorithm);
539
540 LOG_WARNING("no large enough working area available, can't do block memory writes");
541 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
542 }
543 }
544
545 armv4_5_info.common_magic = ARM_COMMON_MAGIC;
546 armv4_5_info.core_mode = ARM_MODE_SVC;
547 armv4_5_info.core_state = ARM_STATE_ARM;
548
549 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
550 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
551 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
552 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
553 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
554 init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
555
556 while (count > 0)
557 {
558 uint32_t thisrun_count = (count > (buffer_size / 8)) ? (buffer_size / 8) : count;
559
560 target_write_buffer(target, source->address, thisrun_count * 8, buffer);
561
562 buf_set_u32(reg_params[0].value, 0, 32, source->address);
563 buf_set_u32(reg_params[1].value, 0, 32, address);
564 buf_set_u32(reg_params[2].value, 0, 32, str7x_get_flash_adr(bank, FLASH_CR0));
565 buf_set_u32(reg_params[3].value, 0, 32, thisrun_count);
566 buf_set_u32(reg_params[5].value, 0, 32, str7x_info->busy_bits);
567
568 if ((retval = target_run_algorithm(target, 0, NULL, 6, reg_params,
569 str7x_info->write_algorithm->address,
570 str7x_info->write_algorithm->address + (sizeof(str7x_flash_write_code) - 4),
571 10000, &armv4_5_info)) != ERROR_OK)
572 {
573 break;
574 }
575
576 if (buf_get_u32(reg_params[4].value, 0, 32) != 0x00)
577 {
578 retval = str7x_result(bank);
579 break;
580 }
581
582 buffer += thisrun_count * 8;
583 address += thisrun_count * 8;
584 count -= thisrun_count;
585 }
586
587 target_free_working_area(target, source);
588 target_free_working_area(target, str7x_info->write_algorithm);
589
590 destroy_reg_param(&reg_params[0]);
591 destroy_reg_param(&reg_params[1]);
592 destroy_reg_param(&reg_params[2]);
593 destroy_reg_param(&reg_params[3]);
594 destroy_reg_param(&reg_params[4]);
595 destroy_reg_param(&reg_params[5]);
596
597 return retval;
598 }
599
600 static int str7x_write(struct flash_bank *bank, uint8_t *buffer,
601 uint32_t offset, uint32_t count)
602 {
603 struct target *target = bank->target;
604 uint32_t dwords_remaining = (count / 8);
605 uint32_t bytes_remaining = (count & 0x00000007);
606 uint32_t address = bank->base + offset;
607 uint32_t bytes_written = 0;
608 uint32_t cmd;
609 int retval;
610 uint32_t check_address = offset;
611 int i;
612
613 if (bank->target->state != TARGET_HALTED)
614 {
615 LOG_ERROR("Target not halted");
616 return ERROR_TARGET_NOT_HALTED;
617 }
618
619 if (offset & 0x7)
620 {
621 LOG_WARNING("offset 0x%" PRIx32 " breaks required 8-byte alignment", offset);
622 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
623 }
624
625 for (i = 0; i < bank->num_sectors; i++)
626 {
627 uint32_t sec_start = bank->sectors[i].offset;
628 uint32_t sec_end = sec_start + bank->sectors[i].size;
629
630 /* check if destination falls within the current sector */
631 if ((check_address >= sec_start) && (check_address < sec_end))
632 {
633 /* check if destination ends in the current sector */
634 if (offset + count < sec_end)
635 check_address = offset + count;
636 else
637 check_address = sec_end;
638 }
639 }
640
641 if (check_address != offset + count)
642 return ERROR_FLASH_DST_OUT_OF_BANK;
643
644 /* clear FLASH_ER register */
645 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
646
647 /* multiple dwords (8-byte) to be programmed? */
648 if (dwords_remaining > 0)
649 {
650 /* try using a block write */
651 if ((retval = str7x_write_block(bank, buffer, offset,
652 dwords_remaining)) != ERROR_OK)
653 {
654 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
655 {
656 /* if block write failed (no sufficient working area),
657 * we use normal (slow) single dword accesses */
658 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
659 } else
660 {
661 return retval;
662 }
663 }
664 else
665 {
666 buffer += dwords_remaining * 8;
667 address += dwords_remaining * 8;
668 dwords_remaining = 0;
669 }
670 }
671
672 while (dwords_remaining > 0)
673 {
674 /* command */
675 cmd = FLASH_DWPG;
676 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
677
678 /* address */
679 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
680
681 /* data word 1 */
682 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0),
683 4, 1, buffer + bytes_written);
684 bytes_written += 4;
685
686 /* data word 2 */
687 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1),
688 4, 1, buffer + bytes_written);
689 bytes_written += 4;
690
691 /* start programming cycle */
692 cmd = FLASH_DWPG | FLASH_WMS;
693 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
694
695 int err;
696 err = str7x_waitbusy(bank);
697 if (err != ERROR_OK)
698 return err;
699
700 err = str7x_result(bank);
701 if (err != ERROR_OK)
702 return err;
703
704 dwords_remaining--;
705 address += 8;
706 }
707
708 if (bytes_remaining)
709 {
710 uint8_t last_dword[8] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
711 i = 0;
712
713 while (bytes_remaining > 0)
714 {
715 last_dword[i++] = *(buffer + bytes_written);
716 bytes_remaining--;
717 bytes_written++;
718 }
719
720 /* command */
721 cmd = FLASH_DWPG;
722 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
723
724 /* address */
725 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
726
727 /* data word 1 */
728 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0),
729 4, 1, last_dword);
730 bytes_written += 4;
731
732 /* data word 2 */
733 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1),
734 4, 1, last_dword + 4);
735 bytes_written += 4;
736
737 /* start programming cycle */
738 cmd = FLASH_DWPG | FLASH_WMS;
739 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
740
741 int err;
742 err = str7x_waitbusy(bank);
743 if (err != ERROR_OK)
744 return err;
745
746 err = str7x_result(bank);
747 if (err != ERROR_OK)
748 return err;
749 }
750
751 return ERROR_OK;
752 }
753
754 static int str7x_probe(struct flash_bank *bank)
755 {
756 return ERROR_OK;
757 }
758
759 #if 0
760 COMMAND_HANDLER(str7x_handle_part_id_command)
761 {
762 return ERROR_OK;
763 }
764 #endif
765
766 static int get_str7x_info(struct flash_bank *bank, char *buf, int buf_size)
767 {
768 snprintf(buf, buf_size, "str7x flash driver info");
769 /* STR7x flash doesn't support sector protection interrogation.
770 * FLASH_NVWPAR acts as a write only register; its read value
771 * doesn't reflect the actual protection state of the sectors.
772 */
773 LOG_WARNING("STR7x flash lock information might not be correct "
774 "due to hardware limitations.");
775 return ERROR_OK;
776 }
777
778 COMMAND_HANDLER(str7x_handle_disable_jtag_command)
779 {
780 struct target *target = NULL;
781 struct str7x_flash_bank *str7x_info = NULL;
782
783 uint32_t flash_cmd;
784 uint16_t ProtectionLevel = 0;
785 uint16_t ProtectionRegs;
786
787 if (CMD_ARGC < 1)
788 {
789 command_print(CMD_CTX, "str7x disable_jtag <bank>");
790 return ERROR_OK;
791 }
792
793 struct flash_bank *bank;
794 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
795 if (ERROR_OK != retval)
796 return retval;
797
798 str7x_info = bank->driver_priv;
799
800 target = bank->target;
801
802 if (target->state != TARGET_HALTED)
803 {
804 LOG_ERROR("Target not halted");
805 return ERROR_TARGET_NOT_HALTED;
806 }
807
808 /* first we get protection status */
809 uint32_t reg;
810 target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR0), &reg);
811
812 if (!(reg & str7x_info->disable_bit))
813 {
814 ProtectionLevel = 1;
815 }
816
817 target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR1), &reg);
818 ProtectionRegs = ~(reg >> 16);
819
820 while (((ProtectionRegs) != 0) && (ProtectionLevel < 16))
821 {
822 ProtectionRegs >>= 1;
823 ProtectionLevel++;
824 }
825
826 if (ProtectionLevel == 0)
827 {
828 flash_cmd = FLASH_SPR;
829 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
830 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFB8);
831 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), 0xFFFFFFFD);
832 flash_cmd = FLASH_SPR | FLASH_WMS;
833 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
834 }
835 else
836 {
837 flash_cmd = FLASH_SPR;
838 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
839 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFBC);
840 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0),
841 ~(1 << (15 + ProtectionLevel)));
842 flash_cmd = FLASH_SPR | FLASH_WMS;
843 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
844 }
845
846 return ERROR_OK;
847 }
848
849 static const struct command_registration str7x_exec_command_handlers[] = {
850 {
851 .name = "disable_jtag",
852 .handler = str7x_handle_disable_jtag_command,
853 .mode = COMMAND_EXEC,
854 .help = "disable jtag access",
855 },
856 COMMAND_REGISTRATION_DONE
857 };
858
859 static const struct command_registration str7x_command_handlers[] = {
860 {
861 .name = "str7x",
862 .mode = COMMAND_ANY,
863 .help = "str7x flash command group",
864 .chain = str7x_exec_command_handlers,
865 },
866 COMMAND_REGISTRATION_DONE
867 };
868
869 struct flash_driver str7x_flash = {
870 .name = "str7x",
871 .commands = str7x_command_handlers,
872 .flash_bank_command = str7x_flash_bank_command,
873 .erase = str7x_erase,
874 .protect = str7x_protect,
875 .write = str7x_write,
876 .read = default_flash_read,
877 .probe = str7x_probe,
878 .auto_probe = str7x_probe,
879 .erase_check = default_flash_blank_check,
880 .protect_check = str7x_protect_check,
881 .info = get_str7x_info,
882 };
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