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flash/nor: improved API of flash_driver.info & fixed buffer overruns
[openocd.git] / src / flash / nor / str7x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2010 Øyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "imp.h"
30 #include <target/arm.h>
31 #include <helper/binarybuffer.h>
32 #include <target/algorithm.h>
33
34 /* Flash registers */
35
36 #define FLASH_CR0 0x00000000
37 #define FLASH_CR1 0x00000004
38 #define FLASH_DR0 0x00000008
39 #define FLASH_DR1 0x0000000C
40 #define FLASH_AR 0x00000010
41 #define FLASH_ER 0x00000014
42 #define FLASH_NVWPAR 0x0000DFB0
43 #define FLASH_NVAPR0 0x0000DFB8
44 #define FLASH_NVAPR1 0x0000DFBC
45
46 /* FLASH_CR0 register bits */
47
48 #define FLASH_WMS 0x80000000
49 #define FLASH_SUSP 0x40000000
50 #define FLASH_WPG 0x20000000
51 #define FLASH_DWPG 0x10000000
52 #define FLASH_SER 0x08000000
53 #define FLASH_SPR 0x01000000
54 #define FLASH_BER 0x04000000
55 #define FLASH_MER 0x02000000
56 #define FLASH_LOCK 0x00000010
57 #define FLASH_BSYA1 0x00000004
58 #define FLASH_BSYA0 0x00000002
59
60 /* FLASH_CR1 register bits */
61
62 #define FLASH_B1S 0x02000000
63 #define FLASH_B0S 0x01000000
64 #define FLASH_B1F1 0x00020000
65 #define FLASH_B1F0 0x00010000
66 #define FLASH_B0F7 0x00000080
67 #define FLASH_B0F6 0x00000040
68 #define FLASH_B0F5 0x00000020
69 #define FLASH_B0F4 0x00000010
70 #define FLASH_B0F3 0x00000008
71 #define FLASH_B0F2 0x00000004
72 #define FLASH_B0F1 0x00000002
73 #define FLASH_B0F0 0x00000001
74
75 /* FLASH_ER register bits */
76
77 #define FLASH_WPF 0x00000100
78 #define FLASH_RESER 0x00000080
79 #define FLASH_SEQER 0x00000040
80 #define FLASH_10ER 0x00000008
81 #define FLASH_PGER 0x00000004
82 #define FLASH_ERER 0x00000002
83 #define FLASH_ERR 0x00000001
84
85
86 struct str7x_flash_bank {
87 uint32_t *sector_bits;
88 uint32_t disable_bit;
89 uint32_t busy_bits;
90 uint32_t register_base;
91 };
92
93 struct str7x_mem_layout {
94 uint32_t sector_start;
95 uint32_t sector_size;
96 uint32_t sector_bit;
97 };
98
99 enum str7x_status_codes {
100 STR7X_CMD_SUCCESS = 0,
101 STR7X_INVALID_COMMAND = 1,
102 STR7X_SRC_ADDR_ERROR = 2,
103 STR7X_DST_ADDR_ERROR = 3,
104 STR7X_SRC_ADDR_NOT_MAPPED = 4,
105 STR7X_DST_ADDR_NOT_MAPPED = 5,
106 STR7X_COUNT_ERROR = 6,
107 STR7X_INVALID_SECTOR = 7,
108 STR7X_SECTOR_NOT_BLANK = 8,
109 STR7X_SECTOR_NOT_PREPARED = 9,
110 STR7X_COMPARE_ERROR = 10,
111 STR7X_BUSY = 11
112 };
113
114 static const struct str7x_mem_layout mem_layout_str7bank0[] = {
115 {0x00000000, 0x02000, 0x01},
116 {0x00002000, 0x02000, 0x02},
117 {0x00004000, 0x02000, 0x04},
118 {0x00006000, 0x02000, 0x08},
119 {0x00008000, 0x08000, 0x10},
120 {0x00010000, 0x10000, 0x20},
121 {0x00020000, 0x10000, 0x40},
122 {0x00030000, 0x10000, 0x80}
123 };
124
125 static const struct str7x_mem_layout mem_layout_str7bank1[] = {
126 {0x00000000, 0x02000, 0x10000},
127 {0x00002000, 0x02000, 0x20000}
128 };
129
130 static int str7x_get_flash_adr(struct flash_bank *bank, uint32_t reg)
131 {
132 struct str7x_flash_bank *str7x_info = bank->driver_priv;
133 return str7x_info->register_base | reg;
134 }
135
136 static int str7x_build_block_list(struct flash_bank *bank)
137 {
138 struct str7x_flash_bank *str7x_info = bank->driver_priv;
139
140 int i;
141 unsigned int num_sectors;
142 int b0_sectors = 0, b1_sectors = 0;
143
144 switch (bank->size) {
145 case 16 * 1024:
146 b1_sectors = 2;
147 break;
148 case 64 * 1024:
149 b0_sectors = 5;
150 break;
151 case 128 * 1024:
152 b0_sectors = 6;
153 break;
154 case 256 * 1024:
155 b0_sectors = 8;
156 break;
157 default:
158 LOG_ERROR("BUG: unknown bank->size encountered");
159 exit(-1);
160 }
161
162 num_sectors = b0_sectors + b1_sectors;
163
164 bank->num_sectors = num_sectors;
165 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
166 str7x_info->sector_bits = malloc(sizeof(uint32_t) * num_sectors);
167
168 num_sectors = 0;
169
170 for (i = 0; i < b0_sectors; i++) {
171 bank->sectors[num_sectors].offset = mem_layout_str7bank0[i].sector_start;
172 bank->sectors[num_sectors].size = mem_layout_str7bank0[i].sector_size;
173 bank->sectors[num_sectors].is_erased = -1;
174 /* the reset_init handler marks all the sectors unprotected,
175 * matching hardware after reset; keep the driver in sync
176 */
177 bank->sectors[num_sectors].is_protected = 0;
178 str7x_info->sector_bits[num_sectors++] = mem_layout_str7bank0[i].sector_bit;
179 }
180
181 for (i = 0; i < b1_sectors; i++) {
182 bank->sectors[num_sectors].offset = mem_layout_str7bank1[i].sector_start;
183 bank->sectors[num_sectors].size = mem_layout_str7bank1[i].sector_size;
184 bank->sectors[num_sectors].is_erased = -1;
185 /* the reset_init handler marks all the sectors unprotected,
186 * matching hardware after reset; keep the driver in sync
187 */
188 bank->sectors[num_sectors].is_protected = 0;
189 str7x_info->sector_bits[num_sectors++] = mem_layout_str7bank1[i].sector_bit;
190 }
191
192 return ERROR_OK;
193 }
194
195 /* flash bank str7x <base> <size> 0 0 <target#> <str71_variant>
196 */
197 FLASH_BANK_COMMAND_HANDLER(str7x_flash_bank_command)
198 {
199 struct str7x_flash_bank *str7x_info;
200
201 if (CMD_ARGC < 7)
202 return ERROR_COMMAND_SYNTAX_ERROR;
203
204 str7x_info = malloc(sizeof(struct str7x_flash_bank));
205 bank->driver_priv = str7x_info;
206
207 /* set default bits for str71x flash */
208 str7x_info->busy_bits = (FLASH_LOCK | FLASH_BSYA1 | FLASH_BSYA0);
209 str7x_info->disable_bit = (1 << 1);
210
211 if (strcmp(CMD_ARGV[6], "STR71x") == 0)
212 str7x_info->register_base = 0x40100000;
213 else if (strcmp(CMD_ARGV[6], "STR73x") == 0) {
214 str7x_info->register_base = 0x80100000;
215 str7x_info->busy_bits = (FLASH_LOCK | FLASH_BSYA0);
216 } else if (strcmp(CMD_ARGV[6], "STR75x") == 0) {
217 str7x_info->register_base = 0x20100000;
218 str7x_info->disable_bit = (1 << 0);
219 } else {
220 LOG_ERROR("unknown STR7x variant: '%s'", CMD_ARGV[6]);
221 free(str7x_info);
222 return ERROR_FLASH_BANK_INVALID;
223 }
224
225 str7x_build_block_list(bank);
226
227 return ERROR_OK;
228 }
229
230 /* wait for flash to become idle or report errors.
231
232 FIX!!! what's the maximum timeout??? The documentation doesn't
233 state any maximum time.... by inspection it seems > 1000ms is to be
234 expected.
235
236 10000ms is long enough that it should cover anything, yet not
237 quite be equivalent to an infinite loop.
238
239 */
240 static int str7x_waitbusy(struct flash_bank *bank)
241 {
242 int err;
243 int i;
244 struct target *target = bank->target;
245 struct str7x_flash_bank *str7x_info = bank->driver_priv;
246
247 for (i = 0 ; i < 10000; i++) {
248 uint32_t retval;
249 err = target_read_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), &retval);
250 if (err != ERROR_OK)
251 return err;
252
253 if ((retval & str7x_info->busy_bits) == 0)
254 return ERROR_OK;
255
256 alive_sleep(1);
257 }
258 LOG_ERROR("Timed out waiting for str7x flash");
259 return ERROR_FAIL;
260 }
261
262
263 static int str7x_result(struct flash_bank *bank)
264 {
265 struct target *target = bank->target;
266 uint32_t flash_flags;
267
268 int retval;
269 retval = target_read_u32(target, str7x_get_flash_adr(bank, FLASH_ER), &flash_flags);
270 if (retval != ERROR_OK)
271 return retval;
272
273 if (flash_flags & FLASH_WPF) {
274 LOG_ERROR("str7x hw write protection set");
275 retval = ERROR_FAIL;
276 }
277 if (flash_flags & FLASH_RESER) {
278 LOG_ERROR("str7x suspended program erase not resumed");
279 retval = ERROR_FAIL;
280 }
281 if (flash_flags & FLASH_10ER) {
282 LOG_ERROR("str7x trying to set bit to 1 when it is already 0");
283 retval = ERROR_FAIL;
284 }
285 if (flash_flags & FLASH_PGER) {
286 LOG_ERROR("str7x program error");
287 retval = ERROR_FAIL;
288 }
289 if (flash_flags & FLASH_ERER) {
290 LOG_ERROR("str7x erase error");
291 retval = ERROR_FAIL;
292 }
293 if (retval == ERROR_OK) {
294 if (flash_flags & FLASH_ERR) {
295 /* this should always be set if one of the others are set... */
296 LOG_ERROR("str7x write operation failed / bad setup");
297 retval = ERROR_FAIL;
298 }
299 }
300
301 return retval;
302 }
303
304 static int str7x_protect_check(struct flash_bank *bank)
305 {
306 struct str7x_flash_bank *str7x_info = bank->driver_priv;
307 struct target *target = bank->target;
308
309 uint32_t flash_flags;
310
311 if (bank->target->state != TARGET_HALTED) {
312 LOG_ERROR("Target not halted");
313 return ERROR_TARGET_NOT_HALTED;
314 }
315
316 int retval;
317 retval = target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVWPAR), &flash_flags);
318 if (retval != ERROR_OK)
319 return retval;
320
321 for (unsigned int i = 0; i < bank->num_sectors; i++) {
322 if (flash_flags & str7x_info->sector_bits[i])
323 bank->sectors[i].is_protected = 0;
324 else
325 bank->sectors[i].is_protected = 1;
326 }
327
328 return ERROR_OK;
329 }
330
331 static int str7x_erase(struct flash_bank *bank, unsigned int first,
332 unsigned int last)
333 {
334 struct str7x_flash_bank *str7x_info = bank->driver_priv;
335 struct target *target = bank->target;
336
337 uint32_t cmd;
338 uint32_t sectors = 0;
339 int err;
340
341 if (bank->target->state != TARGET_HALTED) {
342 LOG_ERROR("Target not halted");
343 return ERROR_TARGET_NOT_HALTED;
344 }
345
346 for (unsigned int i = first; i <= last; i++)
347 sectors |= str7x_info->sector_bits[i];
348
349 LOG_DEBUG("sectors: 0x%" PRIx32 "", sectors);
350
351 /* clear FLASH_ER register */
352 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
353 if (err != ERROR_OK)
354 return err;
355
356 cmd = FLASH_SER;
357 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
358 if (err != ERROR_OK)
359 return err;
360
361 cmd = sectors;
362 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR1), cmd);
363 if (err != ERROR_OK)
364 return err;
365
366 cmd = FLASH_SER | FLASH_WMS;
367 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
368 if (err != ERROR_OK)
369 return err;
370
371 err = str7x_waitbusy(bank);
372 if (err != ERROR_OK)
373 return err;
374
375 err = str7x_result(bank);
376 if (err != ERROR_OK)
377 return err;
378
379 for (unsigned int i = first; i <= last; i++)
380 bank->sectors[i].is_erased = 1;
381
382 return ERROR_OK;
383 }
384
385 static int str7x_protect(struct flash_bank *bank, int set, unsigned int first,
386 unsigned int last)
387 {
388 struct str7x_flash_bank *str7x_info = bank->driver_priv;
389 struct target *target = bank->target;
390 uint32_t cmd;
391 uint32_t protect_blocks;
392
393 if (bank->target->state != TARGET_HALTED) {
394 LOG_ERROR("Target not halted");
395 return ERROR_TARGET_NOT_HALTED;
396 }
397
398 protect_blocks = 0xFFFFFFFF;
399
400 if (set) {
401 for (unsigned int i = first; i <= last; i++)
402 protect_blocks &= ~(str7x_info->sector_bits[i]);
403 }
404
405 /* clear FLASH_ER register */
406 int err;
407 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
408 if (err != ERROR_OK)
409 return err;
410
411 cmd = FLASH_SPR;
412 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
413 if (err != ERROR_OK)
414 return err;
415
416 cmd = str7x_get_flash_adr(bank, FLASH_NVWPAR);
417 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), cmd);
418 if (err != ERROR_OK)
419 return err;
420
421 cmd = protect_blocks;
422 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), cmd);
423 if (err != ERROR_OK)
424 return err;
425
426 cmd = FLASH_SPR | FLASH_WMS;
427 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
428 if (err != ERROR_OK)
429 return err;
430
431 err = str7x_waitbusy(bank);
432 if (err != ERROR_OK)
433 return err;
434
435 err = str7x_result(bank);
436 if (err != ERROR_OK)
437 return err;
438
439 return ERROR_OK;
440 }
441
442 static int str7x_write_block(struct flash_bank *bank, const uint8_t *buffer,
443 uint32_t offset, uint32_t count)
444 {
445 struct str7x_flash_bank *str7x_info = bank->driver_priv;
446 struct target *target = bank->target;
447 uint32_t buffer_size = 32768;
448 struct working_area *write_algorithm;
449 struct working_area *source;
450 uint32_t address = bank->base + offset;
451 struct reg_param reg_params[6];
452 struct arm_algorithm arm_algo;
453 int retval = ERROR_OK;
454
455 /* see contrib/loaders/flash/str7x.s for src */
456
457 static const uint32_t str7x_flash_write_code[] = {
458 /* write: */
459 0xe3a04201, /* mov r4, #0x10000000 */
460 0xe5824000, /* str r4, [r2, #0x0] */
461 0xe5821010, /* str r1, [r2, #0x10] */
462 0xe4904004, /* ldr r4, [r0], #4 */
463 0xe5824008, /* str r4, [r2, #0x8] */
464 0xe4904004, /* ldr r4, [r0], #4 */
465 0xe582400c, /* str r4, [r2, #0xc] */
466 0xe3a04209, /* mov r4, #0x90000000 */
467 0xe5824000, /* str r4, [r2, #0x0] */
468 /* busy: */
469 0xe5924000, /* ldr r4, [r2, #0x0] */
470 0xe1140005, /* tst r4, r5 */
471 0x1afffffc, /* bne busy */
472 0xe5924014, /* ldr r4, [r2, #0x14] */
473 0xe31400ff, /* tst r4, #0xff */
474 0x03140c01, /* tsteq r4, #0x100 */
475 0x1a000002, /* bne exit */
476 0xe2811008, /* add r1, r1, #0x8 */
477 0xe2533001, /* subs r3, r3, #1 */
478 0x1affffec, /* bne write */
479 /* exit: */
480 0xeafffffe, /* b exit */
481 };
482
483 /* flash write code */
484 if (target_alloc_working_area_try(target, sizeof(str7x_flash_write_code),
485 &write_algorithm) != ERROR_OK) {
486 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
487 }
488
489 uint8_t code[sizeof(str7x_flash_write_code)];
490 target_buffer_set_u32_array(target, code, ARRAY_SIZE(str7x_flash_write_code),
491 str7x_flash_write_code);
492 target_write_buffer(target, write_algorithm->address, sizeof(code), code);
493
494 /* memory buffer */
495 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
496 buffer_size /= 2;
497 if (buffer_size <= 256) {
498 /* we already allocated the writing code, but failed to get a
499 * buffer, free the algorithm */
500 target_free_working_area(target, write_algorithm);
501
502 LOG_WARNING("no large enough working area available, can't do block memory writes");
503 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
504 }
505 }
506
507 arm_algo.common_magic = ARM_COMMON_MAGIC;
508 arm_algo.core_mode = ARM_MODE_SVC;
509 arm_algo.core_state = ARM_STATE_ARM;
510
511 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
512 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
513 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
514 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
515 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
516 init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
517
518 while (count > 0) {
519 uint32_t thisrun_count = (count > (buffer_size / 8)) ? (buffer_size / 8) : count;
520
521 target_write_buffer(target, source->address, thisrun_count * 8, buffer);
522
523 buf_set_u32(reg_params[0].value, 0, 32, source->address);
524 buf_set_u32(reg_params[1].value, 0, 32, address);
525 buf_set_u32(reg_params[2].value, 0, 32, str7x_get_flash_adr(bank, FLASH_CR0));
526 buf_set_u32(reg_params[3].value, 0, 32, thisrun_count);
527 buf_set_u32(reg_params[5].value, 0, 32, str7x_info->busy_bits);
528
529 retval = target_run_algorithm(target, 0, NULL, 6, reg_params,
530 write_algorithm->address,
531 write_algorithm->address + (sizeof(str7x_flash_write_code) - 4),
532 10000, &arm_algo);
533 if (retval != ERROR_OK)
534 break;
535
536 if (buf_get_u32(reg_params[4].value, 0, 32) != 0x00) {
537 retval = str7x_result(bank);
538 break;
539 }
540
541 buffer += thisrun_count * 8;
542 address += thisrun_count * 8;
543 count -= thisrun_count;
544 }
545
546 target_free_working_area(target, source);
547 target_free_working_area(target, write_algorithm);
548
549 destroy_reg_param(&reg_params[0]);
550 destroy_reg_param(&reg_params[1]);
551 destroy_reg_param(&reg_params[2]);
552 destroy_reg_param(&reg_params[3]);
553 destroy_reg_param(&reg_params[4]);
554 destroy_reg_param(&reg_params[5]);
555
556 return retval;
557 }
558
559 static int str7x_write(struct flash_bank *bank, const uint8_t *buffer,
560 uint32_t offset, uint32_t count)
561 {
562 struct target *target = bank->target;
563 uint32_t dwords_remaining = (count / 8);
564 uint32_t bytes_remaining = (count & 0x00000007);
565 uint32_t address = bank->base + offset;
566 uint32_t bytes_written = 0;
567 uint32_t cmd;
568 int retval;
569 uint32_t check_address = offset;
570
571 if (bank->target->state != TARGET_HALTED) {
572 LOG_ERROR("Target not halted");
573 return ERROR_TARGET_NOT_HALTED;
574 }
575
576 if (offset & 0x7) {
577 LOG_WARNING("offset 0x%" PRIx32 " breaks required 8-byte alignment", offset);
578 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
579 }
580
581 for (unsigned int i = 0; i < bank->num_sectors; i++) {
582 uint32_t sec_start = bank->sectors[i].offset;
583 uint32_t sec_end = sec_start + bank->sectors[i].size;
584
585 /* check if destination falls within the current sector */
586 if ((check_address >= sec_start) && (check_address < sec_end)) {
587 /* check if destination ends in the current sector */
588 if (offset + count < sec_end)
589 check_address = offset + count;
590 else
591 check_address = sec_end;
592 }
593 }
594
595 if (check_address != offset + count)
596 return ERROR_FLASH_DST_OUT_OF_BANK;
597
598 /* clear FLASH_ER register */
599 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
600
601 /* multiple dwords (8-byte) to be programmed? */
602 if (dwords_remaining > 0) {
603 /* try using a block write */
604 retval = str7x_write_block(bank, buffer, offset, dwords_remaining);
605 if (retval != ERROR_OK) {
606 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
607 /* if block write failed (no sufficient working area),
608 * we use normal (slow) single dword accesses */
609 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
610 } else {
611 return retval;
612 }
613 } else {
614 buffer += dwords_remaining * 8;
615 address += dwords_remaining * 8;
616 dwords_remaining = 0;
617 }
618 }
619
620 while (dwords_remaining > 0) {
621 /* command */
622 cmd = FLASH_DWPG;
623 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
624
625 /* address */
626 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
627
628 /* data word 1 */
629 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0),
630 4, 1, buffer + bytes_written);
631 bytes_written += 4;
632
633 /* data word 2 */
634 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1),
635 4, 1, buffer + bytes_written);
636 bytes_written += 4;
637
638 /* start programming cycle */
639 cmd = FLASH_DWPG | FLASH_WMS;
640 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
641
642 int err;
643 err = str7x_waitbusy(bank);
644 if (err != ERROR_OK)
645 return err;
646
647 err = str7x_result(bank);
648 if (err != ERROR_OK)
649 return err;
650
651 dwords_remaining--;
652 address += 8;
653 }
654
655 if (bytes_remaining) {
656 uint8_t last_dword[8] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
657
658 /* copy the last remaining bytes into the write buffer */
659 memcpy(last_dword, buffer+bytes_written, bytes_remaining);
660
661 /* command */
662 cmd = FLASH_DWPG;
663 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
664
665 /* address */
666 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
667
668 /* data word 1 */
669 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0),
670 4, 1, last_dword);
671
672 /* data word 2 */
673 target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1),
674 4, 1, last_dword + 4);
675
676 /* start programming cycle */
677 cmd = FLASH_DWPG | FLASH_WMS;
678 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
679
680 int err;
681 err = str7x_waitbusy(bank);
682 if (err != ERROR_OK)
683 return err;
684
685 err = str7x_result(bank);
686 if (err != ERROR_OK)
687 return err;
688 }
689
690 return ERROR_OK;
691 }
692
693 static int str7x_probe(struct flash_bank *bank)
694 {
695 return ERROR_OK;
696 }
697
698 #if 0
699 COMMAND_HANDLER(str7x_handle_part_id_command)
700 {
701 return ERROR_OK;
702 }
703 #endif
704
705 static int get_str7x_info(struct flash_bank *bank, struct command_invocation *cmd)
706 {
707 /* Setting the write protection on a sector is a permanent change but it
708 * can be disabled temporarily. FLASH_NVWPAR reflects the permanent
709 * protection state of the sectors, not the temporary.
710 */
711 command_print_sameline(cmd, "STR7x flash protection info is only valid after a power cycle, "
712 "clearing the protection is only temporary and may not be reflected in the current "
713 "info returned.");
714 return ERROR_OK;
715 }
716
717 COMMAND_HANDLER(str7x_handle_disable_jtag_command)
718 {
719 struct target *target = NULL;
720 struct str7x_flash_bank *str7x_info = NULL;
721
722 uint32_t flash_cmd;
723 uint16_t ProtectionLevel = 0;
724 uint16_t ProtectionRegs;
725
726 if (CMD_ARGC < 1)
727 return ERROR_COMMAND_SYNTAX_ERROR;
728
729 struct flash_bank *bank;
730 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
731 if (ERROR_OK != retval)
732 return retval;
733
734 str7x_info = bank->driver_priv;
735
736 target = bank->target;
737
738 if (target->state != TARGET_HALTED) {
739 LOG_ERROR("Target not halted");
740 return ERROR_TARGET_NOT_HALTED;
741 }
742
743 /* first we get protection status */
744 uint32_t reg;
745 target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR0), &reg);
746
747 if (!(reg & str7x_info->disable_bit))
748 ProtectionLevel = 1;
749
750 target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR1), &reg);
751 ProtectionRegs = ~(reg >> 16);
752
753 while (((ProtectionRegs) != 0) && (ProtectionLevel < 16)) {
754 ProtectionRegs >>= 1;
755 ProtectionLevel++;
756 }
757
758 if (ProtectionLevel == 0) {
759 flash_cmd = FLASH_SPR;
760 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
761 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFB8);
762 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), 0xFFFFFFFD);
763 flash_cmd = FLASH_SPR | FLASH_WMS;
764 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
765 } else {
766 flash_cmd = FLASH_SPR;
767 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
768 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFBC);
769 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0),
770 ~(1 << (15 + ProtectionLevel)));
771 flash_cmd = FLASH_SPR | FLASH_WMS;
772 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
773 }
774
775 return ERROR_OK;
776 }
777
778 static const struct command_registration str7x_exec_command_handlers[] = {
779 {
780 .name = "disable_jtag",
781 .usage = "<bank>",
782 .handler = str7x_handle_disable_jtag_command,
783 .mode = COMMAND_EXEC,
784 .help = "disable jtag access",
785 },
786 COMMAND_REGISTRATION_DONE
787 };
788
789 static const struct command_registration str7x_command_handlers[] = {
790 {
791 .name = "str7x",
792 .mode = COMMAND_ANY,
793 .help = "str7x flash command group",
794 .usage = "",
795 .chain = str7x_exec_command_handlers,
796 },
797 COMMAND_REGISTRATION_DONE
798 };
799
800 const struct flash_driver str7x_flash = {
801 .name = "str7x",
802 .commands = str7x_command_handlers,
803 .flash_bank_command = str7x_flash_bank_command,
804 .erase = str7x_erase,
805 .protect = str7x_protect,
806 .write = str7x_write,
807 .read = default_flash_read,
808 .probe = str7x_probe,
809 .auto_probe = str7x_probe,
810 .erase_check = default_flash_blank_check,
811 .protect_check = str7x_protect_check,
812 .info = get_str7x_info,
813 .free_driver_priv = default_flash_free_driver_priv,
814 };
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