1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
31 #include "algorithm.h"
32 #include "binarybuffer.h"
37 int stm32x_register_commands(struct command_context_s
*cmd_ctx
);
38 int stm32x_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
);
39 int stm32x_erase(struct flash_bank_s
*bank
, int first
, int last
);
40 int stm32x_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
);
41 int stm32x_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
);
42 int stm32x_probe(struct flash_bank_s
*bank
);
43 int stm32x_handle_part_id_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
44 int stm32x_protect_check(struct flash_bank_s
*bank
);
45 int stm32x_erase_check(struct flash_bank_s
*bank
);
46 int stm32x_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
);
48 int stm32x_handle_lock_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
49 int stm32x_handle_unlock_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
50 int stm32x_handle_options_read_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
51 int stm32x_handle_options_write_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
52 int stm32x_handle_mass_erase_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
54 flash_driver_t stm32x_flash
=
57 .register_commands
= stm32x_register_commands
,
58 .flash_bank_command
= stm32x_flash_bank_command
,
59 .erase
= stm32x_erase
,
60 .protect
= stm32x_protect
,
61 .write
= stm32x_write
,
62 .probe
= stm32x_probe
,
63 .erase_check
= stm32x_erase_check
,
64 .protect_check
= stm32x_protect_check
,
68 int stm32x_register_commands(struct command_context_s
*cmd_ctx
)
70 command_t
*stm32x_cmd
= register_command(cmd_ctx
, NULL
, "stm32x", NULL
, COMMAND_ANY
, "stm32x flash specific commands");
72 register_command(cmd_ctx
, stm32x_cmd
, "lock", stm32x_handle_lock_command
, COMMAND_EXEC
,
74 register_command(cmd_ctx
, stm32x_cmd
, "unlock", stm32x_handle_unlock_command
, COMMAND_EXEC
,
75 "unlock protected device");
76 register_command(cmd_ctx
, stm32x_cmd
, "mass_erase", stm32x_handle_mass_erase_command
, COMMAND_EXEC
,
78 register_command(cmd_ctx
, stm32x_cmd
, "options_read", stm32x_handle_options_read_command
, COMMAND_EXEC
,
79 "read device option bytes");
80 register_command(cmd_ctx
, stm32x_cmd
, "options_write", stm32x_handle_options_write_command
, COMMAND_EXEC
,
81 "write device option bytes");
85 int stm32x_build_block_list(struct flash_bank_s
*bank
)
102 ERROR("BUG: unknown bank->size encountered");
106 bank
->num_sectors
= num_sectors
;
107 bank
->sectors
= malloc(sizeof(flash_sector_t
) * num_sectors
);
109 for (i
= 0; i
< num_sectors
; i
++)
111 bank
->sectors
[i
].offset
= i
* 1024;
112 bank
->sectors
[i
].size
= 1024;
113 bank
->sectors
[i
].is_erased
= -1;
114 bank
->sectors
[i
].is_protected
= 1;
120 /* flash bank stm32x <base> <size> 0 0 <target#>
122 int stm32x_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
)
124 stm32x_flash_bank_t
*stm32x_info
;
128 WARNING("incomplete flash_bank stm32x configuration");
129 return ERROR_FLASH_BANK_INVALID
;
132 stm32x_info
= malloc(sizeof(stm32x_flash_bank_t
));
133 bank
->driver_priv
= stm32x_info
;
135 if (bank
->base
!= 0x08000000)
137 WARNING("overriding flash base address for STM32x device with 0x08000000");
138 bank
->base
= 0x08000000;
141 stm32x_build_block_list(bank
);
143 stm32x_info
->write_algorithm
= NULL
;
148 u32
stm32x_get_flash_status(flash_bank_t
*bank
)
150 target_t
*target
= bank
->target
;
153 target_read_u32(target
, STM32_FLASH_SR
, &status
);
158 u32
stm32x_wait_status_busy(flash_bank_t
*bank
, int timeout
)
162 /* wait for busy to clear */
163 while (((status
= stm32x_get_flash_status(bank
)) & FLASH_BSY
) && (timeout
-- > 0))
165 DEBUG("status: 0x%x", status
);
172 int stm32x_blank_check(struct flash_bank_s
*bank
, int first
, int last
)
174 target_t
*target
= bank
->target
;
179 if ((first
< 0) || (last
> bank
->num_sectors
))
180 return ERROR_FLASH_SECTOR_INVALID
;
182 if (target
->state
!= TARGET_HALTED
)
184 return ERROR_TARGET_NOT_HALTED
;
187 buffer
= malloc(256);
189 for (i
= first
; i
<= last
; i
++)
191 bank
->sectors
[i
].is_erased
= 1;
193 target
->type
->read_memory(target
, bank
->base
+ bank
->sectors
[i
].offset
, 4, 256/4, buffer
);
195 for (nBytes
= 0; nBytes
< 256; nBytes
++)
197 if (buffer
[nBytes
] != 0xFF)
199 bank
->sectors
[i
].is_erased
= 0;
210 int stm32x_protect_check(struct flash_bank_s
*bank
)
212 target_t
*target
= bank
->target
;
217 if (target
->state
!= TARGET_HALTED
)
219 return ERROR_TARGET_NOT_HALTED
;
222 /* each bit refers to a 4bank protection */
223 target_read_u32(target
, STM32_FLASH_WRPR
, &protection
);
225 for (i
= 0; i
< 32; i
++)
229 if( protection
& (1 << i
))
232 for (s
= 0; s
< 4; s
++)
233 bank
->sectors
[(i
* 4) + s
].is_protected
= set
;
239 int stm32x_erase(struct flash_bank_s
*bank
, int first
, int last
)
241 target_t
*target
= bank
->target
;
246 /* unlock flash registers */
247 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
248 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
250 if (target
->state
!= TARGET_HALTED
)
252 return ERROR_TARGET_NOT_HALTED
;
255 for (i
= first
; i
<= last
; i
++)
257 target_write_u32(target
, STM32_FLASH_CR
, FLASH_PER
);
258 target_write_u32(target
, STM32_FLASH_AR
, bank
->base
+ bank
->sectors
[i
].offset
);
259 target_write_u32(target
, STM32_FLASH_CR
, FLASH_PER
|FLASH_STRT
);
261 status
= stm32x_wait_status_busy(bank
, 10);
263 if( status
& FLASH_WRPRTERR
)
264 return ERROR_FLASH_OPERATION_FAILED
;
265 if( status
& FLASH_PGERR
)
266 return ERROR_FLASH_OPERATION_FAILED
;
267 bank
->sectors
[i
].is_erased
= 1;
270 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
275 int stm32x_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
277 target_t
*target
= bank
->target
;
279 if (target
->state
!= TARGET_HALTED
)
281 return ERROR_TARGET_NOT_HALTED
;
287 int stm32x_write_block(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
)
289 stm32x_flash_bank_t
*stm32x_info
= bank
->driver_priv
;
290 target_t
*target
= bank
->target
;
291 u32 buffer_size
= 8192;
292 working_area_t
*source
;
293 u32 address
= bank
->base
+ offset
;
294 reg_param_t reg_params
[4];
295 armv7m_algorithm_t armv7m_info
;
296 int retval
= ERROR_OK
;
298 u8 stm32x_flash_write_code
[] = {
300 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
301 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
302 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
303 0x23, 0x60, /* str r3, [r4, #0] */
304 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
305 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
307 0x2B, 0x68, /* ldr r3, [r5, #0] */
308 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
309 0xFB, 0xD0, /* beq busy */
310 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
311 0x01, 0xD1, /* bne exit */
312 0x01, 0x3A, /* subs r2, r2, #1 */
313 0xED, 0xD1, /* bne write */
315 0xFE, 0xE7, /* b exit */
316 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
317 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
320 /* flash write code */
321 if (target_alloc_working_area(target
, sizeof(stm32x_flash_write_code
), &stm32x_info
->write_algorithm
) != ERROR_OK
)
323 WARNING("no working area available, can't do block memory writes");
324 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
327 target_write_buffer(target
, stm32x_info
->write_algorithm
->address
, sizeof(stm32x_flash_write_code
), stm32x_flash_write_code
);
330 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
)
333 if (buffer_size
<= 256)
335 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
336 if (stm32x_info
->write_algorithm
)
337 target_free_working_area(target
, stm32x_info
->write_algorithm
);
339 WARNING("no large enough working area available, can't do block memory writes");
340 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
344 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
345 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
346 armv7m_info
.core_state
= ARMV7M_STATE_THUMB
;
348 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
349 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
350 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
351 init_reg_param(®_params
[3], "r3", 32, PARAM_IN
);
355 u32 thisrun_count
= (count
> (buffer_size
/ 2)) ? (buffer_size
/ 2) : count
;
357 target_write_buffer(target
, source
->address
, thisrun_count
* 2, buffer
);
359 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
360 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
361 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
);
363 if ((retval
= target
->type
->run_algorithm(target
, 0, NULL
, 4, reg_params
, stm32x_info
->write_algorithm
->address
, \
364 stm32x_info
->write_algorithm
->address
+ (sizeof(stm32x_flash_write_code
) - 10), 10000, &armv7m_info
)) != ERROR_OK
)
366 ERROR("error executing str7x flash write algorithm");
370 if (buf_get_u32(reg_params
[3].value
, 0, 32) & 0x14)
372 retval
= ERROR_FLASH_OPERATION_FAILED
;
376 buffer
+= thisrun_count
* 2;
377 address
+= thisrun_count
* 2;
378 count
-= thisrun_count
;
381 target_free_working_area(target
, source
);
382 target_free_working_area(target
, stm32x_info
->write_algorithm
);
384 destroy_reg_param(®_params
[0]);
385 destroy_reg_param(®_params
[1]);
386 destroy_reg_param(®_params
[2]);
387 destroy_reg_param(®_params
[3]);
392 int stm32x_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
)
394 target_t
*target
= bank
->target
;
395 u32 words_remaining
= (count
/ 2);
396 u32 bytes_remaining
= (count
& 0x00000001);
397 u32 address
= bank
->base
+ offset
;
398 u32 bytes_written
= 0;
402 if (target
->state
!= TARGET_HALTED
)
404 return ERROR_TARGET_NOT_HALTED
;
409 WARNING("offset 0x%x breaks required 2-byte alignment", offset
);
410 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
413 /* unlock flash registers */
414 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
415 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
417 /* multiple half words (2-byte) to be programmed? */
418 if (words_remaining
> 0)
420 /* try using a block write */
421 if ((retval
= stm32x_write_block(bank
, buffer
, offset
, words_remaining
)) != ERROR_OK
)
423 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
425 /* if block write failed (no sufficient working area),
426 * we use normal (slow) single dword accesses */
427 WARNING("couldn't use block writes, falling back to single memory accesses");
429 else if (retval
== ERROR_FLASH_OPERATION_FAILED
)
431 ERROR("flash writing failed with error code: 0x%x", retval
);
432 return ERROR_FLASH_OPERATION_FAILED
;
437 buffer
+= words_remaining
* 2;
438 address
+= words_remaining
* 2;
443 while (words_remaining
> 0)
445 target_write_u32(target
, STM32_FLASH_CR
, FLASH_PG
);
446 target_write_u16(target
, address
, *(u16
*)(buffer
+ bytes_written
));
448 status
= stm32x_wait_status_busy(bank
, 5);
450 if( status
& FLASH_WRPRTERR
)
451 return ERROR_FLASH_OPERATION_FAILED
;
452 if( status
& FLASH_PGERR
)
453 return ERROR_FLASH_OPERATION_FAILED
;
462 u8 last_halfword
[2] = {0xff, 0xff};
465 while(bytes_remaining
> 0)
467 last_halfword
[i
++] = *(buffer
+ bytes_written
);
472 target_write_u32(target
, STM32_FLASH_CR
, FLASH_PG
);
473 target_write_u16(target
, address
, *(u16
*)last_halfword
);
475 status
= stm32x_wait_status_busy(bank
, 5);
477 if( status
& FLASH_WRPRTERR
)
478 return ERROR_FLASH_OPERATION_FAILED
;
479 if( status
& FLASH_PGERR
)
480 return ERROR_FLASH_OPERATION_FAILED
;
483 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
488 int stm32x_probe(struct flash_bank_s
*bank
)
493 int stm32x_handle_part_id_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
498 int stm32x_erase_check(struct flash_bank_s
*bank
)
500 return stm32x_blank_check(bank
, 0, bank
->num_sectors
- 1);
503 int stm32x_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
505 snprintf(buf
, buf_size
, "stm32x flash driver info" );
509 int stm32x_handle_lock_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
513 target_t
*target
= NULL
;
514 stm32x_flash_bank_t
*stm32x_info
= NULL
;
518 command_print(cmd_ctx
, "stm32x lock <bank>");
522 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
525 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
529 stm32x_info
= bank
->driver_priv
;
531 target
= bank
->target
;
533 if (target
->state
!= TARGET_HALTED
)
535 return ERROR_TARGET_NOT_HALTED
;
538 /* unlock flash registers */
539 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
540 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
542 /* unlock option flash registers */
543 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY1
);
544 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY2
);
546 /* erase option bytes */
547 target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTER
|FLASH_OPTWRE
);
548 target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTER
|FLASH_STRT
|FLASH_OPTWRE
);
550 status
= stm32x_wait_status_busy(bank
, 10);
552 if( status
& FLASH_WRPRTERR
)
553 return ERROR_FLASH_OPERATION_FAILED
;
554 if( status
& FLASH_PGERR
)
555 return ERROR_FLASH_OPERATION_FAILED
;
557 /* program option bytes */
558 target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTPG
|FLASH_OPTWRE
);
560 /* set readout protection */
561 target_write_u16(target
, STM32_OB_ADR
, 0);
563 status
= stm32x_wait_status_busy(bank
, 10);
565 if( status
& FLASH_WRPRTERR
)
566 return ERROR_FLASH_OPERATION_FAILED
;
567 if( status
& FLASH_PGERR
)
568 return ERROR_FLASH_OPERATION_FAILED
;
570 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
571 command_print(cmd_ctx
, "stm32x locked");
576 int stm32x_handle_unlock_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
580 target_t
*target
= NULL
;
581 stm32x_flash_bank_t
*stm32x_info
= NULL
;
585 command_print(cmd_ctx
, "stm32x unlock <bank>");
589 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
592 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
596 stm32x_info
= bank
->driver_priv
;
598 target
= bank
->target
;
600 if (target
->state
!= TARGET_HALTED
)
602 return ERROR_TARGET_NOT_HALTED
;
605 /* unlock flash registers */
606 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
607 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
609 /* unlock option flash registers */
610 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY1
);
611 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY2
);
613 /* erase option bytes */
614 target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTER
|FLASH_OPTWRE
);
615 target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTER
|FLASH_STRT
|FLASH_OPTWRE
);
617 status
= stm32x_wait_status_busy(bank
, 10);
619 if( status
& FLASH_WRPRTERR
)
620 return ERROR_FLASH_OPERATION_FAILED
;
621 if( status
& FLASH_PGERR
)
622 return ERROR_FLASH_OPERATION_FAILED
;
624 /* program option bytes */
625 target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTPG
|FLASH_OPTWRE
);
627 /* clear readout protection and complementary option bytes */
628 target_write_u16(target
, STM32_OB_ADR
, 0x5AA5);
630 status
= stm32x_wait_status_busy(bank
, 10);
632 if( status
& FLASH_WRPRTERR
)
633 return ERROR_FLASH_OPERATION_FAILED
;
634 if( status
& FLASH_PGERR
)
635 return ERROR_FLASH_OPERATION_FAILED
;
637 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
638 command_print(cmd_ctx
, "stm32x unlocked");
643 int stm32x_handle_options_read_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
647 target_t
*target
= NULL
;
648 stm32x_flash_bank_t
*stm32x_info
= NULL
;
652 command_print(cmd_ctx
, "stm32x options_read <bank>");
656 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
659 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
663 stm32x_info
= bank
->driver_priv
;
665 target
= bank
->target
;
667 if (target
->state
!= TARGET_HALTED
)
669 return ERROR_TARGET_NOT_HALTED
;
672 //target_read_u32(target, STM32_OB_ADR, &optionbyte);
673 //command_print(cmd_ctx, "Option Byte 0: 0x%x", optionbyte);
674 //target_read_u32(target, STM32_OB_ADR+4, &optionbyte);
675 //command_print(cmd_ctx, "Option Byte 1: 0x%x", optionbyte);
676 //target_read_u32(target, STM32_OB_ADR+8, &optionbyte);
677 //command_print(cmd_ctx, "Option Byte 2: 0x%x", optionbyte);
678 //target_read_u32(target, STM32_OB_ADR+12, &optionbyte);
679 //command_print(cmd_ctx, "Option Byte 3: 0x%x", optionbyte);
681 target_read_u32(target
, STM32_FLASH_OBR
, &optionbyte
);
682 command_print(cmd_ctx
, "Option Byte: 0x%x", optionbyte
);
684 if (buf_get_u32((u8
*)&optionbyte
, OPT_ERROR
, 1))
685 command_print(cmd_ctx
, "Option Byte Complement Error");
687 if (buf_get_u32((u8
*)&optionbyte
, OPT_READOUT
, 1))
688 command_print(cmd_ctx
, "Readout Protection On");
690 command_print(cmd_ctx
, "Readout Protection Off");
692 if (buf_get_u32((u8
*)&optionbyte
, OPT_RDWDGSW
, 1))
693 command_print(cmd_ctx
, "Software Watchdog");
695 command_print(cmd_ctx
, "Hardware Watchdog");
697 if (buf_get_u32((u8
*)&optionbyte
, OPT_RDRSTSTOP
, 1))
698 command_print(cmd_ctx
, "Stop: No reset generated");
700 command_print(cmd_ctx
, "Stop: Reset generated");
702 if (buf_get_u32((u8
*)&optionbyte
, OPT_RDRSTSTDBY
, 1))
703 command_print(cmd_ctx
, "Standby: No reset generated");
705 command_print(cmd_ctx
, "Standby: Reset generated");
710 int stm32x_handle_options_write_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
713 target_t
*target
= NULL
;
714 stm32x_flash_bank_t
*stm32x_info
= NULL
;
715 u16 optionbyte
= 0xF8;
720 command_print(cmd_ctx
, "stm32x options_write <bank> <SWWDG|HWWDG> <RSTSTNDBY|NORSTSTNDBY> <RSTSTOP|NORSTSTOP>");
724 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
727 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
731 stm32x_info
= bank
->driver_priv
;
733 target
= bank
->target
;
735 if (target
->state
!= TARGET_HALTED
)
737 return ERROR_TARGET_NOT_HALTED
;
740 if (strcmp(args
[1], "SWWDG") == 0)
742 optionbyte
|= (1<<0);
746 optionbyte
&= ~(1<<0);
749 if (strcmp(args
[2], "NORSTSTNDBY") == 0)
751 optionbyte
|= (1<<1);
755 optionbyte
&= ~(1<<1);
758 if (strcmp(args
[3], "NORSTSTOP") == 0)
760 optionbyte
|= (1<<2);
764 optionbyte
&= ~(1<<2);
767 /* unlock flash registers */
768 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
769 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
771 /* unlock option flash registers */
772 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY1
);
773 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY2
);
775 /* program option bytes */
776 target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTPG
|FLASH_OPTWRE
);
778 /* write option byte */
779 target_write_u16(target
, STM32_OB_ADR
+ 2, optionbyte
);
781 status
= stm32x_wait_status_busy(bank
, 10);
783 if( status
& FLASH_WRPRTERR
)
784 return ERROR_FLASH_OPERATION_FAILED
;
785 if( status
& FLASH_PGERR
)
786 return ERROR_FLASH_OPERATION_FAILED
;
788 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
793 int stm32x_handle_mass_erase_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
797 target_t
*target
= NULL
;
798 stm32x_flash_bank_t
*stm32x_info
= NULL
;
802 command_print(cmd_ctx
, "stm32x mass_erase <bank>");
806 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
809 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
813 stm32x_info
= bank
->driver_priv
;
815 target
= bank
->target
;
817 if (target
->state
!= TARGET_HALTED
)
819 return ERROR_TARGET_NOT_HALTED
;
822 /* unlock option flash registers */
823 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
824 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
826 /* mass erase flash memory */
827 target_write_u32(target
, STM32_FLASH_CR
, FLASH_MER
);
828 target_write_u32(target
, STM32_FLASH_CR
, FLASH_MER
|FLASH_STRT
);
830 status
= stm32x_wait_status_busy(bank
, 10);
832 if( status
& FLASH_WRPRTERR
)
833 return ERROR_FLASH_OPERATION_FAILED
;
834 if( status
& FLASH_PGERR
)
835 return ERROR_FLASH_OPERATION_FAILED
;
837 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
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