1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
31 #include "algorithm.h"
32 #include "binarybuffer.h"
37 int stm32x_register_commands(struct command_context_s
*cmd_ctx
);
38 int stm32x_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
);
39 int stm32x_erase(struct flash_bank_s
*bank
, int first
, int last
);
40 int stm32x_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
);
41 int stm32x_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
);
42 int stm32x_probe(struct flash_bank_s
*bank
);
43 int stm32x_handle_part_id_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
44 int stm32x_protect_check(struct flash_bank_s
*bank
);
45 int stm32x_erase_check(struct flash_bank_s
*bank
);
46 int stm32x_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
);
48 int stm32x_handle_lock_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
49 int stm32x_handle_unlock_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
50 int stm32x_handle_options_read_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
51 int stm32x_handle_options_write_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
52 int stm32x_handle_mass_erase_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
54 flash_driver_t stm32x_flash
=
57 .register_commands
= stm32x_register_commands
,
58 .flash_bank_command
= stm32x_flash_bank_command
,
59 .erase
= stm32x_erase
,
60 .protect
= stm32x_protect
,
61 .write
= stm32x_write
,
62 .probe
= stm32x_probe
,
63 .erase_check
= stm32x_erase_check
,
64 .protect_check
= stm32x_protect_check
,
68 int stm32x_register_commands(struct command_context_s
*cmd_ctx
)
70 command_t
*stm32x_cmd
= register_command(cmd_ctx
, NULL
, "stm32x", NULL
, COMMAND_ANY
, "stm32x flash specific commands");
72 register_command(cmd_ctx
, stm32x_cmd
, "lock", stm32x_handle_lock_command
, COMMAND_EXEC
,
74 register_command(cmd_ctx
, stm32x_cmd
, "unlock", stm32x_handle_unlock_command
, COMMAND_EXEC
,
75 "unlock protected device");
76 register_command(cmd_ctx
, stm32x_cmd
, "mass_erase", stm32x_handle_mass_erase_command
, COMMAND_EXEC
,
78 register_command(cmd_ctx
, stm32x_cmd
, "options_read", stm32x_handle_options_read_command
, COMMAND_EXEC
,
79 "read device option bytes");
80 register_command(cmd_ctx
, stm32x_cmd
, "options_write", stm32x_handle_options_write_command
, COMMAND_EXEC
,
81 "write device option bytes");
85 int stm32x_build_block_list(struct flash_bank_s
*bank
)
102 ERROR("BUG: unknown bank->size encountered");
106 bank
->num_sectors
= num_sectors
;
107 bank
->sectors
= malloc(sizeof(flash_sector_t
) * num_sectors
);
109 for (i
= 0; i
< num_sectors
; i
++)
111 bank
->sectors
[i
].offset
= i
* 1024;
112 bank
->sectors
[i
].size
= 1024;
113 bank
->sectors
[i
].is_erased
= -1;
114 bank
->sectors
[i
].is_protected
= 1;
120 /* flash bank stm32x <base> <size> 0 0 <target#>
122 int stm32x_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
)
124 stm32x_flash_bank_t
*stm32x_info
;
128 WARNING("incomplete flash_bank stm32x configuration");
129 return ERROR_FLASH_BANK_INVALID
;
132 stm32x_info
= malloc(sizeof(stm32x_flash_bank_t
));
133 bank
->driver_priv
= stm32x_info
;
135 if (bank
->base
!= 0x08000000)
137 WARNING("overriding flash base address for STM32x device with 0x08000000");
138 bank
->base
= 0x08000000;
141 stm32x_info
->target
= get_target_by_num(strtoul(args
[5], NULL
, 0));
142 if (!stm32x_info
->target
)
144 ERROR("no target '%s' configured", args
[5]);
148 stm32x_build_block_list(bank
);
150 stm32x_info
->write_algorithm
= NULL
;
155 u32
stm32x_get_flash_status(flash_bank_t
*bank
)
157 stm32x_flash_bank_t
*stm32x_info
= bank
->driver_priv
;
158 target_t
*target
= stm32x_info
->target
;
161 target_read_u32(target
, STM32_FLASH_SR
, &status
);
166 u32
stm32x_wait_status_busy(flash_bank_t
*bank
, int timeout
)
170 /* wait for busy to clear */
171 while (((status
= stm32x_get_flash_status(bank
)) & FLASH_BSY
) && (timeout
-- > 0))
173 DEBUG("status: 0x%x", status
);
180 int stm32x_blank_check(struct flash_bank_s
*bank
, int first
, int last
)
182 stm32x_flash_bank_t
*stm32x_info
= bank
->driver_priv
;
183 target_t
*target
= stm32x_info
->target
;
188 if ((first
< 0) || (last
> bank
->num_sectors
))
189 return ERROR_FLASH_SECTOR_INVALID
;
191 if (target
->state
!= TARGET_HALTED
)
193 return ERROR_TARGET_NOT_HALTED
;
196 buffer
= malloc(256);
198 for (i
= first
; i
<= last
; i
++)
200 bank
->sectors
[i
].is_erased
= 1;
202 target
->type
->read_memory(target
, bank
->base
+ bank
->sectors
[i
].offset
, 4, 256/4, buffer
);
204 for (nBytes
= 0; nBytes
< 256; nBytes
++)
206 if (buffer
[nBytes
] != 0xFF)
208 bank
->sectors
[i
].is_erased
= 0;
219 int stm32x_protect_check(struct flash_bank_s
*bank
)
221 stm32x_flash_bank_t
*stm32x_info
= bank
->driver_priv
;
222 target_t
*target
= stm32x_info
->target
;
227 if (target
->state
!= TARGET_HALTED
)
229 return ERROR_TARGET_NOT_HALTED
;
232 /* each bit refers to a 4bank protection */
233 target_read_u32(target
, STM32_FLASH_WRPR
, &protection
);
235 for (i
= 0; i
< 32; i
++)
239 if( protection
& (1 << i
))
242 for (s
= 0; s
< 4; s
++)
243 bank
->sectors
[(i
* 4) + s
].is_protected
= set
;
249 int stm32x_erase(struct flash_bank_s
*bank
, int first
, int last
)
251 stm32x_flash_bank_t
*stm32x_info
= bank
->driver_priv
;
252 target_t
*target
= stm32x_info
->target
;
257 /* unlock flash registers */
258 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
259 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
261 if (target
->state
!= TARGET_HALTED
)
263 return ERROR_TARGET_NOT_HALTED
;
266 for (i
= first
; i
<= last
; i
++)
268 target_write_u32(target
, STM32_FLASH_CR
, FLASH_PER
);
269 target_write_u32(target
, STM32_FLASH_AR
, bank
->base
+ bank
->sectors
[i
].offset
);
270 target_write_u32(target
, STM32_FLASH_CR
, FLASH_PER
|FLASH_STRT
);
272 status
= stm32x_wait_status_busy(bank
, 10);
274 if( status
& FLASH_WRPRTERR
)
275 return ERROR_FLASH_OPERATION_FAILED
;
276 if( status
& FLASH_PGERR
)
277 return ERROR_FLASH_OPERATION_FAILED
;
278 bank
->sectors
[i
].is_erased
= 1;
281 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
286 int stm32x_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
288 stm32x_flash_bank_t
*stm32x_info
= bank
->driver_priv
;
289 target_t
*target
= stm32x_info
->target
;
291 if (target
->state
!= TARGET_HALTED
)
293 return ERROR_TARGET_NOT_HALTED
;
299 int stm32x_write_block(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
)
301 stm32x_flash_bank_t
*stm32x_info
= bank
->driver_priv
;
302 target_t
*target
= stm32x_info
->target
;
303 u32 buffer_size
= 8192;
304 working_area_t
*source
;
305 u32 address
= bank
->base
+ offset
;
306 reg_param_t reg_params
[6];
307 armv7m_algorithm_t armv7m_info
;
308 int retval
= ERROR_OK
;
310 u8 stm32x_flash_write_code
[] = {
312 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
313 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
314 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
315 0x23, 0x60, /* str r3, [r4, #0] */
316 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
317 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
319 0x2B, 0x68, /* ldr r3, [r5, #0] */
320 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
321 0xFB, 0xD0, /* beq busy */
322 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
323 0x01, 0xD1, /* bne exit */
324 0x01, 0x3A, /* subs r2, r2, #1 */
325 0xED, 0xD1, /* bne write */
327 0xFE, 0xE7, /* b exit */
328 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
329 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
332 /* flash write code */
333 if (!stm32x_info
->write_algorithm
)
335 if (target_alloc_working_area(target
, sizeof(stm32x_flash_write_code
), &stm32x_info
->write_algorithm
) != ERROR_OK
)
337 WARNING("no working area available, can't do block memory writes");
338 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
341 target_write_buffer(target
, stm32x_info
->write_algorithm
->address
, sizeof(stm32x_flash_write_code
), stm32x_flash_write_code
);
345 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
)
348 if (buffer_size
<= 256)
350 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
351 if (stm32x_info
->write_algorithm
)
352 target_free_working_area(target
, stm32x_info
->write_algorithm
);
354 WARNING("no large enough working area available, can't do block memory writes");
355 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
359 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
360 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
361 armv7m_info
.core_state
= ARMV7M_STATE_THUMB
;
363 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
364 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
365 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
366 init_reg_param(®_params
[3], "r3", 32, PARAM_IN
);
367 init_reg_param(®_params
[4], "r4", 32, PARAM_IN
);
368 init_reg_param(®_params
[5], "r5", 32, PARAM_IN
);
372 u32 thisrun_count
= (count
> (buffer_size
/ 2)) ? (buffer_size
/ 2) : count
;
374 target_write_buffer(target
, source
->address
, thisrun_count
* 2, buffer
);
376 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
377 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
378 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
);
380 if ((retval
= target
->type
->run_algorithm(target
, 0, NULL
, 6, reg_params
, stm32x_info
->write_algorithm
->address
, \
381 stm32x_info
->write_algorithm
->address
+ (sizeof(stm32x_flash_write_code
) - 10), 10000, &armv7m_info
)) != ERROR_OK
)
383 ERROR("error executing str7x flash write algorithm");
387 if (buf_get_u32(reg_params
[3].value
, 0, 32) & 0x14)
389 retval
= ERROR_FLASH_OPERATION_FAILED
;
393 buffer
+= thisrun_count
* 2;
394 address
+= thisrun_count
* 2;
395 count
-= thisrun_count
;
398 target_free_working_area(target
, source
);
400 destroy_reg_param(®_params
[0]);
401 destroy_reg_param(®_params
[1]);
402 destroy_reg_param(®_params
[2]);
403 destroy_reg_param(®_params
[3]);
404 destroy_reg_param(®_params
[4]);
405 destroy_reg_param(®_params
[5]);
410 int stm32x_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
)
412 stm32x_flash_bank_t
*stm32x_info
= bank
->driver_priv
;
413 target_t
*target
= stm32x_info
->target
;
414 u32 words_remaining
= (count
/ 2);
415 u32 bytes_remaining
= (count
& 0x00000001);
416 u32 address
= bank
->base
+ offset
;
417 u32 bytes_written
= 0;
421 if (target
->state
!= TARGET_HALTED
)
423 return ERROR_TARGET_NOT_HALTED
;
428 WARNING("offset 0x%x breaks required 2-byte alignment", offset
);
429 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
432 /* unlock flash registers */
433 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
434 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
436 /* multiple half words (2-byte) to be programmed? */
437 if (words_remaining
> 0)
439 /* try using a block write */
440 if ((retval
= stm32x_write_block(bank
, buffer
, offset
, words_remaining
)) != ERROR_OK
)
442 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
444 /* if block write failed (no sufficient working area),
445 * we use normal (slow) single dword accesses */
446 WARNING("couldn't use block writes, falling back to single memory accesses");
448 else if (retval
== ERROR_FLASH_OPERATION_FAILED
)
450 ERROR("flash writing failed with error code: 0x%x", retval
);
451 return ERROR_FLASH_OPERATION_FAILED
;
456 buffer
+= words_remaining
* 2;
457 address
+= words_remaining
* 2;
462 while (words_remaining
> 0)
464 target_write_u32(target
, STM32_FLASH_CR
, FLASH_PG
);
465 target_write_u16(target
, address
, *(u16
*)(buffer
+ bytes_written
));
467 status
= stm32x_wait_status_busy(bank
, 5);
469 if( status
& FLASH_WRPRTERR
)
470 return ERROR_FLASH_OPERATION_FAILED
;
471 if( status
& FLASH_PGERR
)
472 return ERROR_FLASH_OPERATION_FAILED
;
481 u8 last_halfword
[2] = {0xff, 0xff};
484 while(bytes_remaining
> 0)
486 last_halfword
[i
++] = *(buffer
+ bytes_written
);
491 target_write_u32(target
, STM32_FLASH_CR
, FLASH_PG
);
492 target_write_u16(target
, address
, *(u16
*)last_halfword
);
494 status
= stm32x_wait_status_busy(bank
, 5);
496 if( status
& FLASH_WRPRTERR
)
497 return ERROR_FLASH_OPERATION_FAILED
;
498 if( status
& FLASH_PGERR
)
499 return ERROR_FLASH_OPERATION_FAILED
;
502 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
507 int stm32x_probe(struct flash_bank_s
*bank
)
512 int stm32x_handle_part_id_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
517 int stm32x_erase_check(struct flash_bank_s
*bank
)
519 return stm32x_blank_check(bank
, 0, bank
->num_sectors
- 1);
522 int stm32x_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
524 snprintf(buf
, buf_size
, "stm32x flash driver info" );
528 int stm32x_handle_lock_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
532 target_t
*target
= NULL
;
533 stm32x_flash_bank_t
*stm32x_info
= NULL
;
537 command_print(cmd_ctx
, "stm32x lock <bank>");
541 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
544 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
548 stm32x_info
= bank
->driver_priv
;
550 target
= stm32x_info
->target
;
552 if (target
->state
!= TARGET_HALTED
)
554 return ERROR_TARGET_NOT_HALTED
;
557 /* unlock flash registers */
558 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
559 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
561 /* unlock option flash registers */
562 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY1
);
563 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY2
);
565 /* erase option bytes */
566 target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTER
|FLASH_OPTWRE
);
567 target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTER
|FLASH_STRT
|FLASH_OPTWRE
);
569 status
= stm32x_wait_status_busy(bank
, 10);
571 if( status
& FLASH_WRPRTERR
)
572 return ERROR_FLASH_OPERATION_FAILED
;
573 if( status
& FLASH_PGERR
)
574 return ERROR_FLASH_OPERATION_FAILED
;
576 /* program option bytes */
577 target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTPG
|FLASH_OPTWRE
);
579 /* set readout protection */
580 target_write_u16(target
, STM32_OB_ADR
, 0);
582 status
= stm32x_wait_status_busy(bank
, 10);
584 if( status
& FLASH_WRPRTERR
)
585 return ERROR_FLASH_OPERATION_FAILED
;
586 if( status
& FLASH_PGERR
)
587 return ERROR_FLASH_OPERATION_FAILED
;
589 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
590 command_print(cmd_ctx
, "stm32x locked");
595 int stm32x_handle_unlock_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
599 target_t
*target
= NULL
;
600 stm32x_flash_bank_t
*stm32x_info
= NULL
;
604 command_print(cmd_ctx
, "stm32x unlock <bank>");
608 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
611 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
615 stm32x_info
= bank
->driver_priv
;
617 target
= stm32x_info
->target
;
619 if (target
->state
!= TARGET_HALTED
)
621 return ERROR_TARGET_NOT_HALTED
;
624 /* unlock flash registers */
625 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
626 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
628 /* unlock option flash registers */
629 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY1
);
630 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY2
);
632 /* erase option bytes */
633 target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTER
|FLASH_OPTWRE
);
634 target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTER
|FLASH_STRT
|FLASH_OPTWRE
);
636 status
= stm32x_wait_status_busy(bank
, 10);
638 if( status
& FLASH_WRPRTERR
)
639 return ERROR_FLASH_OPERATION_FAILED
;
640 if( status
& FLASH_PGERR
)
641 return ERROR_FLASH_OPERATION_FAILED
;
643 /* program option bytes */
644 target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTPG
|FLASH_OPTWRE
);
646 /* clear readout protection and complementary option bytes */
647 target_write_u16(target
, STM32_OB_ADR
, 0x5AA5);
649 status
= stm32x_wait_status_busy(bank
, 10);
651 if( status
& FLASH_WRPRTERR
)
652 return ERROR_FLASH_OPERATION_FAILED
;
653 if( status
& FLASH_PGERR
)
654 return ERROR_FLASH_OPERATION_FAILED
;
656 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
657 command_print(cmd_ctx
, "stm32x unlocked");
662 int stm32x_handle_options_read_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
666 target_t
*target
= NULL
;
667 stm32x_flash_bank_t
*stm32x_info
= NULL
;
671 command_print(cmd_ctx
, "stm32x options_read <bank>");
675 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
678 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
682 stm32x_info
= bank
->driver_priv
;
684 target
= stm32x_info
->target
;
686 if (target
->state
!= TARGET_HALTED
)
688 return ERROR_TARGET_NOT_HALTED
;
691 //target_read_u32(target, STM32_OB_ADR, &optionbyte);
692 //command_print(cmd_ctx, "Option Byte 0: 0x%x", optionbyte);
693 //target_read_u32(target, STM32_OB_ADR+4, &optionbyte);
694 //command_print(cmd_ctx, "Option Byte 1: 0x%x", optionbyte);
695 //target_read_u32(target, STM32_OB_ADR+8, &optionbyte);
696 //command_print(cmd_ctx, "Option Byte 2: 0x%x", optionbyte);
697 //target_read_u32(target, STM32_OB_ADR+12, &optionbyte);
698 //command_print(cmd_ctx, "Option Byte 3: 0x%x", optionbyte);
700 target_read_u32(target
, STM32_FLASH_OBR
, &optionbyte
);
701 command_print(cmd_ctx
, "Option Byte: 0x%x", optionbyte
);
703 if (buf_get_u32((u8
*)&optionbyte
, OPT_ERROR
, 1))
704 command_print(cmd_ctx
, "Option Byte Complement Error");
706 if (buf_get_u32((u8
*)&optionbyte
, OPT_READOUT
, 1))
707 command_print(cmd_ctx
, "Readout Protection On");
709 command_print(cmd_ctx
, "Readout Protection Off");
711 if (buf_get_u32((u8
*)&optionbyte
, OPT_RDWDGSW
, 1))
712 command_print(cmd_ctx
, "Software Watchdog");
714 command_print(cmd_ctx
, "Hardware Watchdog");
716 if (buf_get_u32((u8
*)&optionbyte
, OPT_RDRSTSTOP
, 1))
717 command_print(cmd_ctx
, "Stop: No reset generated");
719 command_print(cmd_ctx
, "Stop: Reset generated");
721 if (buf_get_u32((u8
*)&optionbyte
, OPT_RDRSTSTDBY
, 1))
722 command_print(cmd_ctx
, "Standby: No reset generated");
724 command_print(cmd_ctx
, "Standby: Reset generated");
729 int stm32x_handle_options_write_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
732 target_t
*target
= NULL
;
733 stm32x_flash_bank_t
*stm32x_info
= NULL
;
734 u16 optionbyte
= 0xF8;
739 command_print(cmd_ctx
, "stm32x options_write <bank> <SWWDG|HWWDG> <RSTSTNDBY|NORSTSTNDBY> <RSTSTOP|NORSTSTOP>");
743 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
746 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
750 stm32x_info
= bank
->driver_priv
;
752 target
= stm32x_info
->target
;
754 if (target
->state
!= TARGET_HALTED
)
756 return ERROR_TARGET_NOT_HALTED
;
759 if (strcmp(args
[1], "SWWDG") == 0)
761 optionbyte
|= (1<<0);
765 optionbyte
&= ~(1<<0);
768 if (strcmp(args
[2], "NORSTSTNDBY") == 0)
770 optionbyte
|= (1<<1);
774 optionbyte
&= ~(1<<1);
777 if (strcmp(args
[3], "NORSTSTOP") == 0)
779 optionbyte
|= (1<<2);
783 optionbyte
&= ~(1<<2);
786 /* unlock flash registers */
787 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
788 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
790 /* unlock option flash registers */
791 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY1
);
792 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY2
);
794 /* program option bytes */
795 target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTPG
|FLASH_OPTWRE
);
797 /* write option byte */
798 target_write_u16(target
, STM32_OB_ADR
+ 2, optionbyte
);
800 status
= stm32x_wait_status_busy(bank
, 10);
802 if( status
& FLASH_WRPRTERR
)
803 return ERROR_FLASH_OPERATION_FAILED
;
804 if( status
& FLASH_PGERR
)
805 return ERROR_FLASH_OPERATION_FAILED
;
807 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
812 int stm32x_handle_mass_erase_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
816 target_t
*target
= NULL
;
817 stm32x_flash_bank_t
*stm32x_info
= NULL
;
821 command_print(cmd_ctx
, "stm32x mass_erase <bank>");
825 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
828 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
832 stm32x_info
= bank
->driver_priv
;
834 target
= stm32x_info
->target
;
836 if (target
->state
!= TARGET_HALTED
)
838 return ERROR_TARGET_NOT_HALTED
;
841 /* unlock option flash registers */
842 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
843 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
845 /* mass erase flash memory */
846 target_write_u32(target
, STM32_FLASH_CR
, FLASH_MER
);
847 target_write_u32(target
, STM32_FLASH_CR
, FLASH_MER
|FLASH_STRT
);
849 status
= stm32x_wait_status_busy(bank
, 10);
851 if( status
& FLASH_WRPRTERR
)
852 return ERROR_FLASH_OPERATION_FAILED
;
853 if( status
& FLASH_PGERR
)
854 return ERROR_FLASH_OPERATION_FAILED
;
856 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
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