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flash_bank_t -> struct flash_bank
[openocd.git] / src / flash / stm32x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "stm32x.h"
28 #include "armv7m.h"
29 #include "binarybuffer.h"
30
31
32 static int stm32x_mass_erase(struct flash_bank *bank);
33
34 /* flash bank stm32x <base> <size> 0 0 <target#>
35 */
36 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
37 {
38 struct stm32x_flash_bank *stm32x_info;
39
40 if (argc < 6)
41 {
42 LOG_WARNING("incomplete flash_bank stm32x configuration");
43 return ERROR_FLASH_BANK_INVALID;
44 }
45
46 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
47 bank->driver_priv = stm32x_info;
48
49 stm32x_info->write_algorithm = NULL;
50 stm32x_info->probed = 0;
51
52 return ERROR_OK;
53 }
54
55 static uint32_t stm32x_get_flash_status(struct flash_bank *bank)
56 {
57 struct target *target = bank->target;
58 uint32_t status;
59
60 target_read_u32(target, STM32_FLASH_SR, &status);
61
62 return status;
63 }
64
65 static uint32_t stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
66 {
67 struct target *target = bank->target;
68 uint32_t status;
69
70 /* wait for busy to clear */
71 while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))
72 {
73 LOG_DEBUG("status: 0x%" PRIx32 "", status);
74 alive_sleep(1);
75 }
76 /* Clear but report errors */
77 if (status & (FLASH_WRPRTERR | FLASH_PGERR))
78 {
79 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR | FLASH_PGERR);
80 }
81 return status;
82 }
83
84 static int stm32x_read_options(struct flash_bank *bank)
85 {
86 uint32_t optiondata;
87 struct stm32x_flash_bank *stm32x_info = NULL;
88 struct target *target = bank->target;
89
90 stm32x_info = bank->driver_priv;
91
92 /* read current option bytes */
93 target_read_u32(target, STM32_FLASH_OBR, &optiondata);
94
95 stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
96 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
97
98 if (optiondata & (1 << OPT_READOUT))
99 LOG_INFO("Device Security Bit Set");
100
101 /* each bit refers to a 4bank protection */
102 target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
103
104 stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
105 stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
106 stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
107 stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
108
109 return ERROR_OK;
110 }
111
112 static int stm32x_erase_options(struct flash_bank *bank)
113 {
114 struct stm32x_flash_bank *stm32x_info = NULL;
115 struct target *target = bank->target;
116 uint32_t status;
117
118 stm32x_info = bank->driver_priv;
119
120 /* read current options */
121 stm32x_read_options(bank);
122
123 /* unlock flash registers */
124 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
125 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
126
127 /* unlock option flash registers */
128 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
129 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
130
131 /* erase option bytes */
132 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_OPTWRE);
133 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
134
135 status = stm32x_wait_status_busy(bank, 10);
136
137 if (status & FLASH_WRPRTERR)
138 return ERROR_FLASH_OPERATION_FAILED;
139 if (status & FLASH_PGERR)
140 return ERROR_FLASH_OPERATION_FAILED;
141
142 /* clear readout protection and complementary option bytes
143 * this will also force a device unlock if set */
144 stm32x_info->option_bytes.RDP = 0x5AA5;
145
146 return ERROR_OK;
147 }
148
149 static int stm32x_write_options(struct flash_bank *bank)
150 {
151 struct stm32x_flash_bank *stm32x_info = NULL;
152 struct target *target = bank->target;
153 uint32_t status;
154
155 stm32x_info = bank->driver_priv;
156
157 /* unlock flash registers */
158 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
159 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
160
161 /* unlock option flash registers */
162 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
163 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
164
165 /* program option bytes */
166 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG | FLASH_OPTWRE);
167
168 /* write user option byte */
169 target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
170
171 status = stm32x_wait_status_busy(bank, 10);
172
173 if (status & FLASH_WRPRTERR)
174 return ERROR_FLASH_OPERATION_FAILED;
175 if (status & FLASH_PGERR)
176 return ERROR_FLASH_OPERATION_FAILED;
177
178 /* write protection byte 1 */
179 target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
180
181 status = stm32x_wait_status_busy(bank, 10);
182
183 if (status & FLASH_WRPRTERR)
184 return ERROR_FLASH_OPERATION_FAILED;
185 if (status & FLASH_PGERR)
186 return ERROR_FLASH_OPERATION_FAILED;
187
188 /* write protection byte 2 */
189 target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
190
191 status = stm32x_wait_status_busy(bank, 10);
192
193 if (status & FLASH_WRPRTERR)
194 return ERROR_FLASH_OPERATION_FAILED;
195 if (status & FLASH_PGERR)
196 return ERROR_FLASH_OPERATION_FAILED;
197
198 /* write protection byte 3 */
199 target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
200
201 status = stm32x_wait_status_busy(bank, 10);
202
203 if (status & FLASH_WRPRTERR)
204 return ERROR_FLASH_OPERATION_FAILED;
205 if (status & FLASH_PGERR)
206 return ERROR_FLASH_OPERATION_FAILED;
207
208 /* write protection byte 4 */
209 target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
210
211 status = stm32x_wait_status_busy(bank, 10);
212
213 if (status & FLASH_WRPRTERR)
214 return ERROR_FLASH_OPERATION_FAILED;
215 if (status & FLASH_PGERR)
216 return ERROR_FLASH_OPERATION_FAILED;
217
218 /* write readout protection bit */
219 target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
220
221 status = stm32x_wait_status_busy(bank, 10);
222
223 if (status & FLASH_WRPRTERR)
224 return ERROR_FLASH_OPERATION_FAILED;
225 if (status & FLASH_PGERR)
226 return ERROR_FLASH_OPERATION_FAILED;
227
228 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
229
230 return ERROR_OK;
231 }
232
233 static int stm32x_protect_check(struct flash_bank *bank)
234 {
235 struct target *target = bank->target;
236 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
237
238 uint32_t protection;
239 int i, s;
240 int num_bits;
241 int set;
242
243 if (target->state != TARGET_HALTED)
244 {
245 LOG_ERROR("Target not halted");
246 return ERROR_TARGET_NOT_HALTED;
247 }
248
249 /* medium density - each bit refers to a 4bank protection
250 * high density - each bit refers to a 2bank protection */
251 target_read_u32(target, STM32_FLASH_WRPR, &protection);
252
253 /* medium density - each protection bit is for 4 * 1K pages
254 * high density - each protection bit is for 2 * 2K pages */
255 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
256
257 if (stm32x_info->ppage_size == 2)
258 {
259 /* high density flash/connectivity line protection */
260
261 set = 1;
262
263 if (protection & (1 << 31))
264 set = 0;
265
266 /* bit 31 controls sector 62 - 255 protection for high density
267 * bit 31 controls sector 62 - 127 protection for connectivity line */
268 for (s = 62; s < bank->num_sectors; s++)
269 {
270 bank->sectors[s].is_protected = set;
271 }
272
273 if (bank->num_sectors > 61)
274 num_bits = 31;
275
276 for (i = 0; i < num_bits; i++)
277 {
278 set = 1;
279
280 if (protection & (1 << i))
281 set = 0;
282
283 for (s = 0; s < stm32x_info->ppage_size; s++)
284 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
285 }
286 }
287 else
288 {
289 /* low/medium density flash protection */
290 for (i = 0; i < num_bits; i++)
291 {
292 set = 1;
293
294 if (protection & (1 << i))
295 set = 0;
296
297 for (s = 0; s < stm32x_info->ppage_size; s++)
298 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
299 }
300 }
301
302 return ERROR_OK;
303 }
304
305 static int stm32x_erase(struct flash_bank *bank, int first, int last)
306 {
307 struct target *target = bank->target;
308 int i;
309 uint32_t status;
310
311 if (bank->target->state != TARGET_HALTED)
312 {
313 LOG_ERROR("Target not halted");
314 return ERROR_TARGET_NOT_HALTED;
315 }
316
317 if ((first == 0) && (last == (bank->num_sectors - 1)))
318 {
319 return stm32x_mass_erase(bank);
320 }
321
322 /* unlock flash registers */
323 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
324 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
325
326 for (i = first; i <= last; i++)
327 {
328 target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
329 target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
330 target_write_u32(target, STM32_FLASH_CR, FLASH_PER | FLASH_STRT);
331
332 status = stm32x_wait_status_busy(bank, 10);
333
334 if (status & FLASH_WRPRTERR)
335 return ERROR_FLASH_OPERATION_FAILED;
336 if (status & FLASH_PGERR)
337 return ERROR_FLASH_OPERATION_FAILED;
338 bank->sectors[i].is_erased = 1;
339 }
340
341 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
342
343 return ERROR_OK;
344 }
345
346 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
347 {
348 struct stm32x_flash_bank *stm32x_info = NULL;
349 struct target *target = bank->target;
350 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
351 int i, reg, bit;
352 int status;
353 uint32_t protection;
354
355 stm32x_info = bank->driver_priv;
356
357 if (target->state != TARGET_HALTED)
358 {
359 LOG_ERROR("Target not halted");
360 return ERROR_TARGET_NOT_HALTED;
361 }
362
363 if ((first && (first % stm32x_info->ppage_size)) || ((last + 1) && (last + 1) % stm32x_info->ppage_size))
364 {
365 LOG_WARNING("Error: start and end sectors must be on a %d sector boundary", stm32x_info->ppage_size);
366 return ERROR_FLASH_SECTOR_INVALID;
367 }
368
369 /* medium density - each bit refers to a 4bank protection
370 * high density - each bit refers to a 2bank protection */
371 target_read_u32(target, STM32_FLASH_WRPR, &protection);
372
373 prot_reg[0] = (uint16_t)protection;
374 prot_reg[1] = (uint16_t)(protection >> 8);
375 prot_reg[2] = (uint16_t)(protection >> 16);
376 prot_reg[3] = (uint16_t)(protection >> 24);
377
378 if (stm32x_info->ppage_size == 2)
379 {
380 /* high density flash */
381
382 /* bit 7 controls sector 62 - 255 protection */
383 if (last > 61)
384 {
385 if (set)
386 prot_reg[3] &= ~(1 << 7);
387 else
388 prot_reg[3] |= (1 << 7);
389 }
390
391 if (first > 61)
392 first = 62;
393 if (last > 61)
394 last = 61;
395
396 for (i = first; i <= last; i++)
397 {
398 reg = (i / stm32x_info->ppage_size) / 8;
399 bit = (i / stm32x_info->ppage_size) - (reg * 8);
400
401 if (set)
402 prot_reg[reg] &= ~(1 << bit);
403 else
404 prot_reg[reg] |= (1 << bit);
405 }
406 }
407 else
408 {
409 /* medium density flash */
410 for (i = first; i <= last; i++)
411 {
412 reg = (i / stm32x_info->ppage_size) / 8;
413 bit = (i / stm32x_info->ppage_size) - (reg * 8);
414
415 if (set)
416 prot_reg[reg] &= ~(1 << bit);
417 else
418 prot_reg[reg] |= (1 << bit);
419 }
420 }
421
422 if ((status = stm32x_erase_options(bank)) != ERROR_OK)
423 return status;
424
425 stm32x_info->option_bytes.protection[0] = prot_reg[0];
426 stm32x_info->option_bytes.protection[1] = prot_reg[1];
427 stm32x_info->option_bytes.protection[2] = prot_reg[2];
428 stm32x_info->option_bytes.protection[3] = prot_reg[3];
429
430 return stm32x_write_options(bank);
431 }
432
433 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
434 {
435 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
436 struct target *target = bank->target;
437 uint32_t buffer_size = 16384;
438 struct working_area *source;
439 uint32_t address = bank->base + offset;
440 struct reg_param reg_params[4];
441 struct armv7m_algorithm armv7m_info;
442 int retval = ERROR_OK;
443
444 uint8_t stm32x_flash_write_code[] = {
445 /* write: */
446 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
447 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
448 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
449 0x23, 0x60, /* str r3, [r4, #0] */
450 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
451 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
452 /* busy: */
453 0x2B, 0x68, /* ldr r3, [r5, #0] */
454 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
455 0xFB, 0xD0, /* beq busy */
456 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
457 0x01, 0xD1, /* bne exit */
458 0x01, 0x3A, /* subs r2, r2, #1 */
459 0xED, 0xD1, /* bne write */
460 /* exit: */
461 0xFE, 0xE7, /* b exit */
462 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
463 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
464 };
465
466 /* flash write code */
467 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &stm32x_info->write_algorithm) != ERROR_OK)
468 {
469 LOG_WARNING("no working area available, can't do block memory writes");
470 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
471 };
472
473 if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code)) != ERROR_OK)
474 return retval;
475
476 /* memory buffer */
477 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
478 {
479 buffer_size /= 2;
480 if (buffer_size <= 256)
481 {
482 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
483 if (stm32x_info->write_algorithm)
484 target_free_working_area(target, stm32x_info->write_algorithm);
485
486 LOG_WARNING("no large enough working area available, can't do block memory writes");
487 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
488 }
489 };
490
491 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
492 armv7m_info.core_mode = ARMV7M_MODE_ANY;
493
494 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
495 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
496 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
497 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
498
499 while (count > 0)
500 {
501 uint32_t thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
502
503 if ((retval = target_write_buffer(target, source->address, thisrun_count * 2, buffer)) != ERROR_OK)
504 break;
505
506 buf_set_u32(reg_params[0].value, 0, 32, source->address);
507 buf_set_u32(reg_params[1].value, 0, 32, address);
508 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
509
510 if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params, stm32x_info->write_algorithm->address, \
511 stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
512 {
513 LOG_ERROR("error executing stm32x flash write algorithm");
514 retval = ERROR_FLASH_OPERATION_FAILED;
515 break;
516 }
517
518 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_PGERR)
519 {
520 LOG_ERROR("flash memory not erased before writing");
521 /* Clear but report errors */
522 target_write_u32(target, STM32_FLASH_SR, FLASH_PGERR);
523 retval = ERROR_FLASH_OPERATION_FAILED;
524 break;
525 }
526
527 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_WRPRTERR)
528 {
529 LOG_ERROR("flash memory write protected");
530 /* Clear but report errors */
531 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR);
532 retval = ERROR_FLASH_OPERATION_FAILED;
533 break;
534 }
535
536 buffer += thisrun_count * 2;
537 address += thisrun_count * 2;
538 count -= thisrun_count;
539 }
540
541 target_free_working_area(target, source);
542 target_free_working_area(target, stm32x_info->write_algorithm);
543
544 destroy_reg_param(&reg_params[0]);
545 destroy_reg_param(&reg_params[1]);
546 destroy_reg_param(&reg_params[2]);
547 destroy_reg_param(&reg_params[3]);
548
549 return retval;
550 }
551
552 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
553 {
554 struct target *target = bank->target;
555 uint32_t words_remaining = (count / 2);
556 uint32_t bytes_remaining = (count & 0x00000001);
557 uint32_t address = bank->base + offset;
558 uint32_t bytes_written = 0;
559 uint8_t status;
560 int retval;
561
562 if (bank->target->state != TARGET_HALTED)
563 {
564 LOG_ERROR("Target not halted");
565 return ERROR_TARGET_NOT_HALTED;
566 }
567
568 if (offset & 0x1)
569 {
570 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
571 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
572 }
573
574 /* unlock flash registers */
575 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
576 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
577
578 /* multiple half words (2-byte) to be programmed? */
579 if (words_remaining > 0)
580 {
581 /* try using a block write */
582 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
583 {
584 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
585 {
586 /* if block write failed (no sufficient working area),
587 * we use normal (slow) single dword accesses */
588 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
589 }
590 else if (retval == ERROR_FLASH_OPERATION_FAILED)
591 {
592 LOG_ERROR("flash writing failed with error code: 0x%x", retval);
593 return ERROR_FLASH_OPERATION_FAILED;
594 }
595 }
596 else
597 {
598 buffer += words_remaining * 2;
599 address += words_remaining * 2;
600 words_remaining = 0;
601 }
602 }
603
604 while (words_remaining > 0)
605 {
606 uint16_t value;
607 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
608
609 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
610 target_write_u16(target, address, value);
611
612 status = stm32x_wait_status_busy(bank, 5);
613
614 if (status & FLASH_WRPRTERR)
615 {
616 LOG_ERROR("flash memory not erased before writing");
617 return ERROR_FLASH_OPERATION_FAILED;
618 }
619 if (status & FLASH_PGERR)
620 {
621 LOG_ERROR("flash memory write protected");
622 return ERROR_FLASH_OPERATION_FAILED;
623 }
624
625 bytes_written += 2;
626 words_remaining--;
627 address += 2;
628 }
629
630 if (bytes_remaining)
631 {
632 uint16_t value = 0xffff;
633 memcpy(&value, buffer + bytes_written, bytes_remaining);
634
635 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
636 target_write_u16(target, address, value);
637
638 status = stm32x_wait_status_busy(bank, 5);
639
640 if (status & FLASH_WRPRTERR)
641 {
642 LOG_ERROR("flash memory not erased before writing");
643 return ERROR_FLASH_OPERATION_FAILED;
644 }
645 if (status & FLASH_PGERR)
646 {
647 LOG_ERROR("flash memory write protected");
648 return ERROR_FLASH_OPERATION_FAILED;
649 }
650 }
651
652 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
653
654 return ERROR_OK;
655 }
656
657 static int stm32x_probe(struct flash_bank *bank)
658 {
659 struct target *target = bank->target;
660 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
661 int i;
662 uint16_t num_pages;
663 uint32_t device_id;
664 int page_size;
665
666 if (bank->target->state != TARGET_HALTED)
667 {
668 LOG_ERROR("Target not halted");
669 return ERROR_TARGET_NOT_HALTED;
670 }
671
672 stm32x_info->probed = 0;
673
674 /* read stm32 device id register */
675 target_read_u32(target, 0xE0042000, &device_id);
676 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
677
678 /* get flash size from target */
679 if (target_read_u16(target, 0x1FFFF7E0, &num_pages) != ERROR_OK)
680 {
681 /* failed reading flash size, default to max target family */
682 num_pages = 0xffff;
683 }
684
685 if ((device_id & 0x7ff) == 0x410)
686 {
687 /* medium density - we have 1k pages
688 * 4 pages for a protection area */
689 page_size = 1024;
690 stm32x_info->ppage_size = 4;
691
692 /* check for early silicon */
693 if (num_pages == 0xffff)
694 {
695 /* number of sectors incorrect on revA */
696 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
697 num_pages = 128;
698 }
699 }
700 else if ((device_id & 0x7ff) == 0x412)
701 {
702 /* low density - we have 1k pages
703 * 4 pages for a protection area */
704 page_size = 1024;
705 stm32x_info->ppage_size = 4;
706
707 /* check for early silicon */
708 if (num_pages == 0xffff)
709 {
710 /* number of sectors incorrect on revA */
711 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
712 num_pages = 32;
713 }
714 }
715 else if ((device_id & 0x7ff) == 0x414)
716 {
717 /* high density - we have 2k pages
718 * 2 pages for a protection area */
719 page_size = 2048;
720 stm32x_info->ppage_size = 2;
721
722 /* check for early silicon */
723 if (num_pages == 0xffff)
724 {
725 /* number of sectors incorrect on revZ */
726 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
727 num_pages = 512;
728 }
729 }
730 else if ((device_id & 0x7ff) == 0x418)
731 {
732 /* connectivity line density - we have 2k pages
733 * 2 pages for a protection area */
734 page_size = 2048;
735 stm32x_info->ppage_size = 2;
736
737 /* check for early silicon */
738 if (num_pages == 0xffff)
739 {
740 /* number of sectors incorrect on revZ */
741 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
742 num_pages = 256;
743 }
744 }
745 else
746 {
747 LOG_WARNING("Cannot identify target as a STM32 family.");
748 return ERROR_FLASH_OPERATION_FAILED;
749 }
750
751 LOG_INFO("flash size = %dkbytes", num_pages);
752
753 /* calculate numbers of pages */
754 num_pages /= (page_size / 1024);
755
756 bank->base = 0x08000000;
757 bank->size = (num_pages * page_size);
758 bank->num_sectors = num_pages;
759 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
760
761 for (i = 0; i < num_pages; i++)
762 {
763 bank->sectors[i].offset = i * page_size;
764 bank->sectors[i].size = page_size;
765 bank->sectors[i].is_erased = -1;
766 bank->sectors[i].is_protected = 1;
767 }
768
769 stm32x_info->probed = 1;
770
771 return ERROR_OK;
772 }
773
774 static int stm32x_auto_probe(struct flash_bank *bank)
775 {
776 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
777 if (stm32x_info->probed)
778 return ERROR_OK;
779 return stm32x_probe(bank);
780 }
781
782 #if 0
783 COMMAND_HANDLER(stm32x_handle_part_id_command)
784 {
785 return ERROR_OK;
786 }
787 #endif
788
789 static int stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
790 {
791 struct target *target = bank->target;
792 uint32_t device_id;
793 int printed;
794
795 /* read stm32 device id register */
796 target_read_u32(target, 0xE0042000, &device_id);
797
798 if ((device_id & 0x7ff) == 0x410)
799 {
800 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
801 buf += printed;
802 buf_size -= printed;
803
804 switch (device_id >> 16)
805 {
806 case 0x0000:
807 snprintf(buf, buf_size, "A");
808 break;
809
810 case 0x2000:
811 snprintf(buf, buf_size, "B");
812 break;
813
814 case 0x2001:
815 snprintf(buf, buf_size, "Z");
816 break;
817
818 case 0x2003:
819 snprintf(buf, buf_size, "Y");
820 break;
821
822 default:
823 snprintf(buf, buf_size, "unknown");
824 break;
825 }
826 }
827 else if ((device_id & 0x7ff) == 0x412)
828 {
829 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
830 buf += printed;
831 buf_size -= printed;
832
833 switch (device_id >> 16)
834 {
835 case 0x1000:
836 snprintf(buf, buf_size, "A");
837 break;
838
839 default:
840 snprintf(buf, buf_size, "unknown");
841 break;
842 }
843 }
844 else if ((device_id & 0x7ff) == 0x414)
845 {
846 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
847 buf += printed;
848 buf_size -= printed;
849
850 switch (device_id >> 16)
851 {
852 case 0x1000:
853 snprintf(buf, buf_size, "A");
854 break;
855
856 case 0x1001:
857 snprintf(buf, buf_size, "Z");
858 break;
859
860 default:
861 snprintf(buf, buf_size, "unknown");
862 break;
863 }
864 }
865 else if ((device_id & 0x7ff) == 0x418)
866 {
867 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
868 buf += printed;
869 buf_size -= printed;
870
871 switch (device_id >> 16)
872 {
873 case 0x1000:
874 snprintf(buf, buf_size, "A");
875 break;
876
877 case 0x1001:
878 snprintf(buf, buf_size, "Z");
879 break;
880
881 default:
882 snprintf(buf, buf_size, "unknown");
883 break;
884 }
885 }
886 else
887 {
888 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
889 return ERROR_FLASH_OPERATION_FAILED;
890 }
891
892 return ERROR_OK;
893 }
894
895 COMMAND_HANDLER(stm32x_handle_lock_command)
896 {
897 struct target *target = NULL;
898 struct stm32x_flash_bank *stm32x_info = NULL;
899
900 if (argc < 1)
901 {
902 command_print(cmd_ctx, "stm32x lock <bank>");
903 return ERROR_OK;
904 }
905
906 struct flash_bank *bank;
907 int retval = flash_command_get_bank_by_num(cmd_ctx, args[0], &bank);
908 if (ERROR_OK != retval)
909 return retval;
910
911 stm32x_info = bank->driver_priv;
912
913 target = bank->target;
914
915 if (target->state != TARGET_HALTED)
916 {
917 LOG_ERROR("Target not halted");
918 return ERROR_TARGET_NOT_HALTED;
919 }
920
921 if (stm32x_erase_options(bank) != ERROR_OK)
922 {
923 command_print(cmd_ctx, "stm32x failed to erase options");
924 return ERROR_OK;
925 }
926
927 /* set readout protection */
928 stm32x_info->option_bytes.RDP = 0;
929
930 if (stm32x_write_options(bank) != ERROR_OK)
931 {
932 command_print(cmd_ctx, "stm32x failed to lock device");
933 return ERROR_OK;
934 }
935
936 command_print(cmd_ctx, "stm32x locked");
937
938 return ERROR_OK;
939 }
940
941 COMMAND_HANDLER(stm32x_handle_unlock_command)
942 {
943 struct target *target = NULL;
944 struct stm32x_flash_bank *stm32x_info = NULL;
945
946 if (argc < 1)
947 {
948 command_print(cmd_ctx, "stm32x unlock <bank>");
949 return ERROR_OK;
950 }
951
952 struct flash_bank *bank;
953 int retval = flash_command_get_bank_by_num(cmd_ctx, args[0], &bank);
954 if (ERROR_OK != retval)
955 return retval;
956
957 stm32x_info = bank->driver_priv;
958
959 target = bank->target;
960
961 if (target->state != TARGET_HALTED)
962 {
963 LOG_ERROR("Target not halted");
964 return ERROR_TARGET_NOT_HALTED;
965 }
966
967 if (stm32x_erase_options(bank) != ERROR_OK)
968 {
969 command_print(cmd_ctx, "stm32x failed to unlock device");
970 return ERROR_OK;
971 }
972
973 if (stm32x_write_options(bank) != ERROR_OK)
974 {
975 command_print(cmd_ctx, "stm32x failed to lock device");
976 return ERROR_OK;
977 }
978
979 command_print(cmd_ctx, "stm32x unlocked");
980
981 return ERROR_OK;
982 }
983
984 COMMAND_HANDLER(stm32x_handle_options_read_command)
985 {
986 uint32_t optionbyte;
987 struct target *target = NULL;
988 struct stm32x_flash_bank *stm32x_info = NULL;
989
990 if (argc < 1)
991 {
992 command_print(cmd_ctx, "stm32x options_read <bank>");
993 return ERROR_OK;
994 }
995
996 struct flash_bank *bank;
997 int retval = flash_command_get_bank_by_num(cmd_ctx, args[0], &bank);
998 if (ERROR_OK != retval)
999 return retval;
1000
1001 stm32x_info = bank->driver_priv;
1002
1003 target = bank->target;
1004
1005 if (target->state != TARGET_HALTED)
1006 {
1007 LOG_ERROR("Target not halted");
1008 return ERROR_TARGET_NOT_HALTED;
1009 }
1010
1011 target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
1012 command_print(cmd_ctx, "Option Byte: 0x%" PRIx32 "", optionbyte);
1013
1014 if (buf_get_u32((uint8_t*)&optionbyte, OPT_ERROR, 1))
1015 command_print(cmd_ctx, "Option Byte Complement Error");
1016
1017 if (buf_get_u32((uint8_t*)&optionbyte, OPT_READOUT, 1))
1018 command_print(cmd_ctx, "Readout Protection On");
1019 else
1020 command_print(cmd_ctx, "Readout Protection Off");
1021
1022 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDWDGSW, 1))
1023 command_print(cmd_ctx, "Software Watchdog");
1024 else
1025 command_print(cmd_ctx, "Hardware Watchdog");
1026
1027 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTOP, 1))
1028 command_print(cmd_ctx, "Stop: No reset generated");
1029 else
1030 command_print(cmd_ctx, "Stop: Reset generated");
1031
1032 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTDBY, 1))
1033 command_print(cmd_ctx, "Standby: No reset generated");
1034 else
1035 command_print(cmd_ctx, "Standby: Reset generated");
1036
1037 return ERROR_OK;
1038 }
1039
1040 COMMAND_HANDLER(stm32x_handle_options_write_command)
1041 {
1042 struct target *target = NULL;
1043 struct stm32x_flash_bank *stm32x_info = NULL;
1044 uint16_t optionbyte = 0xF8;
1045
1046 if (argc < 4)
1047 {
1048 command_print(cmd_ctx, "stm32x options_write <bank> <SWWDG | HWWDG> <RSTSTNDBY | NORSTSTNDBY> <RSTSTOP | NORSTSTOP>");
1049 return ERROR_OK;
1050 }
1051
1052 struct flash_bank *bank;
1053 int retval = flash_command_get_bank_by_num(cmd_ctx, args[0], &bank);
1054 if (ERROR_OK != retval)
1055 return retval;
1056
1057 stm32x_info = bank->driver_priv;
1058
1059 target = bank->target;
1060
1061 if (target->state != TARGET_HALTED)
1062 {
1063 LOG_ERROR("Target not halted");
1064 return ERROR_TARGET_NOT_HALTED;
1065 }
1066
1067 if (strcmp(args[1], "SWWDG") == 0)
1068 {
1069 optionbyte |= (1 << 0);
1070 }
1071 else
1072 {
1073 optionbyte &= ~(1 << 0);
1074 }
1075
1076 if (strcmp(args[2], "NORSTSTNDBY") == 0)
1077 {
1078 optionbyte |= (1 << 1);
1079 }
1080 else
1081 {
1082 optionbyte &= ~(1 << 1);
1083 }
1084
1085 if (strcmp(args[3], "NORSTSTOP") == 0)
1086 {
1087 optionbyte |= (1 << 2);
1088 }
1089 else
1090 {
1091 optionbyte &= ~(1 << 2);
1092 }
1093
1094 if (stm32x_erase_options(bank) != ERROR_OK)
1095 {
1096 command_print(cmd_ctx, "stm32x failed to erase options");
1097 return ERROR_OK;
1098 }
1099
1100 stm32x_info->option_bytes.user_options = optionbyte;
1101
1102 if (stm32x_write_options(bank) != ERROR_OK)
1103 {
1104 command_print(cmd_ctx, "stm32x failed to write options");
1105 return ERROR_OK;
1106 }
1107
1108 command_print(cmd_ctx, "stm32x write options complete");
1109
1110 return ERROR_OK;
1111 }
1112
1113 static int stm32x_mass_erase(struct flash_bank *bank)
1114 {
1115 struct target *target = bank->target;
1116 uint32_t status;
1117
1118 if (target->state != TARGET_HALTED)
1119 {
1120 LOG_ERROR("Target not halted");
1121 return ERROR_TARGET_NOT_HALTED;
1122 }
1123
1124 /* unlock option flash registers */
1125 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
1126 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
1127
1128 /* mass erase flash memory */
1129 target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
1130 target_write_u32(target, STM32_FLASH_CR, FLASH_MER | FLASH_STRT);
1131
1132 status = stm32x_wait_status_busy(bank, 10);
1133
1134 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
1135
1136 if (status & FLASH_WRPRTERR)
1137 {
1138 LOG_ERROR("stm32x device protected");
1139 return ERROR_OK;
1140 }
1141
1142 if (status & FLASH_PGERR)
1143 {
1144 LOG_ERROR("stm32x device programming failed");
1145 return ERROR_OK;
1146 }
1147
1148 return ERROR_OK;
1149 }
1150
1151 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1152 {
1153 int i;
1154
1155 if (argc < 1)
1156 {
1157 command_print(cmd_ctx, "stm32x mass_erase <bank>");
1158 return ERROR_OK;
1159 }
1160
1161 struct flash_bank *bank;
1162 int retval = flash_command_get_bank_by_num(cmd_ctx, args[0], &bank);
1163 if (ERROR_OK != retval)
1164 return retval;
1165
1166 if (stm32x_mass_erase(bank) == ERROR_OK)
1167 {
1168 /* set all sectors as erased */
1169 for (i = 0; i < bank->num_sectors; i++)
1170 {
1171 bank->sectors[i].is_erased = 1;
1172 }
1173
1174 command_print(cmd_ctx, "stm32x mass erase complete");
1175 }
1176 else
1177 {
1178 command_print(cmd_ctx, "stm32x mass erase failed");
1179 }
1180
1181 return ERROR_OK;
1182 }
1183
1184 static int stm32x_register_commands(struct command_context_s *cmd_ctx)
1185 {
1186 command_t *stm32x_cmd = register_command(cmd_ctx, NULL, "stm32x",
1187 NULL, COMMAND_ANY, "stm32x flash specific commands");
1188
1189 register_command(cmd_ctx, stm32x_cmd, "lock",
1190 stm32x_handle_lock_command, COMMAND_EXEC,
1191 "lock device");
1192 register_command(cmd_ctx, stm32x_cmd, "unlock",
1193 stm32x_handle_unlock_command, COMMAND_EXEC,
1194 "unlock protected device");
1195 register_command(cmd_ctx, stm32x_cmd, "mass_erase",
1196 stm32x_handle_mass_erase_command, COMMAND_EXEC,
1197 "mass erase device");
1198 register_command(cmd_ctx, stm32x_cmd, "options_read",
1199 stm32x_handle_options_read_command, COMMAND_EXEC,
1200 "read device option bytes");
1201 register_command(cmd_ctx, stm32x_cmd, "options_write",
1202 stm32x_handle_options_write_command, COMMAND_EXEC,
1203 "write device option bytes");
1204
1205 return ERROR_OK;
1206 }
1207
1208 struct flash_driver stm32x_flash = {
1209 .name = "stm32x",
1210 .register_commands = &stm32x_register_commands,
1211 .flash_bank_command = &stm32x_flash_bank_command,
1212 .erase = &stm32x_erase,
1213 .protect = &stm32x_protect,
1214 .write = &stm32x_write,
1215 .probe = &stm32x_probe,
1216 .auto_probe = &stm32x_auto_probe,
1217 .erase_check = &default_flash_mem_blank_check,
1218 .protect_check = &stm32x_protect_check,
1219 .info = &stm32x_info,
1220 };
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