1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
31 #include "algorithm.h"
32 #include "binarybuffer.h"
37 int stm32x_register_commands(struct command_context_s
*cmd_ctx
);
38 int stm32x_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
);
39 int stm32x_erase(struct flash_bank_s
*bank
, int first
, int last
);
40 int stm32x_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
);
41 int stm32x_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
);
42 int stm32x_probe(struct flash_bank_s
*bank
);
43 int stm32x_handle_part_id_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
44 int stm32x_protect_check(struct flash_bank_s
*bank
);
45 int stm32x_erase_check(struct flash_bank_s
*bank
);
46 int stm32x_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
);
48 int stm32x_handle_lock_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
49 int stm32x_handle_unlock_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
50 int stm32x_handle_options_read_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
51 int stm32x_handle_options_write_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
52 int stm32x_handle_mass_erase_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
54 flash_driver_t stm32x_flash
=
57 .register_commands
= stm32x_register_commands
,
58 .flash_bank_command
= stm32x_flash_bank_command
,
59 .erase
= stm32x_erase
,
60 .protect
= stm32x_protect
,
61 .write
= stm32x_write
,
62 .probe
= stm32x_probe
,
63 .auto_probe
= stm32x_probe
,
64 .erase_check
= stm32x_erase_check
,
65 .protect_check
= stm32x_protect_check
,
69 int stm32x_register_commands(struct command_context_s
*cmd_ctx
)
71 command_t
*stm32x_cmd
= register_command(cmd_ctx
, NULL
, "stm32x", NULL
, COMMAND_ANY
, "stm32x flash specific commands");
73 register_command(cmd_ctx
, stm32x_cmd
, "lock", stm32x_handle_lock_command
, COMMAND_EXEC
,
75 register_command(cmd_ctx
, stm32x_cmd
, "unlock", stm32x_handle_unlock_command
, COMMAND_EXEC
,
76 "unlock protected device");
77 register_command(cmd_ctx
, stm32x_cmd
, "mass_erase", stm32x_handle_mass_erase_command
, COMMAND_EXEC
,
79 register_command(cmd_ctx
, stm32x_cmd
, "options_read", stm32x_handle_options_read_command
, COMMAND_EXEC
,
80 "read device option bytes");
81 register_command(cmd_ctx
, stm32x_cmd
, "options_write", stm32x_handle_options_write_command
, COMMAND_EXEC
,
82 "write device option bytes");
86 int stm32x_build_block_list(struct flash_bank_s
*bank
)
103 ERROR("BUG: unknown bank->size encountered");
107 bank
->num_sectors
= num_sectors
;
108 bank
->sectors
= malloc(sizeof(flash_sector_t
) * num_sectors
);
110 for (i
= 0; i
< num_sectors
; i
++)
112 bank
->sectors
[i
].offset
= i
* 1024;
113 bank
->sectors
[i
].size
= 1024;
114 bank
->sectors
[i
].is_erased
= -1;
115 bank
->sectors
[i
].is_protected
= 1;
121 /* flash bank stm32x <base> <size> 0 0 <target#>
123 int stm32x_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
)
125 stm32x_flash_bank_t
*stm32x_info
;
129 WARNING("incomplete flash_bank stm32x configuration");
130 return ERROR_FLASH_BANK_INVALID
;
133 stm32x_info
= malloc(sizeof(stm32x_flash_bank_t
));
134 bank
->driver_priv
= stm32x_info
;
136 if (bank
->base
!= 0x08000000)
138 WARNING("overriding flash base address for STM32x device with 0x08000000");
139 bank
->base
= 0x08000000;
142 stm32x_build_block_list(bank
);
144 stm32x_info
->write_algorithm
= NULL
;
149 u32
stm32x_get_flash_status(flash_bank_t
*bank
)
151 target_t
*target
= bank
->target
;
154 target_read_u32(target
, STM32_FLASH_SR
, &status
);
159 u32
stm32x_wait_status_busy(flash_bank_t
*bank
, int timeout
)
163 /* wait for busy to clear */
164 while (((status
= stm32x_get_flash_status(bank
)) & FLASH_BSY
) && (timeout
-- > 0))
166 DEBUG("status: 0x%x", status
);
173 int stm32x_read_options(struct flash_bank_s
*bank
)
176 stm32x_flash_bank_t
*stm32x_info
= NULL
;
177 target_t
*target
= bank
->target
;
179 stm32x_info
= bank
->driver_priv
;
181 /* read current option bytes */
182 target_read_u32(target
, STM32_FLASH_OBR
, &optiondata
);
184 stm32x_info
->option_bytes
.user_options
= (u16
)0xFFF8|((optiondata
>> 2) & 0x07);
185 stm32x_info
->option_bytes
.RDP
= (optiondata
& (1 << OPT_READOUT
)) ? 0xFFFF : 0x5AA5;
187 if (optiondata
& (1 << OPT_READOUT
))
188 INFO("Device Security Bit Set");
190 /* each bit refers to a 4bank protection */
191 target_read_u32(target
, STM32_FLASH_WRPR
, &optiondata
);
193 stm32x_info
->option_bytes
.protection
[0] = (u16
)optiondata
;
194 stm32x_info
->option_bytes
.protection
[1] = (u16
)(optiondata
>> 8);
195 stm32x_info
->option_bytes
.protection
[2] = (u16
)(optiondata
>> 16);
196 stm32x_info
->option_bytes
.protection
[3] = (u16
)(optiondata
>> 24);
201 int stm32x_erase_options(struct flash_bank_s
*bank
)
203 stm32x_flash_bank_t
*stm32x_info
= NULL
;
204 target_t
*target
= bank
->target
;
207 stm32x_info
= bank
->driver_priv
;
209 /* read current options */
210 stm32x_read_options(bank
);
212 /* unlock flash registers */
213 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
214 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
216 /* unlock option flash registers */
217 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY1
);
218 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY2
);
220 /* erase option bytes */
221 target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTER
|FLASH_OPTWRE
);
222 target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTER
|FLASH_STRT
|FLASH_OPTWRE
);
224 status
= stm32x_wait_status_busy(bank
, 10);
226 if( status
& FLASH_WRPRTERR
)
227 return ERROR_FLASH_OPERATION_FAILED
;
228 if( status
& FLASH_PGERR
)
229 return ERROR_FLASH_OPERATION_FAILED
;
231 /* clear readout protection and complementary option bytes
232 * this will also force a device unlock if set */
233 stm32x_info
->option_bytes
.RDP
= 0x5AA5;
238 int stm32x_write_options(struct flash_bank_s
*bank
)
240 stm32x_flash_bank_t
*stm32x_info
= NULL
;
241 target_t
*target
= bank
->target
;
244 stm32x_info
= bank
->driver_priv
;
246 /* unlock flash registers */
247 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
248 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
250 /* unlock option flash registers */
251 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY1
);
252 target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY2
);
254 /* program option bytes */
255 target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTPG
|FLASH_OPTWRE
);
257 /* write user option byte */
258 target_write_u16(target
, STM32_OB_USER
, stm32x_info
->option_bytes
.user_options
);
260 status
= stm32x_wait_status_busy(bank
, 10);
262 if( status
& FLASH_WRPRTERR
)
263 return ERROR_FLASH_OPERATION_FAILED
;
264 if( status
& FLASH_PGERR
)
265 return ERROR_FLASH_OPERATION_FAILED
;
267 /* write protection byte 1 */
268 target_write_u16(target
, STM32_OB_WRP0
, stm32x_info
->option_bytes
.protection
[0]);
270 status
= stm32x_wait_status_busy(bank
, 10);
272 if( status
& FLASH_WRPRTERR
)
273 return ERROR_FLASH_OPERATION_FAILED
;
274 if( status
& FLASH_PGERR
)
275 return ERROR_FLASH_OPERATION_FAILED
;
277 /* write protection byte 2 */
278 target_write_u16(target
, STM32_OB_WRP1
, stm32x_info
->option_bytes
.protection
[1]);
280 status
= stm32x_wait_status_busy(bank
, 10);
282 if( status
& FLASH_WRPRTERR
)
283 return ERROR_FLASH_OPERATION_FAILED
;
284 if( status
& FLASH_PGERR
)
285 return ERROR_FLASH_OPERATION_FAILED
;
287 /* write protection byte 3 */
288 target_write_u16(target
, STM32_OB_WRP2
, stm32x_info
->option_bytes
.protection
[2]);
290 status
= stm32x_wait_status_busy(bank
, 10);
292 if( status
& FLASH_WRPRTERR
)
293 return ERROR_FLASH_OPERATION_FAILED
;
294 if( status
& FLASH_PGERR
)
295 return ERROR_FLASH_OPERATION_FAILED
;
297 /* write protection byte 4 */
298 target_write_u16(target
, STM32_OB_WRP3
, stm32x_info
->option_bytes
.protection
[3]);
300 status
= stm32x_wait_status_busy(bank
, 10);
302 if( status
& FLASH_WRPRTERR
)
303 return ERROR_FLASH_OPERATION_FAILED
;
304 if( status
& FLASH_PGERR
)
305 return ERROR_FLASH_OPERATION_FAILED
;
307 /* write readout protection bit */
308 target_write_u16(target
, STM32_OB_RDP
, stm32x_info
->option_bytes
.RDP
);
310 status
= stm32x_wait_status_busy(bank
, 10);
312 if( status
& FLASH_WRPRTERR
)
313 return ERROR_FLASH_OPERATION_FAILED
;
314 if( status
& FLASH_PGERR
)
315 return ERROR_FLASH_OPERATION_FAILED
;
317 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
322 int stm32x_blank_check(struct flash_bank_s
*bank
, int first
, int last
)
324 target_t
*target
= bank
->target
;
329 if ((first
< 0) || (last
> bank
->num_sectors
))
330 return ERROR_FLASH_SECTOR_INVALID
;
332 if (target
->state
!= TARGET_HALTED
)
334 return ERROR_TARGET_NOT_HALTED
;
337 buffer
= malloc(256);
339 for (i
= first
; i
<= last
; i
++)
341 bank
->sectors
[i
].is_erased
= 1;
343 target
->type
->read_memory(target
, bank
->base
+ bank
->sectors
[i
].offset
, 4, 256/4, buffer
);
345 for (nBytes
= 0; nBytes
< 256; nBytes
++)
347 if (buffer
[nBytes
] != 0xFF)
349 bank
->sectors
[i
].is_erased
= 0;
360 int stm32x_protect_check(struct flash_bank_s
*bank
)
362 target_t
*target
= bank
->target
;
368 if (target
->state
!= TARGET_HALTED
)
370 return ERROR_TARGET_NOT_HALTED
;
373 /* each bit refers to a 4bank protection */
374 target_read_u32(target
, STM32_FLASH_WRPR
, &protection
);
376 /* each protection bit is for 4 1K pages */
377 num_bits
= (bank
->num_sectors
/ 4);
379 for (i
= 0; i
< num_bits
; i
++)
383 if( protection
& (1 << i
))
386 for (s
= 0; s
< 4; s
++)
387 bank
->sectors
[(i
* 4) + s
].is_protected
= set
;
393 int stm32x_erase(struct flash_bank_s
*bank
, int first
, int last
)
395 target_t
*target
= bank
->target
;
400 if (target
->state
!= TARGET_HALTED
)
402 return ERROR_TARGET_NOT_HALTED
;
405 /* unlock flash registers */
406 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
407 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
409 for (i
= first
; i
<= last
; i
++)
411 target_write_u32(target
, STM32_FLASH_CR
, FLASH_PER
);
412 target_write_u32(target
, STM32_FLASH_AR
, bank
->base
+ bank
->sectors
[i
].offset
);
413 target_write_u32(target
, STM32_FLASH_CR
, FLASH_PER
|FLASH_STRT
);
415 status
= stm32x_wait_status_busy(bank
, 10);
417 if( status
& FLASH_WRPRTERR
)
418 return ERROR_FLASH_OPERATION_FAILED
;
419 if( status
& FLASH_PGERR
)
420 return ERROR_FLASH_OPERATION_FAILED
;
421 bank
->sectors
[i
].is_erased
= 1;
424 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
429 int stm32x_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
431 stm32x_flash_bank_t
*stm32x_info
= NULL
;
432 target_t
*target
= bank
->target
;
433 u16 prot_reg
[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
438 stm32x_info
= bank
->driver_priv
;
440 if (target
->state
!= TARGET_HALTED
)
442 return ERROR_TARGET_NOT_HALTED
;
445 if ((first
&& (first
% 4)) || ((last
+ 1) && (last
+ 1) % 4))
447 WARNING("sector start/end incorrect - stm32 has 4K sector protection");
448 return ERROR_FLASH_SECTOR_INVALID
;
451 /* each bit refers to a 4bank protection */
452 target_read_u32(target
, STM32_FLASH_WRPR
, &protection
);
454 prot_reg
[0] = (u16
)protection
;
455 prot_reg
[1] = (u16
)(protection
>> 8);
456 prot_reg
[2] = (u16
)(protection
>> 16);
457 prot_reg
[3] = (u16
)(protection
>> 24);
459 for (i
= first
; i
<= last
; i
++)
462 bit
= (i
/ 4) - (reg
* 8);
465 prot_reg
[reg
] &= ~(1 << bit
);
467 prot_reg
[reg
] |= (1 << bit
);
470 if ((status
= stm32x_erase_options(bank
)) != ERROR_OK
)
473 stm32x_info
->option_bytes
.protection
[0] = prot_reg
[0];
474 stm32x_info
->option_bytes
.protection
[1] = prot_reg
[1];
475 stm32x_info
->option_bytes
.protection
[2] = prot_reg
[2];
476 stm32x_info
->option_bytes
.protection
[3] = prot_reg
[3];
478 return stm32x_write_options(bank
);
481 int stm32x_write_block(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
)
483 stm32x_flash_bank_t
*stm32x_info
= bank
->driver_priv
;
484 target_t
*target
= bank
->target
;
485 u32 buffer_size
= 8192;
486 working_area_t
*source
;
487 u32 address
= bank
->base
+ offset
;
488 reg_param_t reg_params
[4];
489 armv7m_algorithm_t armv7m_info
;
490 int retval
= ERROR_OK
;
492 u8 stm32x_flash_write_code
[] = {
494 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
495 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
496 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
497 0x23, 0x60, /* str r3, [r4, #0] */
498 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
499 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
501 0x2B, 0x68, /* ldr r3, [r5, #0] */
502 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
503 0xFB, 0xD0, /* beq busy */
504 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
505 0x01, 0xD1, /* bne exit */
506 0x01, 0x3A, /* subs r2, r2, #1 */
507 0xED, 0xD1, /* bne write */
509 0xFE, 0xE7, /* b exit */
510 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
511 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
514 /* flash write code */
515 if (target_alloc_working_area(target
, sizeof(stm32x_flash_write_code
), &stm32x_info
->write_algorithm
) != ERROR_OK
)
517 WARNING("no working area available, can't do block memory writes");
518 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
521 target_write_buffer(target
, stm32x_info
->write_algorithm
->address
, sizeof(stm32x_flash_write_code
), stm32x_flash_write_code
);
524 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
)
527 if (buffer_size
<= 256)
529 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
530 if (stm32x_info
->write_algorithm
)
531 target_free_working_area(target
, stm32x_info
->write_algorithm
);
533 WARNING("no large enough working area available, can't do block memory writes");
534 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
538 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
539 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
540 armv7m_info
.core_state
= ARMV7M_STATE_THUMB
;
542 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
543 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
544 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
545 init_reg_param(®_params
[3], "r3", 32, PARAM_IN
);
549 u32 thisrun_count
= (count
> (buffer_size
/ 2)) ? (buffer_size
/ 2) : count
;
551 target_write_buffer(target
, source
->address
, thisrun_count
* 2, buffer
);
553 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
554 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
555 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
);
557 if ((retval
= target
->type
->run_algorithm(target
, 0, NULL
, 4, reg_params
, stm32x_info
->write_algorithm
->address
, \
558 stm32x_info
->write_algorithm
->address
+ (sizeof(stm32x_flash_write_code
) - 10), 10000, &armv7m_info
)) != ERROR_OK
)
560 ERROR("error executing str7x flash write algorithm");
564 if (buf_get_u32(reg_params
[3].value
, 0, 32) & 0x14)
566 retval
= ERROR_FLASH_OPERATION_FAILED
;
570 buffer
+= thisrun_count
* 2;
571 address
+= thisrun_count
* 2;
572 count
-= thisrun_count
;
575 target_free_working_area(target
, source
);
576 target_free_working_area(target
, stm32x_info
->write_algorithm
);
578 destroy_reg_param(®_params
[0]);
579 destroy_reg_param(®_params
[1]);
580 destroy_reg_param(®_params
[2]);
581 destroy_reg_param(®_params
[3]);
586 int stm32x_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
)
588 target_t
*target
= bank
->target
;
589 u32 words_remaining
= (count
/ 2);
590 u32 bytes_remaining
= (count
& 0x00000001);
591 u32 address
= bank
->base
+ offset
;
592 u32 bytes_written
= 0;
596 if (target
->state
!= TARGET_HALTED
)
598 return ERROR_TARGET_NOT_HALTED
;
603 WARNING("offset 0x%x breaks required 2-byte alignment", offset
);
604 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
607 /* unlock flash registers */
608 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
609 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
611 /* multiple half words (2-byte) to be programmed? */
612 if (words_remaining
> 0)
614 /* try using a block write */
615 if ((retval
= stm32x_write_block(bank
, buffer
, offset
, words_remaining
)) != ERROR_OK
)
617 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
619 /* if block write failed (no sufficient working area),
620 * we use normal (slow) single dword accesses */
621 WARNING("couldn't use block writes, falling back to single memory accesses");
623 else if (retval
== ERROR_FLASH_OPERATION_FAILED
)
625 ERROR("flash writing failed with error code: 0x%x", retval
);
626 return ERROR_FLASH_OPERATION_FAILED
;
631 buffer
+= words_remaining
* 2;
632 address
+= words_remaining
* 2;
637 while (words_remaining
> 0)
639 target_write_u32(target
, STM32_FLASH_CR
, FLASH_PG
);
640 target_write_u16(target
, address
, *(u16
*)(buffer
+ bytes_written
));
642 status
= stm32x_wait_status_busy(bank
, 5);
644 if( status
& FLASH_WRPRTERR
)
645 return ERROR_FLASH_OPERATION_FAILED
;
646 if( status
& FLASH_PGERR
)
647 return ERROR_FLASH_OPERATION_FAILED
;
656 u8 last_halfword
[2] = {0xff, 0xff};
659 while(bytes_remaining
> 0)
661 last_halfword
[i
++] = *(buffer
+ bytes_written
);
666 target_write_u32(target
, STM32_FLASH_CR
, FLASH_PG
);
667 target_write_u16(target
, address
, *(u16
*)last_halfword
);
669 status
= stm32x_wait_status_busy(bank
, 5);
671 if( status
& FLASH_WRPRTERR
)
672 return ERROR_FLASH_OPERATION_FAILED
;
673 if( status
& FLASH_PGERR
)
674 return ERROR_FLASH_OPERATION_FAILED
;
677 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
682 int stm32x_probe(struct flash_bank_s
*bank
)
687 int stm32x_handle_part_id_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
692 int stm32x_erase_check(struct flash_bank_s
*bank
)
694 return stm32x_blank_check(bank
, 0, bank
->num_sectors
- 1);
697 int stm32x_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
699 snprintf(buf
, buf_size
, "stm32x flash driver info" );
703 int stm32x_handle_lock_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
706 target_t
*target
= NULL
;
707 stm32x_flash_bank_t
*stm32x_info
= NULL
;
711 command_print(cmd_ctx
, "stm32x lock <bank>");
715 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
718 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
722 stm32x_info
= bank
->driver_priv
;
724 target
= bank
->target
;
726 if (target
->state
!= TARGET_HALTED
)
728 return ERROR_TARGET_NOT_HALTED
;
731 if (stm32x_erase_options(bank
) != ERROR_OK
)
733 command_print(cmd_ctx
, "stm32x failed to erase options");
737 /* set readout protection */
738 stm32x_info
->option_bytes
.RDP
= 0;
740 if (stm32x_write_options(bank
) != ERROR_OK
)
742 command_print(cmd_ctx
, "stm32x failed to lock device");
746 command_print(cmd_ctx
, "stm32x locked");
751 int stm32x_handle_unlock_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
754 target_t
*target
= NULL
;
755 stm32x_flash_bank_t
*stm32x_info
= NULL
;
759 command_print(cmd_ctx
, "stm32x unlock <bank>");
763 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
766 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
770 stm32x_info
= bank
->driver_priv
;
772 target
= bank
->target
;
774 if (target
->state
!= TARGET_HALTED
)
776 return ERROR_TARGET_NOT_HALTED
;
779 if (stm32x_erase_options(bank
) != ERROR_OK
)
781 command_print(cmd_ctx
, "stm32x failed to unlock device");
785 if (stm32x_write_options(bank
) != ERROR_OK
)
787 command_print(cmd_ctx
, "stm32x failed to lock device");
791 command_print(cmd_ctx
, "stm32x unlocked");
796 int stm32x_handle_options_read_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
800 target_t
*target
= NULL
;
801 stm32x_flash_bank_t
*stm32x_info
= NULL
;
805 command_print(cmd_ctx
, "stm32x options_read <bank>");
809 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
812 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
816 stm32x_info
= bank
->driver_priv
;
818 target
= bank
->target
;
820 if (target
->state
!= TARGET_HALTED
)
822 return ERROR_TARGET_NOT_HALTED
;
825 target_read_u32(target
, STM32_FLASH_OBR
, &optionbyte
);
826 command_print(cmd_ctx
, "Option Byte: 0x%x", optionbyte
);
828 if (buf_get_u32((u8
*)&optionbyte
, OPT_ERROR
, 1))
829 command_print(cmd_ctx
, "Option Byte Complement Error");
831 if (buf_get_u32((u8
*)&optionbyte
, OPT_READOUT
, 1))
832 command_print(cmd_ctx
, "Readout Protection On");
834 command_print(cmd_ctx
, "Readout Protection Off");
836 if (buf_get_u32((u8
*)&optionbyte
, OPT_RDWDGSW
, 1))
837 command_print(cmd_ctx
, "Software Watchdog");
839 command_print(cmd_ctx
, "Hardware Watchdog");
841 if (buf_get_u32((u8
*)&optionbyte
, OPT_RDRSTSTOP
, 1))
842 command_print(cmd_ctx
, "Stop: No reset generated");
844 command_print(cmd_ctx
, "Stop: Reset generated");
846 if (buf_get_u32((u8
*)&optionbyte
, OPT_RDRSTSTDBY
, 1))
847 command_print(cmd_ctx
, "Standby: No reset generated");
849 command_print(cmd_ctx
, "Standby: Reset generated");
854 int stm32x_handle_options_write_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
857 target_t
*target
= NULL
;
858 stm32x_flash_bank_t
*stm32x_info
= NULL
;
859 u16 optionbyte
= 0xF8;
863 command_print(cmd_ctx
, "stm32x options_write <bank> <SWWDG|HWWDG> <RSTSTNDBY|NORSTSTNDBY> <RSTSTOP|NORSTSTOP>");
867 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
870 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
874 stm32x_info
= bank
->driver_priv
;
876 target
= bank
->target
;
878 if (target
->state
!= TARGET_HALTED
)
880 return ERROR_TARGET_NOT_HALTED
;
883 if (strcmp(args
[1], "SWWDG") == 0)
885 optionbyte
|= (1<<0);
889 optionbyte
&= ~(1<<0);
892 if (strcmp(args
[2], "NORSTSTNDBY") == 0)
894 optionbyte
|= (1<<1);
898 optionbyte
&= ~(1<<1);
901 if (strcmp(args
[3], "NORSTSTOP") == 0)
903 optionbyte
|= (1<<2);
907 optionbyte
&= ~(1<<2);
910 if (stm32x_erase_options(bank
) != ERROR_OK
)
912 command_print(cmd_ctx
, "stm32x failed to erase options");
916 stm32x_info
->option_bytes
.user_options
= optionbyte
;
918 if (stm32x_write_options(bank
) != ERROR_OK
)
920 command_print(cmd_ctx
, "stm32x failed to write options");
924 command_print(cmd_ctx
, "stm32x write options complete");
929 int stm32x_handle_mass_erase_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
931 target_t
*target
= NULL
;
932 stm32x_flash_bank_t
*stm32x_info
= NULL
;
938 command_print(cmd_ctx
, "stm32x mass_erase <bank>");
942 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
945 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
949 stm32x_info
= bank
->driver_priv
;
951 target
= bank
->target
;
953 if (target
->state
!= TARGET_HALTED
)
955 return ERROR_TARGET_NOT_HALTED
;
958 /* unlock option flash registers */
959 target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
960 target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
962 /* mass erase flash memory */
963 target_write_u32(target
, STM32_FLASH_CR
, FLASH_MER
);
964 target_write_u32(target
, STM32_FLASH_CR
, FLASH_MER
|FLASH_STRT
);
966 status
= stm32x_wait_status_busy(bank
, 10);
968 target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
970 if( status
& FLASH_WRPRTERR
)
972 command_print(cmd_ctx
, "stm32x device protected");
976 if( status
& FLASH_PGERR
)
978 command_print(cmd_ctx
, "stm32x device programming failed");
982 command_print(cmd_ctx
, "stm32x mass erase complete");
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