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dos2unix fix.
[openocd.git] / src / flash / stm32x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "replacements.h"
25
26 #include "stm32x.h"
27 #include "flash.h"
28 #include "target.h"
29 #include "log.h"
30 #include "armv7m.h"
31 #include "algorithm.h"
32 #include "binarybuffer.h"
33
34 #include <stdlib.h>
35 #include <string.h>
36
37 int stm32x_register_commands(struct command_context_s *cmd_ctx);
38 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
39 int stm32x_erase(struct flash_bank_s *bank, int first, int last);
40 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last);
41 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
42 int stm32x_probe(struct flash_bank_s *bank);
43 int stm32x_auto_probe(struct flash_bank_s *bank);
44 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
45 int stm32x_protect_check(struct flash_bank_s *bank);
46 int stm32x_erase_check(struct flash_bank_s *bank);
47 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size);
48
49 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
50 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
51 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
52 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
54
55 flash_driver_t stm32x_flash =
56 {
57 .name = "stm32x",
58 .register_commands = stm32x_register_commands,
59 .flash_bank_command = stm32x_flash_bank_command,
60 .erase = stm32x_erase,
61 .protect = stm32x_protect,
62 .write = stm32x_write,
63 .probe = stm32x_probe,
64 .auto_probe = stm32x_auto_probe,
65 .erase_check = stm32x_erase_check,
66 .protect_check = stm32x_protect_check,
67 .info = stm32x_info
68 };
69
70 int stm32x_register_commands(struct command_context_s *cmd_ctx)
71 {
72 command_t *stm32x_cmd = register_command(cmd_ctx, NULL, "stm32x", NULL, COMMAND_ANY, "stm32x flash specific commands");
73
74 register_command(cmd_ctx, stm32x_cmd, "lock", stm32x_handle_lock_command, COMMAND_EXEC,
75 "lock device");
76 register_command(cmd_ctx, stm32x_cmd, "unlock", stm32x_handle_unlock_command, COMMAND_EXEC,
77 "unlock protected device");
78 register_command(cmd_ctx, stm32x_cmd, "mass_erase", stm32x_handle_mass_erase_command, COMMAND_EXEC,
79 "mass erase device");
80 register_command(cmd_ctx, stm32x_cmd, "options_read", stm32x_handle_options_read_command, COMMAND_EXEC,
81 "read device option bytes");
82 register_command(cmd_ctx, stm32x_cmd, "options_write", stm32x_handle_options_write_command, COMMAND_EXEC,
83 "write device option bytes");
84 return ERROR_OK;
85 }
86
87 /* flash bank stm32x <base> <size> 0 0 <target#>
88 */
89 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
90 {
91 stm32x_flash_bank_t *stm32x_info;
92
93 if (argc < 6)
94 {
95 WARNING("incomplete flash_bank stm32x configuration");
96 return ERROR_FLASH_BANK_INVALID;
97 }
98
99 stm32x_info = malloc(sizeof(stm32x_flash_bank_t));
100 bank->driver_priv = stm32x_info;
101
102 stm32x_info->write_algorithm = NULL;
103 stm32x_info->probed = 0;
104
105 return ERROR_OK;
106 }
107
108 u32 stm32x_get_flash_status(flash_bank_t *bank)
109 {
110 target_t *target = bank->target;
111 u32 status;
112
113 target_read_u32(target, STM32_FLASH_SR, &status);
114
115 return status;
116 }
117
118 u32 stm32x_wait_status_busy(flash_bank_t *bank, int timeout)
119 {
120 u32 status;
121
122 /* wait for busy to clear */
123 while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))
124 {
125 DEBUG("status: 0x%x", status);
126 usleep(1000);
127 }
128
129 return status;
130 }
131
132 int stm32x_read_options(struct flash_bank_s *bank)
133 {
134 u32 optiondata;
135 stm32x_flash_bank_t *stm32x_info = NULL;
136 target_t *target = bank->target;
137
138 stm32x_info = bank->driver_priv;
139
140 /* read current option bytes */
141 target_read_u32(target, STM32_FLASH_OBR, &optiondata);
142
143 stm32x_info->option_bytes.user_options = (u16)0xFFF8|((optiondata >> 2) & 0x07);
144 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
145
146 if (optiondata & (1 << OPT_READOUT))
147 INFO("Device Security Bit Set");
148
149 /* each bit refers to a 4bank protection */
150 target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
151
152 stm32x_info->option_bytes.protection[0] = (u16)optiondata;
153 stm32x_info->option_bytes.protection[1] = (u16)(optiondata >> 8);
154 stm32x_info->option_bytes.protection[2] = (u16)(optiondata >> 16);
155 stm32x_info->option_bytes.protection[3] = (u16)(optiondata >> 24);
156
157 return ERROR_OK;
158 }
159
160 int stm32x_erase_options(struct flash_bank_s *bank)
161 {
162 stm32x_flash_bank_t *stm32x_info = NULL;
163 target_t *target = bank->target;
164 u32 status;
165
166 stm32x_info = bank->driver_priv;
167
168 /* read current options */
169 stm32x_read_options(bank);
170
171 /* unlock flash registers */
172 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
173 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
174
175 /* unlock option flash registers */
176 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
177 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
178
179 /* erase option bytes */
180 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_OPTWRE);
181 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_STRT|FLASH_OPTWRE);
182
183 status = stm32x_wait_status_busy(bank, 10);
184
185 if( status & FLASH_WRPRTERR )
186 return ERROR_FLASH_OPERATION_FAILED;
187 if( status & FLASH_PGERR )
188 return ERROR_FLASH_OPERATION_FAILED;
189
190 /* clear readout protection and complementary option bytes
191 * this will also force a device unlock if set */
192 stm32x_info->option_bytes.RDP = 0x5AA5;
193
194 return ERROR_OK;
195 }
196
197 int stm32x_write_options(struct flash_bank_s *bank)
198 {
199 stm32x_flash_bank_t *stm32x_info = NULL;
200 target_t *target = bank->target;
201 u32 status;
202
203 stm32x_info = bank->driver_priv;
204
205 /* unlock flash registers */
206 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
207 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
208
209 /* unlock option flash registers */
210 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
211 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
212
213 /* program option bytes */
214 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG|FLASH_OPTWRE);
215
216 /* write user option byte */
217 target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
218
219 status = stm32x_wait_status_busy(bank, 10);
220
221 if( status & FLASH_WRPRTERR )
222 return ERROR_FLASH_OPERATION_FAILED;
223 if( status & FLASH_PGERR )
224 return ERROR_FLASH_OPERATION_FAILED;
225
226 /* write protection byte 1 */
227 target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
228
229 status = stm32x_wait_status_busy(bank, 10);
230
231 if( status & FLASH_WRPRTERR )
232 return ERROR_FLASH_OPERATION_FAILED;
233 if( status & FLASH_PGERR )
234 return ERROR_FLASH_OPERATION_FAILED;
235
236 /* write protection byte 2 */
237 target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
238
239 status = stm32x_wait_status_busy(bank, 10);
240
241 if( status & FLASH_WRPRTERR )
242 return ERROR_FLASH_OPERATION_FAILED;
243 if( status & FLASH_PGERR )
244 return ERROR_FLASH_OPERATION_FAILED;
245
246 /* write protection byte 3 */
247 target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
248
249 status = stm32x_wait_status_busy(bank, 10);
250
251 if( status & FLASH_WRPRTERR )
252 return ERROR_FLASH_OPERATION_FAILED;
253 if( status & FLASH_PGERR )
254 return ERROR_FLASH_OPERATION_FAILED;
255
256 /* write protection byte 4 */
257 target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
258
259 status = stm32x_wait_status_busy(bank, 10);
260
261 if( status & FLASH_WRPRTERR )
262 return ERROR_FLASH_OPERATION_FAILED;
263 if( status & FLASH_PGERR )
264 return ERROR_FLASH_OPERATION_FAILED;
265
266 /* write readout protection bit */
267 target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
268
269 status = stm32x_wait_status_busy(bank, 10);
270
271 if( status & FLASH_WRPRTERR )
272 return ERROR_FLASH_OPERATION_FAILED;
273 if( status & FLASH_PGERR )
274 return ERROR_FLASH_OPERATION_FAILED;
275
276 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
277
278 return ERROR_OK;
279 }
280
281 int stm32x_blank_check(struct flash_bank_s *bank, int first, int last)
282 {
283 target_t *target = bank->target;
284 u8 *buffer;
285 int i;
286 int nBytes;
287
288 if ((first < 0) || (last > bank->num_sectors))
289 return ERROR_FLASH_SECTOR_INVALID;
290
291 if (target->state != TARGET_HALTED)
292 {
293 return ERROR_TARGET_NOT_HALTED;
294 }
295
296 buffer = malloc(256);
297
298 for (i = first; i <= last; i++)
299 {
300 bank->sectors[i].is_erased = 1;
301
302 target->type->read_memory(target, bank->base + bank->sectors[i].offset, 4, 256/4, buffer);
303
304 for (nBytes = 0; nBytes < 256; nBytes++)
305 {
306 if (buffer[nBytes] != 0xFF)
307 {
308 bank->sectors[i].is_erased = 0;
309 break;
310 }
311 }
312 }
313
314 free(buffer);
315
316 return ERROR_OK;
317 }
318
319 int stm32x_protect_check(struct flash_bank_s *bank)
320 {
321 target_t *target = bank->target;
322
323 u32 protection;
324 int i, s;
325 int num_bits;
326
327 if (target->state != TARGET_HALTED)
328 {
329 return ERROR_TARGET_NOT_HALTED;
330 }
331
332 /* each bit refers to a 4bank protection */
333 target_read_u32(target, STM32_FLASH_WRPR, &protection);
334
335 /* each protection bit is for 4 1K pages */
336 num_bits = (bank->num_sectors / 4);
337
338 for (i = 0; i < num_bits; i++)
339 {
340 int set = 1;
341
342 if( protection & (1 << i))
343 set = 0;
344
345 for (s = 0; s < 4; s++)
346 bank->sectors[(i * 4) + s].is_protected = set;
347 }
348
349 return ERROR_OK;
350 }
351
352 int stm32x_erase(struct flash_bank_s *bank, int first, int last)
353 {
354 target_t *target = bank->target;
355
356 int i;
357 u32 status;
358
359 /* unlock flash registers */
360 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
361 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
362
363 for (i = first; i <= last; i++)
364 {
365 target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
366 target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
367 target_write_u32(target, STM32_FLASH_CR, FLASH_PER|FLASH_STRT);
368
369 status = stm32x_wait_status_busy(bank, 10);
370
371 if( status & FLASH_WRPRTERR )
372 return ERROR_FLASH_OPERATION_FAILED;
373 if( status & FLASH_PGERR )
374 return ERROR_FLASH_OPERATION_FAILED;
375 bank->sectors[i].is_erased = 1;
376 }
377
378 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
379
380 return ERROR_OK;
381 }
382
383 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last)
384 {
385 stm32x_flash_bank_t *stm32x_info = NULL;
386 target_t *target = bank->target;
387 u16 prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
388 int i, reg, bit;
389 int status;
390 u32 protection;
391
392 stm32x_info = bank->driver_priv;
393
394 if (target->state != TARGET_HALTED)
395 {
396 return ERROR_TARGET_NOT_HALTED;
397 }
398
399 if ((first && (first % 4)) || ((last + 1) && (last + 1) % 4))
400 {
401 WARNING("sector start/end incorrect - stm32 has 4K sector protection");
402 return ERROR_FLASH_SECTOR_INVALID;
403 }
404
405 /* each bit refers to a 4bank protection */
406 target_read_u32(target, STM32_FLASH_WRPR, &protection);
407
408 prot_reg[0] = (u16)protection;
409 prot_reg[1] = (u16)(protection >> 8);
410 prot_reg[2] = (u16)(protection >> 16);
411 prot_reg[3] = (u16)(protection >> 24);
412
413 for (i = first; i <= last; i++)
414 {
415 reg = (i / 4) / 8;
416 bit = (i / 4) - (reg * 8);
417
418 if( set )
419 prot_reg[reg] &= ~(1 << bit);
420 else
421 prot_reg[reg] |= (1 << bit);
422 }
423
424 if ((status = stm32x_erase_options(bank)) != ERROR_OK)
425 return status;
426
427 stm32x_info->option_bytes.protection[0] = prot_reg[0];
428 stm32x_info->option_bytes.protection[1] = prot_reg[1];
429 stm32x_info->option_bytes.protection[2] = prot_reg[2];
430 stm32x_info->option_bytes.protection[3] = prot_reg[3];
431
432 return stm32x_write_options(bank);
433 }
434
435 int stm32x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
436 {
437 stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
438 target_t *target = bank->target;
439 u32 buffer_size = 8192;
440 working_area_t *source;
441 u32 address = bank->base + offset;
442 reg_param_t reg_params[4];
443 armv7m_algorithm_t armv7m_info;
444 int retval = ERROR_OK;
445
446 u8 stm32x_flash_write_code[] = {
447 /* write: */
448 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
449 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
450 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
451 0x23, 0x60, /* str r3, [r4, #0] */
452 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
453 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
454 /* busy: */
455 0x2B, 0x68, /* ldr r3, [r5, #0] */
456 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
457 0xFB, 0xD0, /* beq busy */
458 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
459 0x01, 0xD1, /* bne exit */
460 0x01, 0x3A, /* subs r2, r2, #1 */
461 0xED, 0xD1, /* bne write */
462 /* exit: */
463 0xFE, 0xE7, /* b exit */
464 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
465 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
466 };
467
468 /* flash write code */
469 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &stm32x_info->write_algorithm) != ERROR_OK)
470 {
471 WARNING("no working area available, can't do block memory writes");
472 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
473 };
474
475 target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
476
477 /* memory buffer */
478 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
479 {
480 buffer_size /= 2;
481 if (buffer_size <= 256)
482 {
483 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
484 if (stm32x_info->write_algorithm)
485 target_free_working_area(target, stm32x_info->write_algorithm);
486
487 WARNING("no large enough working area available, can't do block memory writes");
488 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
489 }
490 };
491
492 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
493 armv7m_info.core_mode = ARMV7M_MODE_ANY;
494 armv7m_info.core_state = ARMV7M_STATE_THUMB;
495
496 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
497 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
498 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
499 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
500
501 while (count > 0)
502 {
503 u32 thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
504
505 target_write_buffer(target, source->address, thisrun_count * 2, buffer);
506
507 buf_set_u32(reg_params[0].value, 0, 32, source->address);
508 buf_set_u32(reg_params[1].value, 0, 32, address);
509 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
510
511 if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, stm32x_info->write_algorithm->address, \
512 stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
513 {
514 ERROR("error executing str7x flash write algorithm");
515 break;
516 }
517
518 if (buf_get_u32(reg_params[3].value, 0, 32) & 0x14)
519 {
520 retval = ERROR_FLASH_OPERATION_FAILED;
521 break;
522 }
523
524 buffer += thisrun_count * 2;
525 address += thisrun_count * 2;
526 count -= thisrun_count;
527 }
528
529 target_free_working_area(target, source);
530 target_free_working_area(target, stm32x_info->write_algorithm);
531
532 destroy_reg_param(&reg_params[0]);
533 destroy_reg_param(&reg_params[1]);
534 destroy_reg_param(&reg_params[2]);
535 destroy_reg_param(&reg_params[3]);
536
537 return retval;
538 }
539
540 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
541 {
542 target_t *target = bank->target;
543 u32 words_remaining = (count / 2);
544 u32 bytes_remaining = (count & 0x00000001);
545 u32 address = bank->base + offset;
546 u32 bytes_written = 0;
547 u8 status;
548 u32 retval;
549
550 if (offset & 0x1)
551 {
552 WARNING("offset 0x%x breaks required 2-byte alignment", offset);
553 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
554 }
555
556 /* unlock flash registers */
557 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
558 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
559
560 /* multiple half words (2-byte) to be programmed? */
561 if (words_remaining > 0)
562 {
563 /* try using a block write */
564 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
565 {
566 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
567 {
568 /* if block write failed (no sufficient working area),
569 * we use normal (slow) single dword accesses */
570 WARNING("couldn't use block writes, falling back to single memory accesses");
571 }
572 else if (retval == ERROR_FLASH_OPERATION_FAILED)
573 {
574 ERROR("flash writing failed with error code: 0x%x", retval);
575 return ERROR_FLASH_OPERATION_FAILED;
576 }
577 }
578 else
579 {
580 buffer += words_remaining * 2;
581 address += words_remaining * 2;
582 words_remaining = 0;
583 }
584 }
585
586 while (words_remaining > 0)
587 {
588 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
589 target_write_u16(target, address, *(u16*)(buffer + bytes_written));
590
591 status = stm32x_wait_status_busy(bank, 5);
592
593 if( status & FLASH_WRPRTERR )
594 return ERROR_FLASH_OPERATION_FAILED;
595 if( status & FLASH_PGERR )
596 return ERROR_FLASH_OPERATION_FAILED;
597
598 bytes_written += 2;
599 words_remaining--;
600 address += 2;
601 }
602
603 if (bytes_remaining)
604 {
605 u8 last_halfword[2] = {0xff, 0xff};
606 int i = 0;
607
608 while(bytes_remaining > 0)
609 {
610 last_halfword[i++] = *(buffer + bytes_written);
611 bytes_remaining--;
612 bytes_written++;
613 }
614
615 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
616 target_write_u16(target, address, *(u16*)last_halfword);
617
618 status = stm32x_wait_status_busy(bank, 5);
619
620 if( status & FLASH_WRPRTERR )
621 return ERROR_FLASH_OPERATION_FAILED;
622 if( status & FLASH_PGERR )
623 return ERROR_FLASH_OPERATION_FAILED;
624 }
625
626 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
627
628 return ERROR_OK;
629 }
630
631 int stm32x_probe(struct flash_bank_s *bank)
632 {
633 target_t *target = bank->target;
634 stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
635 int i;
636 u16 num_sectors;
637 u32 device_id;
638
639 stm32x_info->probed = 0;
640
641 /* read stm32 device id register */
642 target_read_u32(target, 0xE0042000, &device_id);
643 INFO( "device id = 0x%08x", device_id );
644
645 if (!(device_id & 0x410))
646 {
647 WARNING( "Cannot identify target as a STM32 family." );
648 return ERROR_FLASH_OPERATION_FAILED;
649 }
650
651 /* get flash size from target */
652 target_read_u16(target, 0x1FFFF7E0, &num_sectors);
653
654 /* check for early silicon rev A */
655 if ((device_id >> 16) == 0 )
656 {
657 /* number of sectors incorrect on revA */
658 WARNING( "STM32 Rev A Silicon detected, probe inaccurate - assuming 128k flash" );
659 num_sectors = 128;
660 }
661
662 INFO( "flash size = %dkbytes", num_sectors );
663
664 bank->base = 0x08000000;
665 bank->size = num_sectors * 1024;
666 bank->num_sectors = num_sectors;
667 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
668
669 for (i = 0; i < num_sectors; i++)
670 {
671 bank->sectors[i].offset = i * 1024;
672 bank->sectors[i].size = 1024;
673 bank->sectors[i].is_erased = -1;
674 bank->sectors[i].is_protected = 1;
675 }
676
677 stm32x_info->probed = 1;
678
679 return ERROR_OK;
680 }
681
682 int stm32x_auto_probe(struct flash_bank_s *bank)
683 {
684 stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
685 if (stm32x_info->probed)
686 return ERROR_OK;
687 return stm32x_probe(bank);
688 }
689
690 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
691 {
692 return ERROR_OK;
693 }
694
695 int stm32x_erase_check(struct flash_bank_s *bank)
696 {
697 return stm32x_blank_check(bank, 0, bank->num_sectors - 1);
698 }
699
700 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size)
701 {
702 snprintf(buf, buf_size, "stm32x flash driver info" );
703 return ERROR_OK;
704 }
705
706 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
707 {
708 flash_bank_t *bank;
709 target_t *target = NULL;
710 stm32x_flash_bank_t *stm32x_info = NULL;
711
712 if (argc < 1)
713 {
714 command_print(cmd_ctx, "stm32x lock <bank>");
715 return ERROR_OK;
716 }
717
718 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
719 if (!bank)
720 {
721 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
722 return ERROR_OK;
723 }
724
725 stm32x_info = bank->driver_priv;
726
727 target = bank->target;
728
729 if (target->state != TARGET_HALTED)
730 {
731 return ERROR_TARGET_NOT_HALTED;
732 }
733
734 if (stm32x_erase_options(bank) != ERROR_OK)
735 {
736 command_print(cmd_ctx, "stm32x failed to erase options");
737 return ERROR_OK;
738 }
739
740 /* set readout protection */
741 stm32x_info->option_bytes.RDP = 0;
742
743 if (stm32x_write_options(bank) != ERROR_OK)
744 {
745 command_print(cmd_ctx, "stm32x failed to lock device");
746 return ERROR_OK;
747 }
748
749 command_print(cmd_ctx, "stm32x locked");
750
751 return ERROR_OK;
752 }
753
754 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
755 {
756 flash_bank_t *bank;
757 target_t *target = NULL;
758 stm32x_flash_bank_t *stm32x_info = NULL;
759
760 if (argc < 1)
761 {
762 command_print(cmd_ctx, "stm32x unlock <bank>");
763 return ERROR_OK;
764 }
765
766 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
767 if (!bank)
768 {
769 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
770 return ERROR_OK;
771 }
772
773 stm32x_info = bank->driver_priv;
774
775 target = bank->target;
776
777 if (target->state != TARGET_HALTED)
778 {
779 return ERROR_TARGET_NOT_HALTED;
780 }
781
782 if (stm32x_erase_options(bank) != ERROR_OK)
783 {
784 command_print(cmd_ctx, "stm32x failed to unlock device");
785 return ERROR_OK;
786 }
787
788 if (stm32x_write_options(bank) != ERROR_OK)
789 {
790 command_print(cmd_ctx, "stm32x failed to lock device");
791 return ERROR_OK;
792 }
793
794 command_print(cmd_ctx, "stm32x unlocked");
795
796 return ERROR_OK;
797 }
798
799 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
800 {
801 flash_bank_t *bank;
802 u32 optionbyte;
803 target_t *target = NULL;
804 stm32x_flash_bank_t *stm32x_info = NULL;
805
806 if (argc < 1)
807 {
808 command_print(cmd_ctx, "stm32x options_read <bank>");
809 return ERROR_OK;
810 }
811
812 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
813 if (!bank)
814 {
815 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
816 return ERROR_OK;
817 }
818
819 stm32x_info = bank->driver_priv;
820
821 target = bank->target;
822
823 if (target->state != TARGET_HALTED)
824 {
825 return ERROR_TARGET_NOT_HALTED;
826 }
827
828 target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
829 command_print(cmd_ctx, "Option Byte: 0x%x", optionbyte);
830
831 if (buf_get_u32((u8*)&optionbyte, OPT_ERROR, 1))
832 command_print(cmd_ctx, "Option Byte Complement Error");
833
834 if (buf_get_u32((u8*)&optionbyte, OPT_READOUT, 1))
835 command_print(cmd_ctx, "Readout Protection On");
836 else
837 command_print(cmd_ctx, "Readout Protection Off");
838
839 if (buf_get_u32((u8*)&optionbyte, OPT_RDWDGSW, 1))
840 command_print(cmd_ctx, "Software Watchdog");
841 else
842 command_print(cmd_ctx, "Hardware Watchdog");
843
844 if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTOP, 1))
845 command_print(cmd_ctx, "Stop: No reset generated");
846 else
847 command_print(cmd_ctx, "Stop: Reset generated");
848
849 if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTDBY, 1))
850 command_print(cmd_ctx, "Standby: No reset generated");
851 else
852 command_print(cmd_ctx, "Standby: Reset generated");
853
854 return ERROR_OK;
855 }
856
857 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
858 {
859 flash_bank_t *bank;
860 target_t *target = NULL;
861 stm32x_flash_bank_t *stm32x_info = NULL;
862 u16 optionbyte = 0xF8;
863
864 if (argc < 4)
865 {
866 command_print(cmd_ctx, "stm32x options_write <bank> <SWWDG|HWWDG> <RSTSTNDBY|NORSTSTNDBY> <RSTSTOP|NORSTSTOP>");
867 return ERROR_OK;
868 }
869
870 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
871 if (!bank)
872 {
873 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
874 return ERROR_OK;
875 }
876
877 stm32x_info = bank->driver_priv;
878
879 target = bank->target;
880
881 if (target->state != TARGET_HALTED)
882 {
883 return ERROR_TARGET_NOT_HALTED;
884 }
885
886 if (strcmp(args[1], "SWWDG") == 0)
887 {
888 optionbyte |= (1<<0);
889 }
890 else
891 {
892 optionbyte &= ~(1<<0);
893 }
894
895 if (strcmp(args[2], "NORSTSTNDBY") == 0)
896 {
897 optionbyte |= (1<<1);
898 }
899 else
900 {
901 optionbyte &= ~(1<<1);
902 }
903
904 if (strcmp(args[3], "NORSTSTOP") == 0)
905 {
906 optionbyte |= (1<<2);
907 }
908 else
909 {
910 optionbyte &= ~(1<<2);
911 }
912
913 if (stm32x_erase_options(bank) != ERROR_OK)
914 {
915 command_print(cmd_ctx, "stm32x failed to erase options");
916 return ERROR_OK;
917 }
918
919 stm32x_info->option_bytes.user_options = optionbyte;
920
921 if (stm32x_write_options(bank) != ERROR_OK)
922 {
923 command_print(cmd_ctx, "stm32x failed to write options");
924 return ERROR_OK;
925 }
926
927 command_print(cmd_ctx, "stm32x write options complete");
928
929 return ERROR_OK;
930 }
931
932 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
933 {
934 target_t *target = NULL;
935 stm32x_flash_bank_t *stm32x_info = NULL;
936 flash_bank_t *bank;
937 u32 status;
938
939 if (argc < 1)
940 {
941 command_print(cmd_ctx, "stm32x mass_erase <bank>");
942 return ERROR_OK;
943 }
944
945 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
946 if (!bank)
947 {
948 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
949 return ERROR_OK;
950 }
951
952 stm32x_info = bank->driver_priv;
953
954 target = bank->target;
955
956 if (target->state != TARGET_HALTED)
957 {
958 return ERROR_TARGET_NOT_HALTED;
959 }
960
961 /* unlock option flash registers */
962 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
963 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
964
965 /* mass erase flash memory */
966 target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
967 target_write_u32(target, STM32_FLASH_CR, FLASH_MER|FLASH_STRT);
968
969 status = stm32x_wait_status_busy(bank, 10);
970
971 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
972
973 if( status & FLASH_WRPRTERR )
974 {
975 command_print(cmd_ctx, "stm32x device protected");
976 return ERROR_OK;
977 }
978
979 if( status & FLASH_PGERR )
980 {
981 command_print(cmd_ctx, "stm32x device programming failed");
982 return ERROR_OK;
983 }
984
985 command_print(cmd_ctx, "stm32x mass erase complete");
986
987 return ERROR_OK;
988 }
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