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- add missing files from previous commit (tms470 flash driver)
[openocd.git] / src / flash / tms470.c
1 /***************************************************************************
2 * (c) Copyright 2007, 2008 by Christopher Kilgour *
3 * techie |_at_| whiterocker |_dot_| com *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20
21 #ifdef HAVE_CONFIG_H
22 #include "config.h"
23 #endif
24
25 #include "log.h"
26 #include "tms470.h"
27 #include <string.h>
28 #include <unistd.h>
29
30 int
31 tms470_register_commands( struct command_context_s *cmd_ctx );
32
33 int
34 tms470_flash_bank_command( struct command_context_s *cmd_ctx,
35 char *cmd,
36 char **args,
37 int argc,
38 struct flash_bank_s *bank );
39
40 int
41 tms470_erase( struct flash_bank_s *bank,
42 int first,
43 int last );
44
45 int
46 tms470_protect( struct flash_bank_s *bank,
47 int set,
48 int first,
49 int last );
50
51 int
52 tms470_write( struct flash_bank_s *bank,
53 u8 *buffer,
54 u32 offset,
55 u32 count );
56
57 int
58 tms470_probe( struct flash_bank_s *bank );
59
60 int
61 tms470_erase_check( struct flash_bank_s *bank );
62
63 int
64 tms470_protect_check( struct flash_bank_s *bank );
65
66 int
67 tms470_info( struct flash_bank_s *bank,
68 char *buf,
69 int buf_size );
70
71 flash_driver_t tms470_flash =
72 {
73 .name = "tms470",
74 .register_commands = tms470_register_commands,
75 .flash_bank_command = tms470_flash_bank_command,
76 .erase = tms470_erase,
77 .protect = tms470_protect,
78 .write = tms470_write,
79 .probe = tms470_probe,
80 .erase_check = tms470_erase_check,
81 .protect_check = tms470_protect_check,
82 .info = tms470_info
83 };
84
85 /* ----------------------------------------------------------------------
86 Internal Support, Helpers
87 ---------------------------------------------------------------------- */
88
89 const flash_sector_t TMS470R1A256_SECTORS[] =
90 {
91 { 0x00000000, 0x00002000, -1, -1 },
92 { 0x00002000, 0x00002000, -1, -1 },
93 { 0x00004000, 0x00002000, -1, -1 },
94 { 0x00006000, 0x00002000, -1, -1 },
95 { 0x00008000, 0x00008000, -1, -1 },
96 { 0x00010000, 0x00008000, -1, -1 },
97 { 0x00018000, 0x00008000, -1, -1 },
98 { 0x00020000, 0x00008000, -1, -1 },
99 { 0x00028000, 0x00008000, -1, -1 },
100 { 0x00030000, 0x00008000, -1, -1 },
101 { 0x00038000, 0x00002000, -1, -1 },
102 { 0x0003A000, 0x00002000, -1, -1 },
103 { 0x0003C000, 0x00002000, -1, -1 },
104 { 0x0003E000, 0x00002000, -1, -1 },
105 };
106
107 #define TMS470R1A256_NUM_SECTORS \
108 (sizeof(TMS470R1A256_SECTORS)/sizeof(TMS470R1A256_SECTORS[0]))
109
110 const flash_sector_t TMS470R1A288_BANK0_SECTORS[] =
111 {
112 { 0x00000000, 0x00002000, -1, -1 },
113 { 0x00002000, 0x00002000, -1, -1 },
114 { 0x00004000, 0x00002000, -1, -1 },
115 { 0x00006000, 0x00002000, -1, -1 },
116 };
117
118 #define TMS470R1A288_BANK0_NUM_SECTORS \
119 (sizeof(TMS470R1A288_BANK0_SECTORS)/sizeof(TMS470R1A288_BANK0_SECTORS[0]))
120
121 const flash_sector_t TMS470R1A288_BANK1_SECTORS[] =
122 {
123 { 0x00040000, 0x00010000, -1, -1 },
124 { 0x00050000, 0x00010000, -1, -1 },
125 { 0x00060000, 0x00010000, -1, -1 },
126 { 0x00070000, 0x00010000, -1, -1 },
127 };
128
129 #define TMS470R1A288_BANK1_NUM_SECTORS \
130 (sizeof(TMS470R1A288_BANK1_SECTORS)/sizeof(TMS470R1A288_BANK1_SECTORS[0]))
131
132 /* ---------------------------------------------------------------------- */
133
134 int
135 tms470_read_part_info( struct flash_bank_s *bank )
136 {
137 tms470_flash_bank_t *tms470_info = bank->driver_priv;
138 target_t *target = bank->target;
139 u32 device_ident_reg;
140 u32 silicon_version;
141 u32 technology_family;
142 u32 rom_flash;
143 u32 part_number;
144 char * part_name;
145
146 if (target->state != TARGET_HALTED)
147 {
148 WARNING( "Cannot communicate... target not halted." );
149 return ERROR_TARGET_NOT_HALTED;
150 }
151
152 /* read and parse the device identification register */
153 target_read_u32( target, 0xFFFFFFF0, &device_ident_reg );
154
155 INFO( "device_ident_reg=0x%08x", device_ident_reg );
156
157 if ((device_ident_reg & 7) == 0)
158 {
159 WARNING( "Cannot identify target as a TMS470 family." );
160 return ERROR_FLASH_OPERATION_FAILED;
161 }
162
163 silicon_version = (device_ident_reg >> 12) & 0xF;
164 technology_family = (device_ident_reg >> 11) & 1;
165 rom_flash = (device_ident_reg >> 10) & 1;
166 part_number = (device_ident_reg >> 3) & 0x7f;
167
168 /*
169 * If the part number is known, determine if the flash bank is valid
170 * based on the base address being within the known flash bank
171 * ranges. Then fixup/complete the remaining fields of the flash
172 * bank structure.
173 */
174 switch( part_number )
175 {
176 case 0x0a:
177 part_name = "TMS470R1A256";
178
179 if (bank->base >= 0x00040000)
180 {
181 ERROR( "No %s flash bank contains base address 0x%08x.",
182 part_name, bank->base );
183 return ERROR_FLASH_OPERATION_FAILED;
184 }
185 tms470_info->ordinal = 0;
186 bank->base = 0x00000000;
187 bank->size = 256*1024;
188 bank->num_sectors = TMS470R1A256_NUM_SECTORS;
189 bank->sectors = malloc( sizeof( TMS470R1A256_SECTORS ) );
190 if (!bank->sectors)
191 {
192 return ERROR_FLASH_OPERATION_FAILED;
193 }
194 (void) memcpy( bank->sectors,
195 TMS470R1A256_SECTORS,
196 sizeof( TMS470R1A256_SECTORS ) );
197 break;
198
199 case 0x2b:
200 part_name = "TMS470R1A288";
201
202 if ((bank->base >= 0x00000000) && (bank->base < 0x00008000))
203 {
204 tms470_info->ordinal = 0;
205 bank->base = 0x00000000;
206 bank->size = 32*1024;
207 bank->num_sectors = TMS470R1A288_BANK0_NUM_SECTORS;
208 bank->sectors = malloc( sizeof( TMS470R1A288_BANK0_SECTORS ) );
209 if (!bank->sectors)
210 {
211 return ERROR_FLASH_OPERATION_FAILED;
212 }
213 (void) memcpy( bank->sectors,
214 TMS470R1A288_BANK0_SECTORS,
215 sizeof( TMS470R1A288_BANK0_SECTORS ) );
216 }
217 else if ((bank->base >= 0x00040000) && (bank->base < 0x00080000))
218 {
219 tms470_info->ordinal = 1;
220 bank->base = 0x00040000;
221 bank->size = 256*1024;
222 bank->num_sectors = TMS470R1A288_BANK1_NUM_SECTORS;
223 bank->sectors = malloc( sizeof( TMS470R1A288_BANK1_SECTORS ) );
224 if (!bank->sectors)
225 {
226 return ERROR_FLASH_OPERATION_FAILED;
227 }
228 (void) memcpy( bank->sectors,
229 TMS470R1A288_BANK1_SECTORS,
230 sizeof( TMS470R1A288_BANK1_SECTORS ) );
231 }
232 else
233 {
234 ERROR( "No %s flash bank contains base address 0x%08x.",
235 part_name, bank->base );
236 return ERROR_FLASH_OPERATION_FAILED;
237 }
238 break;
239
240 default:
241 WARNING( "Could not identify part 0x%02x as a member of the TMS470 family.",
242 part_number );
243 return ERROR_FLASH_OPERATION_FAILED;
244 }
245
246 /* turn off memory selects */
247 target_write_u32( target, 0xFFFFFFE4, 0x00000000 );
248 target_write_u32( target, 0xFFFFFFE0, 0x00000000 );
249
250 bank->chip_width = 32;
251 bank->bus_width = 32;
252
253 INFO( "Identified %s, ver=%d, core=%s, nvmem=%s.",
254 part_name,
255 silicon_version,
256 (technology_family ? "1.8v" : "3.3v"),
257 (rom_flash ? "rom" : "flash") );
258
259 tms470_info->device_ident_reg = device_ident_reg;
260 tms470_info->silicon_version = silicon_version;
261 tms470_info->technology_family = technology_family;
262 tms470_info->rom_flash = rom_flash;
263 tms470_info->part_number = part_number;
264 tms470_info->part_name = part_name;
265
266 /*
267 * Disable reset on address access violation.
268 */
269 target_write_u32( target, 0xFFFFFFE0, 0x00004007 );
270
271 return ERROR_OK;
272 }
273
274 /* ---------------------------------------------------------------------- */
275
276 u32 keysSet = 0;
277 u32 flashKeys[4];
278
279 int
280 tms470_handle_flash_keyset_command( struct command_context_s * cmd_ctx,
281 char * cmd,
282 char ** args,
283 int argc )
284 {
285 if (argc > 4)
286 {
287 command_print( cmd_ctx, "tms470 flash_keyset <key0> <key1> <key2> <key3>" );
288 return ERROR_INVALID_ARGUMENTS;
289 }
290 else if (argc == 4)
291 {
292 int i;
293
294 for( i=0; i<4; i++ )
295 {
296 int start = (0 == strncmp( args[i], "0x", 2 )) ? 2 : 0;
297 if (1 != sscanf( &args[i][start], "%x", &flashKeys[i] ))
298 {
299 command_print( cmd_ctx, "could not process flash key %s", args[i] );
300 ERROR( "could not process flash key %s", args[i] );
301 return ERROR_INVALID_ARGUMENTS;
302 }
303 }
304
305 keysSet = 1;
306 }
307 else if (argc != 0)
308 {
309 command_print( cmd_ctx, "tms470 flash_keyset <key0> <key1> <key2> <key3>" );
310 return ERROR_INVALID_ARGUMENTS;
311 }
312
313 if (keysSet)
314 {
315 command_print( cmd_ctx, "using flash keys 0x%08x, 0x%08x, 0x%08x, 0x%08x",
316 flashKeys[0], flashKeys[1], flashKeys[2], flashKeys[3] );
317 }
318 else
319 {
320 command_print( cmd_ctx, "flash keys not set" );
321 }
322
323 return ERROR_OK;
324 }
325
326 const u32 FLASH_KEYS_ALL_ONES[] = { 0xFFFFFFFF, 0xFFFFFFFF,
327 0xFFFFFFFF, 0xFFFFFFFF, };
328
329 const u32 FLASH_KEYS_ALL_ZEROS[] = { 0x00000000, 0x00000000,
330 0x00000000, 0x00000000, };
331
332 const u32 FLASH_KEYS_MIX1[] = { 0xf0fff0ff, 0xf0fff0ff,
333 0xf0fff0ff, 0xf0fff0ff };
334
335 const u32 FLASH_KEYS_MIX2[] = { 0x0000ffff, 0x0000ffff,
336 0x0000ffff, 0x0000ffff };
337
338 /* ---------------------------------------------------------------------- */
339
340 int oscMHz = 12;
341
342 int
343 tms470_handle_osc_megahertz_command( struct command_context_s * cmd_ctx,
344 char * cmd,
345 char ** args,
346 int argc )
347 {
348 if (argc > 1)
349 {
350 command_print( cmd_ctx, "tms470 osc_megahertz <MHz>" );
351 return ERROR_INVALID_ARGUMENTS;
352 }
353 else if (argc == 1)
354 {
355 sscanf( args[0], "%d", &oscMHz );
356 }
357
358 if (oscMHz <= 0)
359 {
360 ERROR( "osc_megahertz must be positive and non-zero!" );
361 command_print( cmd_ctx, "osc_megahertz must be positive and non-zero!" );
362 oscMHz = 12;
363 return ERROR_INVALID_ARGUMENTS;
364 }
365
366 command_print( cmd_ctx, "osc_megahertz=%d", oscMHz );
367
368 return ERROR_OK;
369 }
370
371 /* ---------------------------------------------------------------------- */
372
373 int plldis = 0;
374
375 int
376 tms470_handle_plldis_command( struct command_context_s * cmd_ctx,
377 char * cmd,
378 char ** args,
379 int argc )
380 {
381 if (argc > 1)
382 {
383 command_print( cmd_ctx, "tms470 plldis <0|1>" );
384 return ERROR_INVALID_ARGUMENTS;
385 }
386 else if (argc == 1)
387 {
388 sscanf( args[0], "%d", &plldis );
389 plldis = plldis ? 1 : 0;
390 }
391
392 command_print( cmd_ctx, "plldis=%d", plldis );
393
394 return ERROR_OK;
395 }
396
397 /* ---------------------------------------------------------------------- */
398
399 int
400 tms470_check_flash_unlocked( target_t * target )
401 {
402 u32 fmbbusy;
403
404 target_read_u32( target, 0xFFE89C08, &fmbbusy );
405 INFO( "tms470 fmbbusy=0x%08x -> %s",
406 fmbbusy,
407 fmbbusy & 0x8000 ? "unlocked" : "LOCKED" );
408 return fmbbusy & 0x8000 ? ERROR_OK : ERROR_FLASH_OPERATION_FAILED;
409 }
410
411 /* ---------------------------------------------------------------------- */
412
413 int
414 tms470_try_flash_keys( target_t * target,
415 const u32 * key_set )
416 {
417 u32 glbctrl, fmmstat;
418 int retval = ERROR_FLASH_OPERATION_FAILED;
419
420 /* set GLBCTRL.4 */
421 target_read_u32( target, 0xFFFFFFDC, &glbctrl );
422 target_write_u32( target, 0xFFFFFFDC, glbctrl | 0x10 );
423
424 /* only perform the key match when 3VSTAT is clear */
425 target_read_u32( target, 0xFFE8BC0C, &fmmstat );
426 if (!(fmmstat & 0x08))
427 {
428 unsigned i;
429 u32 fmmac2, fmbptr, fmbac2, fmbbusy, orig_fmregopt;
430
431 target_write_u32( target, 0xFFE8BC04, fmmstat & ~0x07 );
432
433 /* wait for pump ready */
434 do
435 {
436 target_read_u32( target, 0xFFE8A814, &fmbptr );
437 usleep( 1000 );
438 }
439 while( !(fmbptr & 0x0200) );
440
441 /* force max wait states */
442 target_read_u32( target, 0xFFE88004, &fmbac2 );
443 target_write_u32( target, 0xFFE88004, fmbac2 | 0xff );
444
445 /* save current access mode, force normal read mode */
446 target_read_u32( target, 0xFFE89C00, &orig_fmregopt );
447 target_write_u32( target, 0xFFE89C00, 0x00 );
448
449 for( i=0; i<4; i++ )
450 {
451 u32 tmp;
452
453 /* There is no point displaying the value of tmp, it is
454 * filtered by the chip. The purpose of this read is to
455 * prime the unlocking logic rather than read out the value.
456 */
457 target_read_u32( target, 0x00001FF0+4*i, &tmp );
458
459 INFO( "tms470 writing fmpkey=0x%08x", key_set[i] );
460 target_write_u32( target, 0xFFE89C0C, key_set[i] );
461 }
462
463 if (ERROR_OK == tms470_check_flash_unlocked( target ))
464 {
465 /*
466 * There seems to be a side-effect of reading the FMPKEY
467 * register in that it re-enables the protection. So we
468 * re-enable it.
469 */
470 for( i=0; i<4; i++ )
471 {
472 u32 tmp;
473 target_read_u32( target, 0x00001FF0+4*i, &tmp );
474 target_write_u32( target, 0xFFE89C0C, key_set[i] );
475 }
476 retval = ERROR_OK;
477 }
478
479 /* restore settings */
480 target_write_u32( target, 0xFFE89C00, orig_fmregopt );
481 target_write_u32( target, 0xFFE88004, fmbac2 );
482 }
483
484 /* clear config bit */
485 target_write_u32( target, 0xFFFFFFDC, glbctrl );
486
487 return retval;
488 }
489
490 /* ---------------------------------------------------------------------- */
491
492 int
493 tms470_unlock_flash( struct flash_bank_s * bank )
494 {
495 tms470_flash_bank_t * tms470_info = bank->driver_priv;
496 target_t * target = bank->target;
497 const u32 * p_key_sets[5];
498 unsigned i, key_set_count;
499
500 if (keysSet)
501 {
502 p_key_sets[0] = flashKeys;
503 p_key_sets[1] = FLASH_KEYS_ALL_ONES;
504 p_key_sets[2] = FLASH_KEYS_ALL_ZEROS;
505 p_key_sets[3] = FLASH_KEYS_MIX1;
506 p_key_sets[4] = FLASH_KEYS_MIX2;
507 }
508 else
509 {
510 key_set_count = 4;
511 p_key_sets[0] = FLASH_KEYS_ALL_ONES;
512 p_key_sets[1] = FLASH_KEYS_ALL_ZEROS;
513 p_key_sets[2] = FLASH_KEYS_MIX1;
514 p_key_sets[3] = FLASH_KEYS_MIX2;
515 }
516
517 for( i=0; i<key_set_count; i++ )
518 {
519 if (tms470_try_flash_keys( target, p_key_sets[i] ) == ERROR_OK)
520 {
521 INFO( "tms470 flash is unlocked" );
522 return ERROR_OK;
523 }
524 }
525
526 WARNING( "tms470 could not unlock flash memory protection level 2" );
527 return ERROR_FLASH_OPERATION_FAILED;
528 }
529
530 /* ---------------------------------------------------------------------- */
531
532 int
533 tms470_flash_initialize_internal_state_machine( struct flash_bank_s * bank )
534 {
535 u32 fmmac2, fmmac1, fmmaxep, k, delay, glbctrl, sysclk;
536 target_t *target = bank->target;
537 tms470_flash_bank_t * tms470_info = bank->driver_priv;
538 int result = ERROR_OK;
539
540 /*
541 * Select the desired bank to be programmed by writing BANK[2:0] of
542 * FMMAC2.
543 */
544 target_read_u32( target, 0xFFE8BC04, &fmmac2 );
545 fmmac2 &= ~0x0007;
546 fmmac2 |= (tms470_info->ordinal & 7);
547 target_write_u32( target, 0xFFE8BC04, fmmac2 );
548 DEBUG( "set fmmac2=0x%04x", fmmac2 );
549
550 /*
551 * Disable level 1 sector protection by setting bit 15 of FMMAC1.
552 */
553 target_read_u32( target, 0xFFE8BC00, &fmmac1 );
554 fmmac1 |= 0x8000;
555 target_write_u32( target, 0xFFE8BC00, fmmac1 );
556 DEBUG( "set fmmac1=0x%04x", fmmac1 );
557
558 /*
559 * FMTCREG=0x2fc0;
560 */
561 target_write_u32( target, 0xFFE8BC10, 0x2fc0 );
562 DEBUG( "set fmtcreg=0x2fc0" );
563
564 /*
565 * MAXPP=50
566 */
567 target_write_u32( target, 0xFFE8A07C, 50 );
568 DEBUG( "set fmmaxpp=50" );
569
570 /*
571 * MAXCP=0xf000+2000
572 */
573 target_write_u32( target, 0xFFE8A084, 0xf000+2000 );
574 DEBUG( "set fmmaxcp=0x%04x", 0xf000+2000 );
575
576 /*
577 * configure VHV
578 */
579 target_read_u32( target, 0xFFE8A080, &fmmaxep );
580 if (fmmaxep == 0xf000)
581 {
582 fmmaxep = 0xf000+4095;
583 target_write_u32( target, 0xFFE8A80C, 0x9964 );
584 DEBUG( "set fmptr3=0x9964" );
585 }
586 else
587 {
588 fmmaxep = 0xa000+4095;
589 target_write_u32( target, 0xFFE8A80C, 0x9b64 );
590 DEBUG( "set fmptr3=0x9b64" );
591 }
592 target_write_u32( target, 0xFFE8A080, fmmaxep );
593 DEBUG( "set fmmaxep=0x%04x", fmmaxep );
594
595 /*
596 * FMPTR4=0xa000
597 */
598 target_write_u32( target, 0xFFE8A810, 0xa000 );
599 DEBUG( "set fmptr4=0xa000" );
600
601 /*
602 * FMPESETUP, delay parameter selected based on clock frequency.
603 *
604 * According to the TI App Note SPNU257 and flashing code, delay is
605 * int((sysclk(MHz) + 1) / 2), with a minimum of 5. The system
606 * clock is usually derived from the ZPLL module, and selected by
607 * the plldis global.
608 */
609 target_read_u32( target, 0xFFFFFFDC, &glbctrl );
610 sysclk = (plldis ? 1 : (glbctrl & 0x08) ? 4 : 8 ) * oscMHz / (1 + (glbctrl & 7));
611 delay = (sysclk > 10) ? (sysclk + 1) / 2 : 5;
612 target_write_u32( target, 0xFFE8A018, (delay<<4)|(delay<<8) );
613 DEBUG( "set fmpsetup=0x%04x", (delay<<4)|(delay<<8) );
614
615 /*
616 * FMPVEVACCESS, based on delay.
617 */
618 k = delay|(delay<<8);
619 target_write_u32( target, 0xFFE8A05C, k );
620 DEBUG( "set fmpvevaccess=0x%04x", k );
621
622 /*
623 * FMPCHOLD, FMPVEVHOLD, FMPVEVSETUP, based on delay.
624 */
625 k <<= 1;
626 target_write_u32( target, 0xFFE8A034, k );
627 DEBUG( "set fmpchold=0x%04x", k );
628 target_write_u32( target, 0xFFE8A040, k );
629 DEBUG( "set fmpvevhold=0x%04x", k );
630 target_write_u32( target, 0xFFE8A024, k );
631 DEBUG( "set fmpvevsetup=0x%04x", k );
632
633 /*
634 * FMCVACCESS, based on delay.
635 */
636 k = delay*16;
637 target_write_u32( target, 0xFFE8A060, k );
638 DEBUG( "set fmcvaccess=0x%04x", k );
639
640 /*
641 * FMCSETUP, based on delay.
642 */
643 k = 0x3000 | delay*20;
644 target_write_u32( target, 0xFFE8A020, k );
645 DEBUG( "set fmcsetup=0x%04x", k );
646
647 /*
648 * FMEHOLD, based on delay.
649 */
650 k = (delay*20) << 2;
651 target_write_u32( target, 0xFFE8A038, k );
652 DEBUG( "set fmehold=0x%04x", k );
653
654 /*
655 * PWIDTH, CWIDTH, EWIDTH, based on delay.
656 */
657 target_write_u32( target, 0xFFE8A050, delay*8 );
658 DEBUG( "set fmpwidth=0x%04x", delay*8 );
659 target_write_u32( target, 0xFFE8A058, delay*1000 );
660 DEBUG( "set fmcwidth=0x%04x", delay*1000 );
661 target_write_u32( target, 0xFFE8A054, delay*5400 );
662 DEBUG( "set fmewidth=0x%04x", delay*5400 );
663
664 return result;
665 }
666
667
668 /* ---------------------------------------------------------------------- */
669
670 int
671 tms470_flash_status( struct flash_bank_s * bank )
672 {
673 target_t *target = bank->target;
674 int result = ERROR_OK;
675 u32 fmmstat;
676
677 target_read_u32( target, 0xFFE8BC0C, &fmmstat );
678 DEBUG( "set fmmstat=0x%04x", fmmstat );
679
680 if (fmmstat & 0x0080)
681 {
682 WARNING( "tms470 flash command: erase still active after busy clear." );
683 result = ERROR_FLASH_OPERATION_FAILED;
684 }
685
686 if (fmmstat & 0x0040)
687 {
688 WARNING( "tms470 flash command: program still active after busy clear." );
689 result = ERROR_FLASH_OPERATION_FAILED;
690 }
691
692 if (fmmstat & 0x0020)
693 {
694 WARNING( "tms470 flash command: invalid data command." );
695 result = ERROR_FLASH_OPERATION_FAILED;
696 }
697
698 if (fmmstat & 0x0010)
699 {
700 WARNING( "tms470 flash command: program, erase or validate sector failed." );
701 result = ERROR_FLASH_OPERATION_FAILED;
702 }
703
704 if (fmmstat & 0x0008)
705 {
706 WARNING( "tms470 flash command: voltage instability detected." );
707 result = ERROR_FLASH_OPERATION_FAILED;
708 }
709
710 if (fmmstat & 0x0006)
711 {
712 WARNING( "tms470 flash command: command suspend detected." );
713 result = ERROR_FLASH_OPERATION_FAILED;
714 }
715
716 if (fmmstat & 0x0001)
717 {
718 WARNING( "tms470 flash command: sector was locked." );
719 result = ERROR_FLASH_OPERATION_FAILED;
720 }
721
722 return result;
723 }
724
725 /* ---------------------------------------------------------------------- */
726
727 int
728 tms470_erase_sector( struct flash_bank_s * bank,
729 int sector )
730 {
731 u32 glbctrl, orig_fmregopt, fmbsea, fmbseb, fmmstat;
732 target_t *target = bank->target;
733 u32 flashAddr = bank->base + bank->sectors[sector].offset;
734 int result = ERROR_OK;
735
736 /*
737 * Set the bit GLBCTRL4 of the GLBCTRL register (in the System
738 * module) to enable writing to the flash registers }.
739 */
740 target_read_u32( target, 0xFFFFFFDC, &glbctrl );
741 target_write_u32( target, 0xFFFFFFDC, glbctrl | 0x10 );
742 DEBUG( "set glbctrl=0x%08x", glbctrl | 0x10 );
743
744 /* Force normal read mode. */
745 target_read_u32( target, 0xFFE89C00, &orig_fmregopt );
746 target_write_u32( target, 0xFFE89C00, 0 );
747 DEBUG( "set fmregopt=0x%08x", 0 );
748
749 (void) tms470_flash_initialize_internal_state_machine( bank );
750
751 /*
752 * Select one or more bits in FMBSEA or FMBSEB to disable Level 1
753 * protection for the particular sector to be erased/written.
754 */
755 if (sector < 16)
756 {
757 target_read_u32( target, 0xFFE88008, &fmbsea );
758 target_write_u32( target, 0xFFE88008, fmbsea | (1<<sector) );
759 DEBUG( "set fmbsea=0x%04x", fmbsea | (1<<sector) );
760 }
761 else
762 {
763 target_read_u32( target, 0xFFE8800C, &fmbseb );
764 target_write_u32( target, 0xFFE8800C, fmbseb | (1<<(sector-16)) );
765 DEBUG( "set fmbseb=0x%04x", fmbseb | (1<<(sector-16)) );
766 }
767 bank->sectors[sector].is_protected = 0;
768
769 /*
770 * clear status regiser, sent erase command, kickoff erase
771 */
772 target_write_u16( target, flashAddr, 0x0040 );
773 DEBUG( "write *(u16 *)0x%08x=0x0040", flashAddr );
774 target_write_u16( target, flashAddr, 0x0020 );
775 DEBUG( "write *(u16 *)0x%08x=0x0020", flashAddr );
776 target_write_u16( target, flashAddr, 0xffff );
777 DEBUG( "write *(u16 *)0x%08x=0xffff", flashAddr );
778
779 /*
780 * Monitor FMMSTAT, busy until clear, then check and other flags for
781 * ultimate result of the operation.
782 */
783 do
784 {
785 target_read_u32( target, 0xFFE8BC0C, &fmmstat );
786 if (fmmstat & 0x0100)
787 {
788 usleep( 1000 );
789 }
790 }
791 while( fmmstat & 0x0100 );
792
793 result = tms470_flash_status( bank );
794
795 if (sector < 16)
796 {
797 target_write_u32( target, 0xFFE88008, fmbsea );
798 DEBUG( "set fmbsea=0x%04x", fmbsea );
799 bank->sectors[sector].is_protected =
800 fmbsea & (1<<sector) ? 0 : 1;
801 }
802 else
803 {
804 target_write_u32( target, 0xFFE8800C, fmbseb );
805 DEBUG( "set fmbseb=0x%04x", fmbseb );
806 bank->sectors[sector].is_protected =
807 fmbseb & (1<<(sector-16)) ? 0 : 1;
808 }
809 target_write_u32( target, 0xFFE89C00, orig_fmregopt );
810 DEBUG( "set fmregopt=0x%08x", orig_fmregopt );
811 target_write_u32( target, 0xFFFFFFDC, glbctrl );
812 DEBUG( "set glbctrl=0x%08x", glbctrl );
813
814 if (result == ERROR_OK)
815 {
816 bank->sectors[sector].is_erased = 1;
817 }
818
819 return result;
820 }
821
822 /* ----------------------------------------------------------------------
823 Implementation of Flash Driver Interfaces
824 ---------------------------------------------------------------------- */
825
826 int
827 tms470_register_commands( struct command_context_s *cmd_ctx )
828 {
829 command_t *tms470_cmd = register_command( cmd_ctx,
830 NULL,
831 "tms470",
832 NULL,
833 COMMAND_ANY,
834 "applies to TI tms470 family" );
835
836 register_command( cmd_ctx,
837 tms470_cmd,
838 "flash_keyset",
839 tms470_handle_flash_keyset_command,
840 COMMAND_ANY,
841 "tms470 flash_keyset <key0> <key1> <key2> <key3>" );
842
843 register_command( cmd_ctx,
844 tms470_cmd,
845 "osc_megahertz",
846 tms470_handle_osc_megahertz_command,
847 COMMAND_ANY,
848 "tms470 osc_megahertz <MHz>" );
849
850 register_command( cmd_ctx,
851 tms470_cmd,
852 "plldis",
853 tms470_handle_plldis_command,
854 COMMAND_ANY,
855 "tms470 plldis <0/1>" );
856
857 return ERROR_OK;
858 }
859
860 /* ---------------------------------------------------------------------- */
861
862 int
863 tms470_erase( struct flash_bank_s * bank,
864 int first,
865 int last )
866 {
867 tms470_flash_bank_t *tms470_info = bank->driver_priv;
868 target_t *target = bank->target;
869 int sector, result = ERROR_OK;
870
871 if (!tms470_info->device_ident_reg)
872 {
873 tms470_read_part_info( bank );
874 }
875
876 if ((first < 0) ||
877 (first >= bank->num_sectors) ||
878 (last < 0) ||
879 (last >= bank->num_sectors) ||
880 (first > last))
881 {
882 ERROR( "Sector range %d to %d invalid.", first, last );
883 return ERROR_FLASH_SECTOR_INVALID;
884 }
885
886 result = tms470_unlock_flash( bank );
887 if (result != ERROR_OK)
888 {
889 return result;
890 }
891
892 for( sector=first; sector<=last; sector++ )
893 {
894 INFO( "Erasing tms470 bank %d sector %d...",
895 tms470_info->ordinal, sector );
896
897 result = tms470_erase_sector( bank, sector );
898
899 if (result != ERROR_OK)
900 {
901 ERROR( "tms470 could not erase flash sector." );
902 break;
903 }
904 else
905 {
906 INFO( "sector erased successfully." );
907 }
908 }
909
910 return result;
911 }
912
913 /* ---------------------------------------------------------------------- */
914
915 int
916 tms470_protect( struct flash_bank_s * bank,
917 int set,
918 int first,
919 int last )
920 {
921 tms470_flash_bank_t *tms470_info = bank->driver_priv;
922 target_t *target = bank->target;
923 u32 fmmac2, fmbsea, fmbseb;
924 int sector;
925
926 if (!tms470_info->device_ident_reg)
927 {
928 tms470_read_part_info( bank );
929 }
930
931 if ((first < 0) ||
932 (first >= bank->num_sectors) ||
933 (last < 0) ||
934 (last >= bank->num_sectors) ||
935 (first > last))
936 {
937 ERROR( "Sector range %d to %d invalid.", first, last );
938 return ERROR_FLASH_SECTOR_INVALID;
939 }
940
941 /* enable the appropriate bank */
942 target_read_u32( target, 0xFFE8BC04, &fmmac2 );
943 target_write_u32( target, 0xFFE8BC04,
944 (fmmac2 & ~7) | tms470_info->ordinal );
945
946 /* get the original sector proection flags for this bank */
947 target_read_u32( target, 0xFFE88008, &fmbsea );
948 target_read_u32( target, 0xFFE8800C, &fmbseb );
949
950 for( sector=0; sector<bank->num_sectors; sector++ )
951 {
952 if (sector < 16)
953 {
954 fmbsea = set ? fmbsea & ~(1<<sector) :
955 fmbsea | (1<<sector);
956 bank->sectors[sector].is_protected = set ? 1 : 0;
957 }
958 else
959 {
960 fmbseb = set ? fmbseb & ~(1<<(sector-16)) :
961 fmbseb | (1<<(sector-16));
962 bank->sectors[sector].is_protected = set ? 1 : 0;
963 }
964 }
965
966 /* update the protection bits */
967 target_write_u32( target, 0xFFE88008, fmbsea );
968 target_write_u32( target, 0xFFE8800C, fmbseb );
969
970 return ERROR_OK;
971 }
972
973 /* ---------------------------------------------------------------------- */
974
975 int
976 tms470_write( struct flash_bank_s * bank,
977 u8 * buffer,
978 u32 offset,
979 u32 count )
980 {
981 target_t *target = bank->target;
982 tms470_flash_bank_t *tms470_info = bank->driver_priv;
983 u32 glbctrl, fmbac2, orig_fmregopt, fmbsea, fmbseb, fmmaxpp, fmmstat;
984 int i, result = ERROR_OK;
985
986 if (!tms470_info->device_ident_reg)
987 {
988 tms470_read_part_info( bank );
989 }
990
991 INFO( "Writing %d bytes starting at 0x%08x",
992 count, bank->base + offset );
993
994 /* set GLBCTRL.4 */
995 target_read_u32( target, 0xFFFFFFDC, &glbctrl );
996 target_write_u32( target, 0xFFFFFFDC, glbctrl | 0x10 );
997
998 (void) tms470_flash_initialize_internal_state_machine( bank );
999
1000 /* force max wait states */
1001 target_read_u32( target, 0xFFE88004, &fmbac2 );
1002 target_write_u32( target, 0xFFE88004, fmbac2 | 0xff );
1003
1004 /* save current access mode, force normal read mode */
1005 target_read_u32( target, 0xFFE89C00, &orig_fmregopt );
1006 target_write_u32( target, 0xFFE89C00, 0x00 );
1007
1008 /*
1009 * Disable Level 1 protection for all sectors to be erased/written.
1010 */
1011 target_read_u32( target, 0xFFE88008, &fmbsea );
1012 target_write_u32( target, 0xFFE88008, 0xffff );
1013 target_read_u32( target, 0xFFE8800C, &fmbseb );
1014 target_write_u32( target, 0xFFE8800C, 0xffff );
1015
1016 /* read MAXPP */
1017 target_read_u32( target, 0xFFE8A07C, &fmmaxpp );
1018
1019 for( i=0; i<count; i+=2 )
1020 {
1021 u32 addr = bank->base + offset + i;
1022 u16 word = (((u16) buffer[i]) << 8) | (u16) buffer[i+1];
1023
1024 if (word != 0xffff)
1025 {
1026 INFO( "writing 0x%04x at 0x%08x", word, addr );
1027
1028 /* clear status register */
1029 target_write_u16( target, addr, 0x0040 );
1030 /* program flash command */
1031 target_write_u16( target, addr, 0x0010 );
1032 /* burn the 16-bit word (big-endian) */
1033 target_write_u16( target, addr, word );
1034
1035 /*
1036 * Monitor FMMSTAT, busy until clear, then check and other flags
1037 * for ultimate result of the operation.
1038 */
1039 do
1040 {
1041 target_read_u32( target, 0xFFE8BC0C, &fmmstat );
1042 if (fmmstat & 0x0100)
1043 {
1044 usleep( 1000 );
1045 }
1046 }
1047 while( fmmstat & 0x0100 );
1048
1049 if (fmmstat & 0x3ff)
1050 {
1051 ERROR( "fmstat=0x%04x", fmmstat );
1052 ERROR( "Could not program word 0x%04x at address 0x%08x.",
1053 word, addr );
1054 result = ERROR_FLASH_OPERATION_FAILED;
1055 break;
1056 }
1057 }
1058 else
1059 {
1060 INFO( "skipping 0xffff at 0x%08x", addr );
1061 }
1062 }
1063
1064 /* restore */
1065 target_write_u32( target, 0xFFE88008, fmbsea );
1066 target_write_u32( target, 0xFFE8800C, fmbseb );
1067 target_write_u32( target, 0xFFE88004, fmbac2 );
1068 target_write_u32( target, 0xFFE89C00, orig_fmregopt );
1069 target_write_u32( target, 0xFFFFFFDC, glbctrl );
1070
1071 return result;
1072 }
1073
1074 /* ---------------------------------------------------------------------- */
1075
1076 int
1077 tms470_probe( struct flash_bank_s * bank )
1078 {
1079 tms470_flash_bank_t * tms470_info = bank->driver_priv;
1080
1081 if (!tms470_info->device_ident_reg)
1082 {
1083 tms470_read_part_info( bank );
1084 }
1085
1086 return ERROR_OK;
1087 }
1088
1089 /* ---------------------------------------------------------------------- */
1090
1091 int
1092 tms470_erase_check( struct flash_bank_s * bank )
1093 {
1094 target_t *target = bank->target;
1095 tms470_flash_bank_t * tms470_info = bank->driver_priv;
1096 int sector, result = ERROR_OK;
1097 u32 fmmac2, fmbac2, glbctrl, orig_fmregopt;
1098 static u8 buffer[64*1024];
1099
1100 if (!tms470_info->device_ident_reg)
1101 {
1102 tms470_read_part_info( bank );
1103 }
1104
1105 /* set GLBCTRL.4 */
1106 target_read_u32( target, 0xFFFFFFDC, &glbctrl );
1107 target_write_u32( target, 0xFFFFFFDC, glbctrl | 0x10 );
1108
1109 /* save current access mode, force normal read mode */
1110 target_read_u32( target, 0xFFE89C00, &orig_fmregopt );
1111 target_write_u32( target, 0xFFE89C00, 0x00 );
1112
1113 /* enable the appropriate bank */
1114 target_read_u32( target, 0xFFE8BC04, &fmmac2 );
1115 target_write_u32( target, 0xFFE8BC04,
1116 (fmmac2 & ~7) | tms470_info->ordinal );
1117
1118 /* TCR=0 */
1119 target_write_u32( target, 0xFFE8BC10, 0x2fc0 );
1120
1121 /* clear TEZ in fmbrdy */
1122 target_write_u32( target, 0xFFE88010, 0x0b );
1123
1124 /* save current wait states, force max */
1125 target_read_u32( target, 0xFFE88004, &fmbac2 );
1126 target_write_u32( target, 0xFFE88004, fmbac2 | 0xff );
1127
1128 /*
1129 * The TI primitives inspect the flash memory by reading one 32-bit
1130 * word at a time. Here we read an entire sector and inspect it in
1131 * an attempt to reduce the JTAG overhead.
1132 */
1133 for( sector=0; sector<bank->num_sectors; sector++ )
1134 {
1135 if (bank->sectors[sector].is_erased != 1)
1136 {
1137 u32 i, addr = bank->base + bank->sectors[sector].offset;
1138
1139 INFO( "checking flash bank %d sector %d",
1140 tms470_info->ordinal,
1141 sector );
1142
1143 target_read_buffer( target,
1144 addr,
1145 bank->sectors[sector].size,
1146 buffer );
1147
1148 bank->sectors[sector].is_erased = 1;
1149 for( i=0; i<bank->sectors[sector].size; i++ )
1150 {
1151 if (buffer[i] != 0xff)
1152 {
1153 WARNING( "tms470 bank %d, sector %d, not erased.",
1154 tms470_info->ordinal,
1155 sector );
1156 WARNING( "at location 0x%08x: flash data is 0x%02x.",
1157 addr+i,
1158 buffer[i] );
1159
1160 bank->sectors[sector].is_erased = 0;
1161 break;
1162 }
1163 }
1164 }
1165 if (bank->sectors[sector].is_erased != 1)
1166 {
1167 result = ERROR_FLASH_SECTOR_NOT_ERASED;
1168 break;
1169 }
1170 else
1171 {
1172 INFO( "sector erased" );
1173 }
1174 }
1175
1176 /* reset TEZ, wait states, read mode, GLBCTRL.4 */
1177 target_write_u32( target, 0xFFE88010, 0x0f );
1178 target_write_u32( target, 0xFFE88004, fmbac2 );
1179 target_write_u32( target, 0xFFE89C00, orig_fmregopt );
1180 target_write_u32( target, 0xFFFFFFDC, glbctrl );
1181
1182 return result;
1183 }
1184
1185 /* ---------------------------------------------------------------------- */
1186
1187 int
1188 tms470_protect_check( struct flash_bank_s * bank )
1189 {
1190 target_t *target = bank->target;
1191 tms470_flash_bank_t * tms470_info = bank->driver_priv;
1192 int sector, result = ERROR_OK;
1193 u32 fmmac2, fmbsea, fmbseb;
1194
1195 if (!tms470_info->device_ident_reg)
1196 {
1197 tms470_read_part_info( bank );
1198 }
1199
1200 /* enable the appropriate bank */
1201 target_read_u32( target, 0xFFE8BC04, &fmmac2 );
1202 target_write_u32( target, 0xFFE8BC04,
1203 (fmmac2 & ~7) | tms470_info->ordinal );
1204
1205 target_read_u32( target, 0xFFE88008, &fmbsea );
1206 target_read_u32( target, 0xFFE8800C, &fmbseb );
1207
1208 for( sector=0; sector<bank->num_sectors; sector++ )
1209 {
1210 int protected;
1211
1212 if (sector < 16)
1213 {
1214 protected = fmbsea & (1<<sector) ? 0 : 1;
1215 bank->sectors[sector].is_protected = protected;
1216 }
1217 else
1218 {
1219 protected = fmbseb & (1<<(sector-16)) ? 0 : 1;
1220 bank->sectors[sector].is_protected = protected;
1221 }
1222
1223 DEBUG( "bank %d sector %d is %s",
1224 tms470_info->ordinal,
1225 sector,
1226 protected ? "protected" : "not protected" );
1227 }
1228
1229 return result;
1230 }
1231
1232 /* ---------------------------------------------------------------------- */
1233
1234 int
1235 tms470_info( struct flash_bank_s * bank,
1236 char * buf,
1237 int buf_size )
1238 {
1239 int used = 0;
1240 tms470_flash_bank_t * tms470_info = bank->driver_priv;
1241
1242 if (!tms470_info->device_ident_reg)
1243 {
1244 tms470_read_part_info( bank );
1245 }
1246
1247 if (!tms470_info->device_ident_reg)
1248 {
1249 (void) snprintf(buf, buf_size, "Cannot identify target as a TMS470\n");
1250 return ERROR_FLASH_OPERATION_FAILED;
1251 }
1252
1253 used += snprintf( buf, buf_size,
1254 "\ntms470 information: Chip is %s\n",
1255 tms470_info->part_name );
1256 buf += used;
1257 buf_size -= used;
1258
1259 used += snprintf( buf, buf_size,
1260 "Flash protection level 2 is %s\n",
1261 tms470_check_flash_unlocked( bank->target ) == ERROR_OK ? "disabled" : "enabled" );
1262 buf += used;
1263 buf_size -= used;
1264
1265 return ERROR_OK;
1266 }
1267
1268 /* ---------------------------------------------------------------------- */
1269
1270 /*
1271 * flash bank tms470 <base> <size> <chip_width> <bus_width> <target>
1272 * [options...]
1273 */
1274
1275 int
1276 tms470_flash_bank_command( struct command_context_s *cmd_ctx,
1277 char *cmd,
1278 char **args,
1279 int argc,
1280 struct flash_bank_s *bank )
1281 {
1282 bank->driver_priv = malloc( sizeof( tms470_flash_bank_t ) );
1283
1284 if (!bank->driver_priv)
1285 {
1286 return ERROR_FLASH_OPERATION_FAILED;
1287 }
1288
1289 (void) memset( bank->driver_priv, 0, sizeof( tms470_flash_bank_t ) );
1290
1291 return ERROR_OK;
1292 }
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