src/jtag/aice/aice_port.h

   1 /***************************************************************************
   2  *   Copyright (C) 2013 by Andes Technology                                *
   3  *   Hsiangkai Wang <hkwang@andestech.com>                                 *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  17  ***************************************************************************/
  18
  19 #ifndef OPENOCD_JTAG_AICE_AICE_PORT_H
  20 #define OPENOCD_JTAG_AICE_AICE_PORT_H
  21
  22 #include <target/nds32_edm.h>
  23
  24 #define AICE_MAX_NUM_CORE      (0x10)
  25
  26 #define ERROR_AICE_DISCONNECT  (-200)
  27 #define ERROR_AICE_TIMEOUT     (-201)
  28
  29 enum aice_target_state_s {
  30         AICE_DISCONNECT = 0,
  31         AICE_TARGET_DETACH,
  32         AICE_TARGET_UNKNOWN,
  33         AICE_TARGET_RUNNING,
  34         AICE_TARGET_HALTED,
  35         AICE_TARGET_RESET,
  36         AICE_TARGET_DEBUG_RUNNING,
  37 };
  38
  39 enum aice_srst_type_s {
  40         AICE_SRST = 0x1,
  41         AICE_RESET_HOLD = 0x8,
  42 };
  43
  44 enum aice_target_endian {
  45         AICE_LITTLE_ENDIAN = 0,
  46         AICE_BIG_ENDIAN,
  47 };
  48
  49 enum aice_api_s {
  50         AICE_OPEN = 0x0,
  51         AICE_CLOSE,
  52         AICE_RESET,
  53         AICE_IDCODE,
  54         AICE_SET_JTAG_CLOCK,
  55         AICE_ASSERT_SRST,
  56         AICE_RUN,
  57         AICE_HALT,
  58         AICE_STEP,
  59         AICE_READ_REG,
  60         AICE_WRITE_REG,
  61         AICE_READ_REG_64,
  62         AICE_WRITE_REG_64,
  63         AICE_READ_MEM_UNIT,
  64         AICE_WRITE_MEM_UNIT,
  65         AICE_READ_MEM_BULK,
  66         AICE_WRITE_MEM_BULK,
  67         AICE_READ_DEBUG_REG,
  68         AICE_WRITE_DEBUG_REG,
  69         AICE_STATE,
  70         AICE_MEMORY_ACCESS,
  71         AICE_MEMORY_MODE,
  72         AICE_READ_TLB,
  73         AICE_CACHE_CTL,
  74         AICE_SET_RETRY_TIMES,
  75         AICE_PROGRAM_EDM,
  76         AICE_SET_COMMAND_MODE,
  77         AICE_EXECUTE,
  78         AICE_SET_CUSTOM_SRST_SCRIPT,
  79         AICE_SET_CUSTOM_TRST_SCRIPT,
  80         AICE_SET_CUSTOM_RESTART_SCRIPT,
  81         AICE_SET_COUNT_TO_CHECK_DBGER,
  82         AICE_SET_DATA_ENDIAN,
  83 };
  84
  85 enum aice_error_s {
  86         AICE_OK,
  87         AICE_ACK,
  88         AICE_ERROR,
  89 };
  90
  91 enum aice_cache_ctl_type {
  92         AICE_CACHE_CTL_L1D_INVALALL = 0,
  93         AICE_CACHE_CTL_L1D_VA_INVAL,
  94         AICE_CACHE_CTL_L1D_WBALL,
  95         AICE_CACHE_CTL_L1D_VA_WB,
  96         AICE_CACHE_CTL_L1I_INVALALL,
  97         AICE_CACHE_CTL_L1I_VA_INVAL,
  98 };
  99
 100 enum aice_command_mode {
 101         AICE_COMMAND_MODE_NORMAL,
 102         AICE_COMMAND_MODE_PACK,
 103         AICE_COMMAND_MODE_BATCH,
 104 };
 105
 106 struct aice_port_param_s {
 107         /** */
 108         const char *device_desc;
 109         /** */
 110         uint16_t vid;
 111         /** */
 112         uint16_t pid;
 113         /** */
 114         char *adapter_name;
 115 };
 116
 117 struct aice_port_s {
 118         /** */
 119         uint32_t coreid;
 120         /** */
 121         const struct aice_port *port;
 122 };
 123
 124 /** */
 125 extern struct aice_port_api_s aice_usb_layout_api;
 126
 127 /** */
 128 struct aice_port_api_s {
 129         /** */
 130         int (*open)(struct aice_port_param_s *param);
 131         /** */
 132         int (*close)(void);
 133         /** */
 134         int (*reset)(void);
 135         /** */
 136         int (*idcode)(uint32_t *idcode, uint8_t *num_of_idcode);
 137         /** */
 138         int (*set_jtag_clock)(uint32_t a_clock);
 139         /** */
 140         int (*assert_srst)(uint32_t coreid, enum aice_srst_type_s srst);
 141         /** */
 142         int (*run)(uint32_t coreid);
 143         /** */
 144         int (*halt)(uint32_t coreid);
 145         /** */
 146         int (*step)(uint32_t coreid);
 147         /** */
 148         int (*read_reg)(uint32_t coreid, uint32_t num, uint32_t *val);
 149         /** */
 150         int (*write_reg)(uint32_t coreid, uint32_t num, uint32_t val);
 151         /** */
 152         int (*read_reg_64)(uint32_t coreid, uint32_t num, uint64_t *val);
 153         /** */
 154         int (*write_reg_64)(uint32_t coreid, uint32_t num, uint64_t val);
 155         /** */
 156         int (*read_mem_unit)(uint32_t coreid, uint32_t addr, uint32_t size,
 157                         uint32_t count, uint8_t *buffer);
 158         /** */
 159         int (*write_mem_unit)(uint32_t coreid, uint32_t addr, uint32_t size,
 160                         uint32_t count, const uint8_t *buffer);
 161         /** */
 162         int (*read_mem_bulk)(uint32_t coreid, uint32_t addr, uint32_t length,
 163                         uint8_t *buffer);
 164         /** */
 165         int (*write_mem_bulk)(uint32_t coreid, uint32_t addr, uint32_t length,
 166                         const uint8_t *buffer);
 167         /** */
 168         int (*read_debug_reg)(uint32_t coreid, uint32_t addr, uint32_t *val);
 169         /** */
 170         int (*write_debug_reg)(uint32_t coreid, uint32_t addr, const uint32_t val);
 171
 172         /** */
 173         int (*state)(uint32_t coreid, enum aice_target_state_s *state);
 174
 175         /** */
 176         int (*memory_access)(uint32_t coreid, enum nds_memory_access a_access);
 177         /** */
 178         int (*memory_mode)(uint32_t coreid, enum nds_memory_select mem_select);
 179
 180         /** */
 181         int (*read_tlb)(uint32_t coreid, target_addr_t virtual_address, target_addr_t *physical_address);
 182
 183         /** */
 184         int (*cache_ctl)(uint32_t coreid, uint32_t subtype, uint32_t address);
 185
 186         /** */
 187         int (*set_retry_times)(uint32_t a_retry_times);
 188
 189         /** */
 190         int (*program_edm)(uint32_t coreid, char *command_sequence);
 191
 192         /** */
 193         int (*set_command_mode)(enum aice_command_mode command_mode);
 194
 195         /** */
 196         int (*execute)(uint32_t coreid, uint32_t *instructions, uint32_t instruction_num);
 197
 198         /** */
 199         int (*set_custom_srst_script)(const char *script);
 200
 201         /** */
 202         int (*set_custom_trst_script)(const char *script);
 203
 204         /** */
 205         int (*set_custom_restart_script)(const char *script);
 206
 207         /** */
 208         int (*set_count_to_check_dbger)(uint32_t count_to_check);
 209
 210         /** */
 211         int (*set_data_endian)(uint32_t coreid, enum aice_target_endian target_data_endian);
 212
 213         /** */
 214         int (*profiling)(uint32_t coreid, uint32_t interval, uint32_t iteration,
 215                 uint32_t reg_no, uint32_t *samples, uint32_t *num_samples);
 216 };
 217
 218 #define AICE_PORT_UNKNOWN       0
 219 #define AICE_PORT_AICE_USB      1
 220 #define AICE_PORT_AICE_PIPE     2
 221
 222 /** */
 223 struct aice_port {
 224         /** */
 225         const char *name;
 226         /** */
 227         int type;
 228         /** */
 229         struct aice_port_api_s *const api;
 230 };
 231
 232 /** */
 233 const struct aice_port *aice_port_get_list(void);
 234
 235 #endif /* OPENOCD_JTAG_AICE_AICE_PORT_H */