src/jtag/aice/aice_port.h

   1 /***************************************************************************
   2  *   Copyright (C) 2013 by Andes Technology                                *
   3  *   Hsiangkai Wang <hkwang@andestech.com>                                 *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  17  ***************************************************************************/
  18 #ifndef _AICE_PORT_H_
  19 #define _AICE_PORT_H_
  20
  21 #include <target/nds32_edm.h>
  22
  23 #define AICE_MAX_NUM_CORE      (0x10)
  24
  25 #define ERROR_AICE_DISCONNECT  (-200)
  26 #define ERROR_AICE_TIMEOUT     (-201)
  27
  28 enum aice_target_state_s {
  29         AICE_DISCONNECT = 0,
  30         AICE_TARGET_DETACH,
  31         AICE_TARGET_UNKNOWN,
  32         AICE_TARGET_RUNNING,
  33         AICE_TARGET_HALTED,
  34         AICE_TARGET_RESET,
  35         AICE_TARGET_DEBUG_RUNNING,
  36 };
  37
  38 enum aice_srst_type_s {
  39         AICE_SRST = 0x1,
  40         AICE_RESET_HOLD = 0x8,
  41 };
  42
  43 enum aice_target_endian {
  44         AICE_LITTLE_ENDIAN = 0,
  45         AICE_BIG_ENDIAN,
  46 };
  47
  48 enum aice_api_s {
  49         AICE_OPEN = 0x0,
  50         AICE_CLOSE,
  51         AICE_RESET,
  52         AICE_IDCODE,
  53         AICE_SET_JTAG_CLOCK,
  54         AICE_ASSERT_SRST,
  55         AICE_RUN,
  56         AICE_HALT,
  57         AICE_STEP,
  58         AICE_READ_REG,
  59         AICE_WRITE_REG,
  60         AICE_READ_REG_64,
  61         AICE_WRITE_REG_64,
  62         AICE_READ_MEM_UNIT,
  63         AICE_WRITE_MEM_UNIT,
  64         AICE_READ_MEM_BULK,
  65         AICE_WRITE_MEM_BULK,
  66         AICE_READ_DEBUG_REG,
  67         AICE_WRITE_DEBUG_REG,
  68         AICE_STATE,
  69         AICE_MEMORY_ACCESS,
  70         AICE_MEMORY_MODE,
  71         AICE_READ_TLB,
  72         AICE_CACHE_CTL,
  73         AICE_SET_RETRY_TIMES,
  74         AICE_PROGRAM_EDM,
  75         AICE_SET_COMMAND_MODE,
  76         AICE_EXECUTE,
  77         AICE_SET_CUSTOM_SRST_SCRIPT,
  78         AICE_SET_CUSTOM_TRST_SCRIPT,
  79         AICE_SET_CUSTOM_RESTART_SCRIPT,
  80         AICE_SET_COUNT_TO_CHECK_DBGER,
  81         AICE_SET_DATA_ENDIAN,
  82 };
  83
  84 enum aice_error_s {
  85         AICE_OK,
  86         AICE_ACK,
  87         AICE_ERROR,
  88 };
  89
  90 enum aice_cache_ctl_type {
  91         AICE_CACHE_CTL_L1D_INVALALL = 0,
  92         AICE_CACHE_CTL_L1D_VA_INVAL,
  93         AICE_CACHE_CTL_L1D_WBALL,
  94         AICE_CACHE_CTL_L1D_VA_WB,
  95         AICE_CACHE_CTL_L1I_INVALALL,
  96         AICE_CACHE_CTL_L1I_VA_INVAL,
  97 };
  98
  99 enum aice_command_mode {
 100         AICE_COMMAND_MODE_NORMAL,
 101         AICE_COMMAND_MODE_PACK,
 102         AICE_COMMAND_MODE_BATCH,
 103 };
 104
 105 struct aice_port_param_s {
 106         /** */
 107         const char *device_desc;
 108         /** */
 109         const char *serial;
 110         /** */
 111         uint16_t vid;
 112         /** */
 113         uint16_t pid;
 114         /** */
 115         char *adapter_name;
 116 };
 117
 118 struct aice_port_s {
 119         /** */
 120         uint32_t coreid;
 121         /** */
 122         const struct aice_port *port;
 123 };
 124
 125 /** */
 126 extern struct aice_port_api_s aice_usb_layout_api;
 127
 128 /** */
 129 struct aice_port_api_s {
 130         /** */
 131         int (*open)(struct aice_port_param_s *param);
 132         /** */
 133         int (*close)(void);
 134         /** */
 135         int (*reset)(void);
 136         /** */
 137         int (*idcode)(uint32_t *idcode, uint8_t *num_of_idcode);
 138         /** */
 139         int (*set_jtag_clock)(uint32_t a_clock);
 140         /** */
 141         int (*assert_srst)(uint32_t coreid, enum aice_srst_type_s srst);
 142         /** */
 143         int (*run)(uint32_t coreid);
 144         /** */
 145         int (*halt)(uint32_t coreid);
 146         /** */
 147         int (*step)(uint32_t coreid);
 148         /** */
 149         int (*read_reg)(uint32_t coreid, uint32_t num, uint32_t *val);
 150         /** */
 151         int (*write_reg)(uint32_t coreid, uint32_t num, uint32_t val);
 152         /** */
 153         int (*read_reg_64)(uint32_t coreid, uint32_t num, uint64_t *val);
 154         /** */
 155         int (*write_reg_64)(uint32_t coreid, uint32_t num, uint64_t val);
 156         /** */
 157         int (*read_mem_unit)(uint32_t coreid, uint32_t addr, uint32_t size,
 158                         uint32_t count, uint8_t *buffer);
 159         /** */
 160         int (*write_mem_unit)(uint32_t coreid, uint32_t addr, uint32_t size,
 161                         uint32_t count, const uint8_t *buffer);
 162         /** */
 163         int (*read_mem_bulk)(uint32_t coreid, uint32_t addr, uint32_t length,
 164                         uint8_t *buffer);
 165         /** */
 166         int (*write_mem_bulk)(uint32_t coreid, uint32_t addr, uint32_t length,
 167                         const uint8_t *buffer);
 168         /** */
 169         int (*read_debug_reg)(uint32_t coreid, uint32_t addr, uint32_t *val);
 170         /** */
 171         int (*write_debug_reg)(uint32_t coreid, uint32_t addr, const uint32_t val);
 172
 173         /** */
 174         int (*state)(uint32_t coreid, enum aice_target_state_s *state);
 175
 176         /** */
 177         int (*memory_access)(uint32_t coreid, enum nds_memory_access a_access);
 178         /** */
 179         int (*memory_mode)(uint32_t coreid, enum nds_memory_select mem_select);
 180
 181         /** */
 182         int (*read_tlb)(uint32_t coreid, uint32_t virtual_address, uint32_t *physical_address);
 183
 184         /** */
 185         int (*cache_ctl)(uint32_t coreid, uint32_t subtype, uint32_t address);
 186
 187         /** */
 188         int (*set_retry_times)(uint32_t a_retry_times);
 189
 190         /** */
 191         int (*program_edm)(uint32_t coreid, char *command_sequence);
 192
 193         /** */
 194         int (*set_command_mode)(enum aice_command_mode command_mode);
 195
 196         /** */
 197         int (*execute)(uint32_t coreid, uint32_t *instructions, uint32_t instruction_num);
 198
 199         /** */
 200         int (*set_custom_srst_script)(const char *script);
 201
 202         /** */
 203         int (*set_custom_trst_script)(const char *script);
 204
 205         /** */
 206         int (*set_custom_restart_script)(const char *script);
 207
 208         /** */
 209         int (*set_count_to_check_dbger)(uint32_t count_to_check);
 210
 211         /** */
 212         int (*set_data_endian)(uint32_t coreid, enum aice_target_endian target_data_endian);
 213
 214         /** */
 215         int (*profiling)(uint32_t coreid, uint32_t interval, uint32_t iteration,
 216                 uint32_t reg_no, uint32_t *samples, uint32_t *num_samples);
 217 };
 218
 219 #define AICE_PORT_UNKNOWN       0
 220 #define AICE_PORT_AICE_USB      1
 221 #define AICE_PORT_AICE_PIPE     2
 222
 223 /** */
 224 struct aice_port {
 225         /** */
 226         const char *name;
 227         /** */
 228         int type;
 229         /** */
 230         struct aice_port_api_s *const api;
 231 };
 232
 233 /** */
 234 const struct aice_port *aice_port_get_list(void);
 235
 236 #endif