1 /***************************************************************************
2 * Copyright (C) 2013 by Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
24 #include <jtag/drivers/libusb_common.h>
25 #include <helper/log.h>
26 #include <helper/time_support.h>
27 #include <target/target.h>
28 #include <jtag/jtag.h>
29 #include <target/nds32_insn.h>
30 #include <target/nds32_reg.h>
34 /* Global USB buffers */
35 static uint8_t usb_in_buffer
[AICE_IN_BUFFER_SIZE
];
36 static uint8_t usb_out_buffer
[AICE_OUT_BUFFER_SIZE
];
37 static uint32_t jtag_clock
;
38 static struct aice_usb_handler_s aice_handler
;
39 /* AICE max retry times. If AICE command timeout, retry it. */
40 static int aice_max_retry_times
= 50;
41 /* Default endian is little endian. */
42 static enum aice_target_endian data_endian
;
45 /***************************************************************************/
46 /* AICE commands' pack/unpack functions */
47 static void aice_pack_htda(uint8_t cmd_code
, uint8_t extra_word_length
,
50 usb_out_buffer
[0] = cmd_code
;
51 usb_out_buffer
[1] = extra_word_length
;
52 usb_out_buffer
[2] = (uint8_t)(address
& 0xFF);
55 static void aice_pack_htdc(uint8_t cmd_code
, uint8_t extra_word_length
,
56 uint32_t address
, uint32_t word
, enum aice_target_endian access_endian
)
58 usb_out_buffer
[0] = cmd_code
;
59 usb_out_buffer
[1] = extra_word_length
;
60 usb_out_buffer
[2] = (uint8_t)(address
& 0xFF);
61 if (access_endian
== AICE_BIG_ENDIAN
) {
62 usb_out_buffer
[6] = (uint8_t)((word
>> 24) & 0xFF);
63 usb_out_buffer
[5] = (uint8_t)((word
>> 16) & 0xFF);
64 usb_out_buffer
[4] = (uint8_t)((word
>> 8) & 0xFF);
65 usb_out_buffer
[3] = (uint8_t)(word
& 0xFF);
67 usb_out_buffer
[3] = (uint8_t)((word
>> 24) & 0xFF);
68 usb_out_buffer
[4] = (uint8_t)((word
>> 16) & 0xFF);
69 usb_out_buffer
[5] = (uint8_t)((word
>> 8) & 0xFF);
70 usb_out_buffer
[6] = (uint8_t)(word
& 0xFF);
74 static void aice_pack_htdma(uint8_t cmd_code
, uint8_t target_id
,
75 uint8_t extra_word_length
, uint32_t address
)
77 usb_out_buffer
[0] = cmd_code
;
78 usb_out_buffer
[1] = target_id
;
79 usb_out_buffer
[2] = extra_word_length
;
80 usb_out_buffer
[3] = (uint8_t)(address
& 0xFF);
83 static void aice_pack_htdmb(uint8_t cmd_code
, uint8_t target_id
,
84 uint8_t extra_word_length
, uint32_t address
)
86 usb_out_buffer
[0] = cmd_code
;
87 usb_out_buffer
[1] = target_id
;
88 usb_out_buffer
[2] = extra_word_length
;
89 usb_out_buffer
[3] = 0;
90 usb_out_buffer
[4] = (uint8_t)((address
>> 24) & 0xFF);
91 usb_out_buffer
[5] = (uint8_t)((address
>> 16) & 0xFF);
92 usb_out_buffer
[6] = (uint8_t)((address
>> 8) & 0xFF);
93 usb_out_buffer
[7] = (uint8_t)(address
& 0xFF);
96 static void aice_pack_htdmc(uint8_t cmd_code
, uint8_t target_id
,
97 uint8_t extra_word_length
, uint32_t address
, uint32_t word
,
98 enum aice_target_endian access_endian
)
100 usb_out_buffer
[0] = cmd_code
;
101 usb_out_buffer
[1] = target_id
;
102 usb_out_buffer
[2] = extra_word_length
;
103 usb_out_buffer
[3] = (uint8_t)(address
& 0xFF);
104 if (access_endian
== AICE_BIG_ENDIAN
) {
105 usb_out_buffer
[7] = (uint8_t)((word
>> 24) & 0xFF);
106 usb_out_buffer
[6] = (uint8_t)((word
>> 16) & 0xFF);
107 usb_out_buffer
[5] = (uint8_t)((word
>> 8) & 0xFF);
108 usb_out_buffer
[4] = (uint8_t)(word
& 0xFF);
110 usb_out_buffer
[4] = (uint8_t)((word
>> 24) & 0xFF);
111 usb_out_buffer
[5] = (uint8_t)((word
>> 16) & 0xFF);
112 usb_out_buffer
[6] = (uint8_t)((word
>> 8) & 0xFF);
113 usb_out_buffer
[7] = (uint8_t)(word
& 0xFF);
117 static void aice_pack_htdmc_multiple_data(uint8_t cmd_code
, uint8_t target_id
,
118 uint8_t extra_word_length
, uint32_t address
, uint32_t *word
,
119 uint8_t num_of_words
, enum aice_target_endian access_endian
)
121 usb_out_buffer
[0] = cmd_code
;
122 usb_out_buffer
[1] = target_id
;
123 usb_out_buffer
[2] = extra_word_length
;
124 usb_out_buffer
[3] = (uint8_t)(address
& 0xFF);
127 for (i
= 0 ; i
< num_of_words
; i
++, word
++) {
128 if (access_endian
== AICE_BIG_ENDIAN
) {
129 usb_out_buffer
[7 + i
* 4] = (uint8_t)((*word
>> 24) & 0xFF);
130 usb_out_buffer
[6 + i
* 4] = (uint8_t)((*word
>> 16) & 0xFF);
131 usb_out_buffer
[5 + i
* 4] = (uint8_t)((*word
>> 8) & 0xFF);
132 usb_out_buffer
[4 + i
* 4] = (uint8_t)(*word
& 0xFF);
134 usb_out_buffer
[4 + i
* 4] = (uint8_t)((*word
>> 24) & 0xFF);
135 usb_out_buffer
[5 + i
* 4] = (uint8_t)((*word
>> 16) & 0xFF);
136 usb_out_buffer
[6 + i
* 4] = (uint8_t)((*word
>> 8) & 0xFF);
137 usb_out_buffer
[7 + i
* 4] = (uint8_t)(*word
& 0xFF);
142 static void aice_pack_htdmd(uint8_t cmd_code
, uint8_t target_id
,
143 uint8_t extra_word_length
, uint32_t address
, uint32_t word
,
144 enum aice_target_endian access_endian
)
146 usb_out_buffer
[0] = cmd_code
;
147 usb_out_buffer
[1] = target_id
;
148 usb_out_buffer
[2] = extra_word_length
;
149 usb_out_buffer
[3] = 0;
150 usb_out_buffer
[4] = (uint8_t)((address
>> 24) & 0xFF);
151 usb_out_buffer
[5] = (uint8_t)((address
>> 16) & 0xFF);
152 usb_out_buffer
[6] = (uint8_t)((address
>> 8) & 0xFF);
153 usb_out_buffer
[7] = (uint8_t)(address
& 0xFF);
154 if (access_endian
== AICE_BIG_ENDIAN
) {
155 usb_out_buffer
[11] = (uint8_t)((word
>> 24) & 0xFF);
156 usb_out_buffer
[10] = (uint8_t)((word
>> 16) & 0xFF);
157 usb_out_buffer
[9] = (uint8_t)((word
>> 8) & 0xFF);
158 usb_out_buffer
[8] = (uint8_t)(word
& 0xFF);
160 usb_out_buffer
[8] = (uint8_t)((word
>> 24) & 0xFF);
161 usb_out_buffer
[9] = (uint8_t)((word
>> 16) & 0xFF);
162 usb_out_buffer
[10] = (uint8_t)((word
>> 8) & 0xFF);
163 usb_out_buffer
[11] = (uint8_t)(word
& 0xFF);
167 static void aice_pack_htdmd_multiple_data(uint8_t cmd_code
, uint8_t target_id
,
168 uint8_t extra_word_length
, uint32_t address
, const uint8_t *word
,
169 enum aice_target_endian access_endian
)
171 usb_out_buffer
[0] = cmd_code
;
172 usb_out_buffer
[1] = target_id
;
173 usb_out_buffer
[2] = extra_word_length
;
174 usb_out_buffer
[3] = 0;
175 usb_out_buffer
[4] = (uint8_t)((address
>> 24) & 0xFF);
176 usb_out_buffer
[5] = (uint8_t)((address
>> 16) & 0xFF);
177 usb_out_buffer
[6] = (uint8_t)((address
>> 8) & 0xFF);
178 usb_out_buffer
[7] = (uint8_t)(address
& 0xFF);
181 /* num_of_words may be over 0xFF, so use uint32_t */
182 uint32_t num_of_words
= extra_word_length
+ 1;
184 for (i
= 0 ; i
< num_of_words
; i
++, word
+= 4) {
185 if (access_endian
== AICE_BIG_ENDIAN
) {
186 usb_out_buffer
[11 + i
* 4] = word
[3];
187 usb_out_buffer
[10 + i
* 4] = word
[2];
188 usb_out_buffer
[9 + i
* 4] = word
[1];
189 usb_out_buffer
[8 + i
* 4] = word
[0];
191 usb_out_buffer
[8 + i
* 4] = word
[3];
192 usb_out_buffer
[9 + i
* 4] = word
[2];
193 usb_out_buffer
[10 + i
* 4] = word
[1];
194 usb_out_buffer
[11 + i
* 4] = word
[0];
199 static void aice_unpack_dtha(uint8_t *cmd_ack_code
, uint8_t *extra_word_length
,
200 uint32_t *word
, enum aice_target_endian access_endian
)
202 *cmd_ack_code
= usb_in_buffer
[0];
203 *extra_word_length
= usb_in_buffer
[1];
205 if (access_endian
== AICE_BIG_ENDIAN
) {
206 *word
= (usb_in_buffer
[5] << 24) |
207 (usb_in_buffer
[4] << 16) |
208 (usb_in_buffer
[3] << 8) |
211 *word
= (usb_in_buffer
[2] << 24) |
212 (usb_in_buffer
[3] << 16) |
213 (usb_in_buffer
[4] << 8) |
218 static void aice_unpack_dtha_multiple_data(uint8_t *cmd_ack_code
,
219 uint8_t *extra_word_length
, uint32_t *word
, uint8_t num_of_words
,
220 enum aice_target_endian access_endian
)
222 *cmd_ack_code
= usb_in_buffer
[0];
223 *extra_word_length
= usb_in_buffer
[1];
226 for (i
= 0 ; i
< num_of_words
; i
++, word
++) {
227 if (access_endian
== AICE_BIG_ENDIAN
) {
228 *word
= (usb_in_buffer
[5 + i
* 4] << 24) |
229 (usb_in_buffer
[4 + i
* 4] << 16) |
230 (usb_in_buffer
[3 + i
* 4] << 8) |
231 (usb_in_buffer
[2 + i
* 4]);
233 *word
= (usb_in_buffer
[2 + i
* 4] << 24) |
234 (usb_in_buffer
[3 + i
* 4] << 16) |
235 (usb_in_buffer
[4 + i
* 4] << 8) |
236 (usb_in_buffer
[5 + i
* 4]);
241 static void aice_unpack_dthb(uint8_t *cmd_ack_code
, uint8_t *extra_word_length
)
243 *cmd_ack_code
= usb_in_buffer
[0];
244 *extra_word_length
= usb_in_buffer
[1];
247 static void aice_unpack_dthma(uint8_t *cmd_ack_code
, uint8_t *target_id
,
248 uint8_t *extra_word_length
, uint32_t *word
,
249 enum aice_target_endian access_endian
)
251 *cmd_ack_code
= usb_in_buffer
[0];
252 *target_id
= usb_in_buffer
[1];
253 *extra_word_length
= usb_in_buffer
[2];
254 if (access_endian
== AICE_BIG_ENDIAN
) {
255 *word
= (usb_in_buffer
[7] << 24) |
256 (usb_in_buffer
[6] << 16) |
257 (usb_in_buffer
[5] << 8) |
260 *word
= (usb_in_buffer
[4] << 24) |
261 (usb_in_buffer
[5] << 16) |
262 (usb_in_buffer
[6] << 8) |
267 static void aice_unpack_dthma_multiple_data(uint8_t *cmd_ack_code
,
268 uint8_t *target_id
, uint8_t *extra_word_length
, uint8_t *word
,
269 enum aice_target_endian access_endian
)
271 *cmd_ack_code
= usb_in_buffer
[0];
272 *target_id
= usb_in_buffer
[1];
273 *extra_word_length
= usb_in_buffer
[2];
274 if (access_endian
== AICE_BIG_ENDIAN
) {
275 word
[0] = usb_in_buffer
[4];
276 word
[1] = usb_in_buffer
[5];
277 word
[2] = usb_in_buffer
[6];
278 word
[3] = usb_in_buffer
[7];
280 word
[0] = usb_in_buffer
[7];
281 word
[1] = usb_in_buffer
[6];
282 word
[2] = usb_in_buffer
[5];
283 word
[3] = usb_in_buffer
[4];
288 for (i
= 0; i
< *extra_word_length
; i
++) {
289 if (access_endian
== AICE_BIG_ENDIAN
) {
290 word
[0] = usb_in_buffer
[8 + i
* 4];
291 word
[1] = usb_in_buffer
[9 + i
* 4];
292 word
[2] = usb_in_buffer
[10 + i
* 4];
293 word
[3] = usb_in_buffer
[11 + i
* 4];
295 word
[0] = usb_in_buffer
[11 + i
* 4];
296 word
[1] = usb_in_buffer
[10 + i
* 4];
297 word
[2] = usb_in_buffer
[9 + i
* 4];
298 word
[3] = usb_in_buffer
[8 + i
* 4];
304 static void aice_unpack_dthmb(uint8_t *cmd_ack_code
, uint8_t *target_id
,
305 uint8_t *extra_word_length
)
307 *cmd_ack_code
= usb_in_buffer
[0];
308 *target_id
= usb_in_buffer
[1];
309 *extra_word_length
= usb_in_buffer
[2];
312 /***************************************************************************/
313 /* End of AICE commands' pack/unpack functions */
315 /* calls the given usb_bulk_* function, allowing for the data to
316 * trickle in with some timeouts */
317 static int usb_bulk_with_retries(
318 int (*f
)(jtag_libusb_device_handle
*, int, char *, int, int),
319 jtag_libusb_device_handle
*dev
, int ep
,
320 char *bytes
, int size
, int timeout
)
322 int tries
= 3, count
= 0;
324 while (tries
&& (count
< size
)) {
325 int result
= f(dev
, ep
, bytes
+ count
, size
- count
, timeout
);
328 else if ((-ETIMEDOUT
!= result
) || !--tries
)
334 static int wrap_usb_bulk_write(jtag_libusb_device_handle
*dev
, int ep
,
335 char *buff
, int size
, int timeout
)
337 /* usb_bulk_write() takes const char *buff */
338 return jtag_libusb_bulk_write(dev
, ep
, buff
, size
, timeout
);
341 static inline int usb_bulk_write_ex(jtag_libusb_device_handle
*dev
, int ep
,
342 char *bytes
, int size
, int timeout
)
344 return usb_bulk_with_retries(&wrap_usb_bulk_write
,
345 dev
, ep
, bytes
, size
, timeout
);
348 static inline int usb_bulk_read_ex(jtag_libusb_device_handle
*dev
, int ep
,
349 char *bytes
, int size
, int timeout
)
351 return usb_bulk_with_retries(&jtag_libusb_bulk_read
,
352 dev
, ep
, bytes
, size
, timeout
);
355 /* Write data from out_buffer to USB. */
356 static int aice_usb_write(uint8_t *out_buffer
, int out_length
)
360 if (out_length
> AICE_OUT_BUFFER_SIZE
) {
361 LOG_ERROR("aice_write illegal out_length=%d (max=%d)",
362 out_length
, AICE_OUT_BUFFER_SIZE
);
366 result
= usb_bulk_write_ex(aice_handler
.usb_handle
, aice_handler
.usb_write_ep
,
367 (char *)out_buffer
, out_length
, AICE_USB_TIMEOUT
);
369 DEBUG_JTAG_IO("aice_usb_write, out_length = %d, result = %d",
375 /* Read data from USB into in_buffer. */
376 static int aice_usb_read(uint8_t *in_buffer
, int expected_size
)
378 int result
= usb_bulk_read_ex(aice_handler
.usb_handle
, aice_handler
.usb_read_ep
,
379 (char *)in_buffer
, expected_size
, AICE_USB_TIMEOUT
);
381 DEBUG_JTAG_IO("aice_usb_read, result = %d", result
);
386 static uint8_t usb_out_packets_buffer
[AICE_OUT_PACKETS_BUFFER_SIZE
];
387 static uint8_t usb_in_packets_buffer
[AICE_IN_PACKETS_BUFFER_SIZE
];
388 static uint32_t usb_out_packets_buffer_length
;
389 static uint32_t usb_in_packets_buffer_length
;
390 static enum aice_command_mode aice_command_mode
;
392 static int aice_batch_buffer_write(uint8_t buf_index
, const uint8_t *word
,
393 uint32_t num_of_words
);
395 static int aice_usb_packet_flush(void)
397 if (usb_out_packets_buffer_length
== 0)
400 if (AICE_COMMAND_MODE_PACK
== aice_command_mode
) {
401 LOG_DEBUG("Flush usb packets (AICE_COMMAND_MODE_PACK)");
403 if (aice_usb_write(usb_out_packets_buffer
,
404 usb_out_packets_buffer_length
) < 0)
407 if (aice_usb_read(usb_in_packets_buffer
,
408 usb_in_packets_buffer_length
) < 0)
411 usb_out_packets_buffer_length
= 0;
412 usb_in_packets_buffer_length
= 0;
414 } else if (AICE_COMMAND_MODE_BATCH
== aice_command_mode
) {
415 LOG_DEBUG("Flush usb packets (AICE_COMMAND_MODE_BATCH)");
417 /* use BATCH_BUFFER_WRITE to fill command-batch-buffer */
418 if (aice_batch_buffer_write(AICE_BATCH_COMMAND_BUFFER_0
,
419 usb_out_packets_buffer
,
420 (usb_out_packets_buffer_length
+ 3) / 4) != ERROR_OK
)
423 usb_out_packets_buffer_length
= 0;
424 usb_in_packets_buffer_length
= 0;
426 /* enable BATCH command */
427 aice_command_mode
= AICE_COMMAND_MODE_NORMAL
;
428 if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_CTRL
, 0x80000000) != ERROR_OK
)
430 aice_command_mode
= AICE_COMMAND_MODE_BATCH
;
432 /* wait 1 second (AICE bug, workaround) */
437 uint32_t batch_status
;
441 aice_read_ctrl(AICE_READ_CTRL_BATCH_STATUS
, &batch_status
);
443 if (batch_status
& 0x1)
445 else if (batch_status
& 0xE)
458 static int aice_usb_packet_append(uint8_t *out_buffer
, int out_length
, int in_length
)
460 uint32_t max_packet_size
= AICE_OUT_PACKETS_BUFFER_SIZE
;
462 if (AICE_COMMAND_MODE_PACK
== aice_command_mode
) {
463 max_packet_size
= AICE_OUT_PACK_COMMAND_SIZE
;
464 } else if (AICE_COMMAND_MODE_BATCH
== aice_command_mode
) {
465 max_packet_size
= AICE_OUT_BATCH_COMMAND_SIZE
;
467 /* AICE_COMMAND_MODE_NORMAL */
468 if (aice_usb_packet_flush() != ERROR_OK
)
472 if (usb_out_packets_buffer_length
+ out_length
> max_packet_size
)
473 if (aice_usb_packet_flush() != ERROR_OK
) {
474 LOG_DEBUG("Flush usb packets failed");
478 LOG_DEBUG("Append usb packets 0x%02x", out_buffer
[0]);
480 memcpy(usb_out_packets_buffer
+ usb_out_packets_buffer_length
, out_buffer
, out_length
);
481 usb_out_packets_buffer_length
+= out_length
;
482 usb_in_packets_buffer_length
+= in_length
;
487 /***************************************************************************/
489 static int aice_reset_box(void)
491 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
494 /* turn off FASTMODE */
496 if (aice_read_ctrl(AICE_READ_CTRL_GET_JTAG_PIN_STATUS
, &pin_status
)
500 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_STATUS
, pin_status
& (~0x2))
507 static int aice_scan_chain(uint32_t *id_codes
, uint8_t *num_of_ids
)
512 if ((AICE_COMMAND_MODE_PACK
== aice_command_mode
) ||
513 (AICE_COMMAND_MODE_BATCH
== aice_command_mode
))
514 aice_usb_packet_flush();
517 aice_pack_htda(AICE_CMD_SCAN_CHAIN
, 0x0F, 0x0);
519 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDA
);
521 LOG_DEBUG("SCAN_CHAIN, length: 0x0F");
523 /** TODO: modify receive length */
524 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHA
);
525 if (AICE_FORMAT_DTHA
!= result
) {
526 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
527 AICE_FORMAT_DTHA
, result
);
531 uint8_t cmd_ack_code
;
532 aice_unpack_dtha_multiple_data(&cmd_ack_code
, num_of_ids
, id_codes
,
533 0x10, AICE_LITTLE_ENDIAN
);
535 if (cmd_ack_code
!= AICE_CMD_SCAN_CHAIN
) {
537 if (retry_times
> aice_max_retry_times
) {
538 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
539 AICE_CMD_SCAN_CHAIN
, cmd_ack_code
);
543 /* clear timeout and retry */
544 if (aice_reset_box() != ERROR_OK
)
551 LOG_DEBUG("SCAN_CHAIN response, # of IDs: %d", *num_of_ids
);
553 if (*num_of_ids
== 0xFF) {
554 LOG_ERROR("No target connected");
556 } else if (*num_of_ids
== AICE_MAX_NUM_CORE
) {
557 LOG_INFO("The ice chain over 16 targets");
567 int aice_read_ctrl(uint32_t address
, uint32_t *data
)
571 if ((AICE_COMMAND_MODE_PACK
== aice_command_mode
) ||
572 (AICE_COMMAND_MODE_BATCH
== aice_command_mode
))
573 aice_usb_packet_flush();
575 aice_pack_htda(AICE_CMD_READ_CTRL
, 0, address
);
577 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDA
);
579 LOG_DEBUG("READ_CTRL, address: 0x%x", address
);
581 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHA
);
582 if (AICE_FORMAT_DTHA
!= result
) {
583 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
584 AICE_FORMAT_DTHA
, result
);
588 uint8_t cmd_ack_code
;
589 uint8_t extra_length
;
590 aice_unpack_dtha(&cmd_ack_code
, &extra_length
, data
, AICE_LITTLE_ENDIAN
);
592 LOG_DEBUG("READ_CTRL response, data: 0x%x", *data
);
594 if (cmd_ack_code
!= AICE_CMD_READ_CTRL
) {
595 LOG_ERROR("aice command error (command=0x%x, response=0x%x)",
596 AICE_CMD_READ_CTRL
, cmd_ack_code
);
603 int aice_write_ctrl(uint32_t address
, uint32_t data
)
607 if (AICE_COMMAND_MODE_PACK
== aice_command_mode
) {
608 aice_usb_packet_flush();
609 } else if (AICE_COMMAND_MODE_BATCH
== aice_command_mode
) {
610 aice_pack_htdc(AICE_CMD_WRITE_CTRL
, 0, address
, data
, AICE_LITTLE_ENDIAN
);
611 return aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDC
,
615 aice_pack_htdc(AICE_CMD_WRITE_CTRL
, 0, address
, data
, AICE_LITTLE_ENDIAN
);
617 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDC
);
619 LOG_DEBUG("WRITE_CTRL, address: 0x%x, data: 0x%x", address
, data
);
621 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHB
);
622 if (AICE_FORMAT_DTHB
!= result
) {
623 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
624 AICE_FORMAT_DTHB
, result
);
628 uint8_t cmd_ack_code
;
629 uint8_t extra_length
;
630 aice_unpack_dthb(&cmd_ack_code
, &extra_length
);
632 LOG_DEBUG("WRITE_CTRL response");
634 if (cmd_ack_code
!= AICE_CMD_WRITE_CTRL
) {
635 LOG_ERROR("aice command error (command=0x%x, response=0x%x)",
636 AICE_CMD_WRITE_CTRL
, cmd_ack_code
);
643 int aice_read_dtr(uint8_t target_id
, uint32_t *data
)
648 if ((AICE_COMMAND_MODE_PACK
== aice_command_mode
) ||
649 (AICE_COMMAND_MODE_BATCH
== aice_command_mode
))
650 aice_usb_packet_flush();
653 aice_pack_htdma(AICE_CMD_T_READ_DTR
, target_id
, 0, 0);
655 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMA
);
657 LOG_DEBUG("READ_DTR, COREID: %d", target_id
);
659 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
);
660 if (AICE_FORMAT_DTHMA
!= result
) {
661 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
662 AICE_FORMAT_DTHMA
, result
);
666 uint8_t cmd_ack_code
;
667 uint8_t extra_length
;
668 uint8_t res_target_id
;
669 aice_unpack_dthma(&cmd_ack_code
, &res_target_id
, &extra_length
,
670 data
, AICE_LITTLE_ENDIAN
);
672 if (cmd_ack_code
== AICE_CMD_T_READ_DTR
) {
673 LOG_DEBUG("READ_DTR response, data: 0x%x", *data
);
677 if (retry_times
> aice_max_retry_times
) {
678 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
679 AICE_CMD_T_READ_DTR
, cmd_ack_code
);
683 /* clear timeout and retry */
684 if (aice_reset_box() != ERROR_OK
)
694 int aice_read_dtr_to_buffer(uint8_t target_id
, uint32_t buffer_idx
)
699 if (AICE_COMMAND_MODE_PACK
== aice_command_mode
) {
700 aice_usb_packet_flush();
701 } else if (AICE_COMMAND_MODE_BATCH
== aice_command_mode
) {
702 aice_pack_htdma(AICE_CMD_READ_DTR_TO_BUFFER
, target_id
, 0, buffer_idx
);
703 return aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDMA
,
708 aice_pack_htdma(AICE_CMD_READ_DTR_TO_BUFFER
, target_id
, 0, buffer_idx
);
710 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMA
);
712 LOG_DEBUG("READ_DTR_TO_BUFFER, COREID: %d", target_id
);
714 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
715 if (AICE_FORMAT_DTHMB
!= result
) {
716 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB
, result
);
720 uint8_t cmd_ack_code
;
721 uint8_t extra_length
;
722 uint8_t res_target_id
;
723 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
725 if (cmd_ack_code
== AICE_CMD_READ_DTR_TO_BUFFER
) {
728 if (retry_times
> aice_max_retry_times
) {
729 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
730 AICE_CMD_READ_DTR_TO_BUFFER
, cmd_ack_code
);
735 /* clear timeout and retry */
736 if (aice_reset_box() != ERROR_OK
)
746 int aice_write_dtr(uint8_t target_id
, uint32_t data
)
751 if (AICE_COMMAND_MODE_PACK
== aice_command_mode
) {
752 aice_usb_packet_flush();
753 } else if (AICE_COMMAND_MODE_BATCH
== aice_command_mode
) {
754 aice_pack_htdmc(AICE_CMD_T_WRITE_DTR
, target_id
, 0, 0, data
, AICE_LITTLE_ENDIAN
);
755 return aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDMC
,
760 aice_pack_htdmc(AICE_CMD_T_WRITE_DTR
, target_id
, 0, 0, data
, AICE_LITTLE_ENDIAN
);
762 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMC
);
764 LOG_DEBUG("WRITE_DTR, COREID: %d, data: 0x%x", target_id
, data
);
766 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
767 if (AICE_FORMAT_DTHMB
!= result
) {
768 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB
, result
);
772 uint8_t cmd_ack_code
;
773 uint8_t extra_length
;
774 uint8_t res_target_id
;
775 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
777 if (cmd_ack_code
== AICE_CMD_T_WRITE_DTR
) {
778 LOG_DEBUG("WRITE_DTR response");
781 if (retry_times
> aice_max_retry_times
) {
782 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
783 AICE_CMD_T_WRITE_DTR
, cmd_ack_code
);
788 /* clear timeout and retry */
789 if (aice_reset_box() != ERROR_OK
)
799 int aice_write_dtr_from_buffer(uint8_t target_id
, uint32_t buffer_idx
)
804 if (AICE_COMMAND_MODE_PACK
== aice_command_mode
) {
805 aice_usb_packet_flush();
806 } else if (AICE_COMMAND_MODE_BATCH
== aice_command_mode
) {
807 aice_pack_htdma(AICE_CMD_WRITE_DTR_FROM_BUFFER
, target_id
, 0, buffer_idx
);
808 return aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDMA
,
813 aice_pack_htdma(AICE_CMD_WRITE_DTR_FROM_BUFFER
, target_id
, 0, buffer_idx
);
815 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMA
);
817 LOG_DEBUG("WRITE_DTR_FROM_BUFFER, COREID: %d", target_id
);
819 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
820 if (AICE_FORMAT_DTHMB
!= result
) {
821 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB
, result
);
825 uint8_t cmd_ack_code
;
826 uint8_t extra_length
;
827 uint8_t res_target_id
;
828 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
830 if (cmd_ack_code
== AICE_CMD_WRITE_DTR_FROM_BUFFER
) {
833 if (retry_times
> aice_max_retry_times
) {
834 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
835 AICE_CMD_WRITE_DTR_FROM_BUFFER
, cmd_ack_code
);
840 /* clear timeout and retry */
841 if (aice_reset_box() != ERROR_OK
)
851 int aice_read_misc(uint8_t target_id
, uint32_t address
, uint32_t *data
)
856 if ((AICE_COMMAND_MODE_PACK
== aice_command_mode
) ||
857 (AICE_COMMAND_MODE_BATCH
== aice_command_mode
))
858 aice_usb_packet_flush();
861 aice_pack_htdma(AICE_CMD_T_READ_MISC
, target_id
, 0, address
);
863 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMA
);
865 LOG_DEBUG("READ_MISC, COREID: %d, address: 0x%x", target_id
, address
);
867 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
);
868 if (AICE_FORMAT_DTHMA
!= result
) {
869 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
870 AICE_FORMAT_DTHMA
, result
);
871 return ERROR_AICE_DISCONNECT
;
874 uint8_t cmd_ack_code
;
875 uint8_t extra_length
;
876 uint8_t res_target_id
;
877 aice_unpack_dthma(&cmd_ack_code
, &res_target_id
, &extra_length
,
878 data
, AICE_LITTLE_ENDIAN
);
880 if (cmd_ack_code
== AICE_CMD_T_READ_MISC
) {
881 LOG_DEBUG("READ_MISC response, data: 0x%x", *data
);
884 if (retry_times
> aice_max_retry_times
) {
885 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
886 AICE_CMD_T_READ_MISC
, cmd_ack_code
);
890 /* clear timeout and retry */
891 if (aice_reset_box() != ERROR_OK
)
901 int aice_write_misc(uint8_t target_id
, uint32_t address
, uint32_t data
)
906 if (AICE_COMMAND_MODE_PACK
== aice_command_mode
) {
907 aice_usb_packet_flush();
908 } else if (AICE_COMMAND_MODE_BATCH
== aice_command_mode
) {
909 aice_pack_htdmc(AICE_CMD_T_WRITE_MISC
, target_id
, 0, address
, data
,
911 return aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDMC
,
916 aice_pack_htdmc(AICE_CMD_T_WRITE_MISC
, target_id
, 0, address
,
917 data
, AICE_LITTLE_ENDIAN
);
919 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMC
);
921 LOG_DEBUG("WRITE_MISC, COREID: %d, address: 0x%x, data: 0x%x",
922 target_id
, address
, data
);
924 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
925 if (AICE_FORMAT_DTHMB
!= result
) {
926 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
927 AICE_FORMAT_DTHMB
, result
);
931 uint8_t cmd_ack_code
;
932 uint8_t extra_length
;
933 uint8_t res_target_id
;
934 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
936 if (cmd_ack_code
== AICE_CMD_T_WRITE_MISC
) {
937 LOG_DEBUG("WRITE_MISC response");
940 if (retry_times
> aice_max_retry_times
) {
941 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
942 AICE_CMD_T_WRITE_MISC
, cmd_ack_code
);
947 /* clear timeout and retry */
948 if (aice_reset_box() != ERROR_OK
)
958 int aice_read_edmsr(uint8_t target_id
, uint32_t address
, uint32_t *data
)
963 if ((AICE_COMMAND_MODE_PACK
== aice_command_mode
) ||
964 (AICE_COMMAND_MODE_BATCH
== aice_command_mode
))
965 aice_usb_packet_flush();
968 aice_pack_htdma(AICE_CMD_T_READ_EDMSR
, target_id
, 0, address
);
970 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMA
);
972 LOG_DEBUG("READ_EDMSR, COREID: %d, address: 0x%x", target_id
, address
);
974 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
);
975 if (AICE_FORMAT_DTHMA
!= result
) {
976 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
977 AICE_FORMAT_DTHMA
, result
);
981 uint8_t cmd_ack_code
;
982 uint8_t extra_length
;
983 uint8_t res_target_id
;
984 aice_unpack_dthma(&cmd_ack_code
, &res_target_id
, &extra_length
,
985 data
, AICE_LITTLE_ENDIAN
);
987 if (cmd_ack_code
== AICE_CMD_T_READ_EDMSR
) {
988 LOG_DEBUG("READ_EDMSR response, data: 0x%x", *data
);
991 if (retry_times
> aice_max_retry_times
) {
992 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
993 AICE_CMD_T_READ_EDMSR
, cmd_ack_code
);
998 /* clear timeout and retry */
999 if (aice_reset_box() != ERROR_OK
)
1009 int aice_write_edmsr(uint8_t target_id
, uint32_t address
, uint32_t data
)
1012 int retry_times
= 0;
1014 if (AICE_COMMAND_MODE_PACK
== aice_command_mode
) {
1015 aice_usb_packet_flush();
1016 } else if (AICE_COMMAND_MODE_BATCH
== aice_command_mode
) {
1017 aice_pack_htdmc(AICE_CMD_T_WRITE_EDMSR
, target_id
, 0, address
, data
,
1018 AICE_LITTLE_ENDIAN
);
1019 return aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDMC
,
1024 aice_pack_htdmc(AICE_CMD_T_WRITE_EDMSR
, target_id
, 0, address
,
1025 data
, AICE_LITTLE_ENDIAN
);
1027 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMC
);
1029 LOG_DEBUG("WRITE_EDMSR, COREID: %d, address: 0x%x, data: 0x%x",
1030 target_id
, address
, data
);
1032 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1033 if (AICE_FORMAT_DTHMB
!= result
) {
1034 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1035 AICE_FORMAT_DTHMB
, result
);
1039 uint8_t cmd_ack_code
;
1040 uint8_t extra_length
;
1041 uint8_t res_target_id
;
1042 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1044 if (cmd_ack_code
== AICE_CMD_T_WRITE_EDMSR
) {
1045 LOG_DEBUG("WRITE_EDMSR response");
1048 if (retry_times
> aice_max_retry_times
) {
1049 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
1050 AICE_CMD_T_WRITE_EDMSR
, cmd_ack_code
);
1055 /* clear timeout and retry */
1056 if (aice_reset_box() != ERROR_OK
)
1066 static int aice_switch_to_big_endian(uint32_t *word
, uint8_t num_of_words
)
1070 for (uint8_t i
= 0 ; i
< num_of_words
; i
++) {
1071 tmp
= ((word
[i
] >> 24) & 0x000000FF) |
1072 ((word
[i
] >> 8) & 0x0000FF00) |
1073 ((word
[i
] << 8) & 0x00FF0000) |
1074 ((word
[i
] << 24) & 0xFF000000);
1081 static int aice_write_dim(uint8_t target_id
, uint32_t *word
, uint8_t num_of_words
)
1084 uint32_t big_endian_word
[4];
1085 int retry_times
= 0;
1087 /** instruction is big-endian */
1088 memcpy(big_endian_word
, word
, sizeof(big_endian_word
));
1089 aice_switch_to_big_endian(big_endian_word
, num_of_words
);
1091 if (AICE_COMMAND_MODE_PACK
== aice_command_mode
) {
1092 aice_usb_packet_flush();
1093 } else if (AICE_COMMAND_MODE_BATCH
== aice_command_mode
) {
1094 aice_pack_htdmc_multiple_data(AICE_CMD_T_WRITE_DIM
, target_id
,
1095 num_of_words
- 1, 0, big_endian_word
, num_of_words
,
1096 AICE_LITTLE_ENDIAN
);
1097 return aice_usb_packet_append(usb_out_buffer
,
1098 AICE_FORMAT_HTDMC
+ (num_of_words
- 1) * 4,
1103 aice_pack_htdmc_multiple_data(AICE_CMD_T_WRITE_DIM
, target_id
, num_of_words
- 1, 0,
1104 big_endian_word
, num_of_words
, AICE_LITTLE_ENDIAN
);
1106 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMC
+ (num_of_words
- 1) * 4);
1108 LOG_DEBUG("WRITE_DIM, COREID: %d, data: 0x%08x, 0x%08x, 0x%08x, 0x%08x",
1113 big_endian_word
[3]);
1115 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1116 if (AICE_FORMAT_DTHMB
!= result
) {
1117 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB
, result
);
1121 uint8_t cmd_ack_code
;
1122 uint8_t extra_length
;
1123 uint8_t res_target_id
;
1124 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1127 if (cmd_ack_code
== AICE_CMD_T_WRITE_DIM
) {
1128 LOG_DEBUG("WRITE_DIM response");
1131 if (retry_times
> aice_max_retry_times
) {
1132 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)", AICE_CMD_T_WRITE_DIM
, cmd_ack_code
);
1137 /* clear timeout and retry */
1138 if (aice_reset_box() != ERROR_OK
)
1148 static int aice_do_execute(uint8_t target_id
)
1151 int retry_times
= 0;
1153 if (AICE_COMMAND_MODE_PACK
== aice_command_mode
) {
1154 aice_usb_packet_flush();
1155 } else if (AICE_COMMAND_MODE_BATCH
== aice_command_mode
) {
1156 aice_pack_htdmc(AICE_CMD_T_EXECUTE
, target_id
, 0, 0, 0, AICE_LITTLE_ENDIAN
);
1157 return aice_usb_packet_append(usb_out_buffer
,
1163 aice_pack_htdmc(AICE_CMD_T_EXECUTE
, target_id
, 0, 0, 0, AICE_LITTLE_ENDIAN
);
1165 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMC
);
1167 LOG_DEBUG("EXECUTE, COREID: %d", target_id
);
1169 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1170 if (AICE_FORMAT_DTHMB
!= result
) {
1171 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1172 AICE_FORMAT_DTHMB
, result
);
1176 uint8_t cmd_ack_code
;
1177 uint8_t extra_length
;
1178 uint8_t res_target_id
;
1179 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1181 if (cmd_ack_code
== AICE_CMD_T_EXECUTE
) {
1182 LOG_DEBUG("EXECUTE response");
1185 if (retry_times
> aice_max_retry_times
) {
1186 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
1187 AICE_CMD_T_EXECUTE
, cmd_ack_code
);
1192 /* clear timeout and retry */
1193 if (aice_reset_box() != ERROR_OK
)
1203 int aice_write_mem_b(uint8_t target_id
, uint32_t address
, uint32_t data
)
1206 int retry_times
= 0;
1208 LOG_DEBUG("WRITE_MEM_B, COREID: %d, ADDRESS %08" PRIx32
" VALUE %08" PRIx32
,
1213 if ((AICE_COMMAND_MODE_PACK
== aice_command_mode
) ||
1214 (AICE_COMMAND_MODE_BATCH
== aice_command_mode
)) {
1215 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_B
, target_id
, 0, address
,
1216 data
& 0x000000FF, data_endian
);
1217 return aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDMD
,
1221 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_B
, target_id
, 0,
1222 address
, data
& 0x000000FF, data_endian
);
1223 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMD
);
1225 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1226 if (AICE_FORMAT_DTHMB
!= result
) {
1227 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB
, result
);
1231 uint8_t cmd_ack_code
;
1232 uint8_t extra_length
;
1233 uint8_t res_target_id
;
1234 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1236 if (cmd_ack_code
== AICE_CMD_T_WRITE_MEM_B
) {
1239 if (retry_times
> aice_max_retry_times
) {
1240 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
1241 AICE_CMD_T_WRITE_MEM_B
, cmd_ack_code
);
1246 /* clear timeout and retry */
1247 if (aice_reset_box() != ERROR_OK
)
1258 int aice_write_mem_h(uint8_t target_id
, uint32_t address
, uint32_t data
)
1261 int retry_times
= 0;
1263 LOG_DEBUG("WRITE_MEM_H, COREID: %d, ADDRESS %08" PRIx32
" VALUE %08" PRIx32
,
1268 if ((AICE_COMMAND_MODE_PACK
== aice_command_mode
) ||
1269 (AICE_COMMAND_MODE_BATCH
== aice_command_mode
)) {
1270 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_H
, target_id
, 0,
1271 (address
>> 1) & 0x7FFFFFFF, data
& 0x0000FFFF, data_endian
);
1272 return aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDMD
,
1276 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_H
, target_id
, 0,
1277 (address
>> 1) & 0x7FFFFFFF, data
& 0x0000FFFF, data_endian
);
1278 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMD
);
1280 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1281 if (AICE_FORMAT_DTHMB
!= result
) {
1282 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1283 AICE_FORMAT_DTHMB
, result
);
1287 uint8_t cmd_ack_code
;
1288 uint8_t extra_length
;
1289 uint8_t res_target_id
;
1290 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1292 if (cmd_ack_code
== AICE_CMD_T_WRITE_MEM_H
) {
1295 if (retry_times
> aice_max_retry_times
) {
1296 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
1297 AICE_CMD_T_WRITE_MEM_H
, cmd_ack_code
);
1302 /* clear timeout and retry */
1303 if (aice_reset_box() != ERROR_OK
)
1314 int aice_write_mem(uint8_t target_id
, uint32_t address
, uint32_t data
)
1317 int retry_times
= 0;
1319 LOG_DEBUG("WRITE_MEM, COREID: %d, ADDRESS %08" PRIx32
" VALUE %08" PRIx32
,
1324 if ((AICE_COMMAND_MODE_PACK
== aice_command_mode
) ||
1325 (AICE_COMMAND_MODE_BATCH
== aice_command_mode
)) {
1326 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM
, target_id
, 0,
1327 (address
>> 2) & 0x3FFFFFFF, data
, data_endian
);
1328 return aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDMD
,
1332 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM
, target_id
, 0,
1333 (address
>> 2) & 0x3FFFFFFF, data
, data_endian
);
1334 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMD
);
1336 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1337 if (AICE_FORMAT_DTHMB
!= result
) {
1338 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1339 AICE_FORMAT_DTHMB
, result
);
1343 uint8_t cmd_ack_code
;
1344 uint8_t extra_length
;
1345 uint8_t res_target_id
;
1346 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1348 if (cmd_ack_code
== AICE_CMD_T_WRITE_MEM
) {
1351 if (retry_times
> aice_max_retry_times
) {
1352 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
1353 AICE_CMD_T_WRITE_MEM
, cmd_ack_code
);
1358 /* clear timeout and retry */
1359 if (aice_reset_box() != ERROR_OK
)
1370 int aice_fastread_mem(uint8_t target_id
, uint8_t *word
, uint32_t num_of_words
)
1373 int retry_times
= 0;
1375 if ((AICE_COMMAND_MODE_PACK
== aice_command_mode
) ||
1376 (AICE_COMMAND_MODE_BATCH
== aice_command_mode
))
1377 aice_usb_packet_flush();
1380 aice_pack_htdmb(AICE_CMD_T_FASTREAD_MEM
, target_id
, num_of_words
- 1, 0);
1382 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMB
);
1384 LOG_DEBUG("FASTREAD_MEM, COREID: %d, # of DATA %08" PRIx32
,
1385 target_id
, num_of_words
);
1387 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
+ (num_of_words
- 1) * 4);
1389 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1390 AICE_FORMAT_DTHMA
+ (num_of_words
- 1) * 4, result
);
1394 uint8_t cmd_ack_code
;
1395 uint8_t extra_length
;
1396 uint8_t res_target_id
;
1397 aice_unpack_dthma_multiple_data(&cmd_ack_code
, &res_target_id
,
1398 &extra_length
, word
, data_endian
);
1400 if (cmd_ack_code
== AICE_CMD_T_FASTREAD_MEM
) {
1403 if (retry_times
> aice_max_retry_times
) {
1404 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
1405 AICE_CMD_T_FASTREAD_MEM
, cmd_ack_code
);
1410 /* clear timeout and retry */
1411 if (aice_reset_box() != ERROR_OK
)
1421 int aice_fastwrite_mem(uint8_t target_id
, const uint8_t *word
, uint32_t num_of_words
)
1424 int retry_times
= 0;
1426 if (AICE_COMMAND_MODE_PACK
== aice_command_mode
) {
1427 aice_usb_packet_flush();
1428 } else if (AICE_COMMAND_MODE_BATCH
== aice_command_mode
) {
1429 aice_pack_htdmd_multiple_data(AICE_CMD_T_FASTWRITE_MEM
, target_id
,
1430 num_of_words
- 1, 0, word
, data_endian
);
1431 return aice_usb_packet_append(usb_out_buffer
,
1432 AICE_FORMAT_HTDMD
+ (num_of_words
- 1) * 4,
1437 aice_pack_htdmd_multiple_data(AICE_CMD_T_FASTWRITE_MEM
, target_id
,
1438 num_of_words
- 1, 0, word
, data_endian
);
1440 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMD
+ (num_of_words
- 1) * 4);
1442 LOG_DEBUG("FASTWRITE_MEM, COREID: %d, # of DATA %08" PRIx32
,
1443 target_id
, num_of_words
);
1445 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1446 if (AICE_FORMAT_DTHMB
!= result
) {
1447 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1448 AICE_FORMAT_DTHMB
, result
);
1452 uint8_t cmd_ack_code
;
1453 uint8_t extra_length
;
1454 uint8_t res_target_id
;
1455 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1457 if (cmd_ack_code
== AICE_CMD_T_FASTWRITE_MEM
) {
1460 if (retry_times
> aice_max_retry_times
) {
1461 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
1462 AICE_CMD_T_FASTWRITE_MEM
, cmd_ack_code
);
1467 /* clear timeout and retry */
1468 if (aice_reset_box() != ERROR_OK
)
1478 int aice_read_mem_b(uint8_t target_id
, uint32_t address
, uint32_t *data
)
1481 int retry_times
= 0;
1483 if ((AICE_COMMAND_MODE_PACK
== aice_command_mode
) ||
1484 (AICE_COMMAND_MODE_BATCH
== aice_command_mode
))
1485 aice_usb_packet_flush();
1488 aice_pack_htdmb(AICE_CMD_T_READ_MEM_B
, target_id
, 0, address
);
1490 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMB
);
1492 LOG_DEBUG("READ_MEM_B, COREID: %d", target_id
);
1494 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
);
1495 if (AICE_FORMAT_DTHMA
!= result
) {
1496 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1497 AICE_FORMAT_DTHMA
, result
);
1501 uint8_t cmd_ack_code
;
1502 uint8_t extra_length
;
1503 uint8_t res_target_id
;
1504 aice_unpack_dthma(&cmd_ack_code
, &res_target_id
, &extra_length
,
1507 if (cmd_ack_code
== AICE_CMD_T_READ_MEM_B
) {
1508 LOG_DEBUG("READ_MEM_B response, data: 0x%02x", *data
);
1511 if (retry_times
> aice_max_retry_times
) {
1512 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
1513 AICE_CMD_T_READ_MEM_B
, cmd_ack_code
);
1518 /* clear timeout and retry */
1519 if (aice_reset_box() != ERROR_OK
)
1529 int aice_read_mem_h(uint8_t target_id
, uint32_t address
, uint32_t *data
)
1532 int retry_times
= 0;
1534 if ((AICE_COMMAND_MODE_PACK
== aice_command_mode
) ||
1535 (AICE_COMMAND_MODE_BATCH
== aice_command_mode
))
1536 aice_usb_packet_flush();
1539 aice_pack_htdmb(AICE_CMD_T_READ_MEM_H
, target_id
, 0, (address
>> 1) & 0x7FFFFFFF);
1541 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMB
);
1543 LOG_DEBUG("READ_MEM_H, CORE_ID: %d", target_id
);
1545 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
);
1546 if (AICE_FORMAT_DTHMA
!= result
) {
1547 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1548 AICE_FORMAT_DTHMA
, result
);
1552 uint8_t cmd_ack_code
;
1553 uint8_t extra_length
;
1554 uint8_t res_target_id
;
1555 aice_unpack_dthma(&cmd_ack_code
, &res_target_id
, &extra_length
,
1558 if (cmd_ack_code
== AICE_CMD_T_READ_MEM_H
) {
1559 LOG_DEBUG("READ_MEM_H response, data: 0x%x", *data
);
1562 if (retry_times
> aice_max_retry_times
) {
1563 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
1564 AICE_CMD_T_READ_MEM_H
, cmd_ack_code
);
1569 /* clear timeout and retry */
1570 if (aice_reset_box() != ERROR_OK
)
1580 int aice_read_mem(uint8_t target_id
, uint32_t address
, uint32_t *data
)
1583 int retry_times
= 0;
1585 if ((AICE_COMMAND_MODE_PACK
== aice_command_mode
) ||
1586 (AICE_COMMAND_MODE_BATCH
== aice_command_mode
))
1587 aice_usb_packet_flush();
1590 aice_pack_htdmb(AICE_CMD_T_READ_MEM
, target_id
, 0,
1591 (address
>> 2) & 0x3FFFFFFF);
1593 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMB
);
1595 LOG_DEBUG("READ_MEM, COREID: %d", target_id
);
1597 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
);
1598 if (AICE_FORMAT_DTHMA
!= result
) {
1599 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1600 AICE_FORMAT_DTHMA
, result
);
1604 uint8_t cmd_ack_code
;
1605 uint8_t extra_length
;
1606 uint8_t res_target_id
;
1607 aice_unpack_dthma(&cmd_ack_code
, &res_target_id
, &extra_length
,
1610 if (cmd_ack_code
== AICE_CMD_T_READ_MEM
) {
1611 LOG_DEBUG("READ_MEM response, data: 0x%x", *data
);
1614 if (retry_times
> aice_max_retry_times
) {
1615 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
1616 AICE_CMD_T_READ_MEM
, cmd_ack_code
);
1621 /* clear timeout and retry */
1622 if (aice_reset_box() != ERROR_OK
)
1632 int aice_batch_buffer_read(uint8_t buf_index
, uint32_t *word
, uint32_t num_of_words
)
1635 int retry_times
= 0;
1638 aice_pack_htdma(AICE_CMD_BATCH_BUFFER_READ
, 0, num_of_words
- 1, buf_index
);
1640 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMA
);
1642 LOG_DEBUG("BATCH_BUFFER_READ, # of DATA %08" PRIx32
, num_of_words
);
1644 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
+ (num_of_words
- 1) * 4);
1646 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1647 AICE_FORMAT_DTHMA
+ (num_of_words
- 1) * 4, result
);
1651 uint8_t cmd_ack_code
;
1652 uint8_t extra_length
;
1653 uint8_t res_target_id
;
1654 aice_unpack_dthma_multiple_data(&cmd_ack_code
, &res_target_id
,
1655 &extra_length
, (uint8_t *)word
, data_endian
);
1657 if (cmd_ack_code
== AICE_CMD_BATCH_BUFFER_READ
) {
1660 if (retry_times
> aice_max_retry_times
) {
1661 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
1662 AICE_CMD_BATCH_BUFFER_READ
, cmd_ack_code
);
1667 /* clear timeout and retry */
1668 if (aice_reset_box() != ERROR_OK
)
1678 int aice_batch_buffer_write(uint8_t buf_index
, const uint8_t *word
, uint32_t num_of_words
)
1681 int retry_times
= 0;
1683 if (num_of_words
== 0)
1687 /* only pack AICE_CMD_BATCH_BUFFER_WRITE command header */
1688 aice_pack_htdmc(AICE_CMD_BATCH_BUFFER_WRITE
, 0, num_of_words
- 1, buf_index
,
1691 /* use append instead of pack */
1692 memcpy(usb_out_buffer
+ 4, word
, num_of_words
* 4);
1694 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMC
+ (num_of_words
- 1) * 4);
1696 LOG_DEBUG("BATCH_BUFFER_WRITE, # of DATA %08" PRIx32
, num_of_words
);
1698 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1699 if (AICE_FORMAT_DTHMB
!= result
) {
1700 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1701 AICE_FORMAT_DTHMB
, result
);
1705 uint8_t cmd_ack_code
;
1706 uint8_t extra_length
;
1707 uint8_t res_target_id
;
1708 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1710 if (cmd_ack_code
== AICE_CMD_BATCH_BUFFER_WRITE
) {
1713 if (retry_times
> aice_max_retry_times
) {
1714 LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
1715 AICE_CMD_BATCH_BUFFER_WRITE
, cmd_ack_code
);
1720 /* clear timeout and retry */
1721 if (aice_reset_box() != ERROR_OK
)
1731 /***************************************************************************/
1732 /* End of AICE commands */
1734 typedef int (*read_mem_func_t
)(uint32_t coreid
, uint32_t address
, uint32_t *data
);
1735 typedef int (*write_mem_func_t
)(uint32_t coreid
, uint32_t address
, uint32_t data
);
1737 struct aice_nds32_info core_info
[AICE_MAX_NUM_CORE
];
1738 static uint8_t total_num_of_core
;
1740 static char *custom_srst_script
;
1741 static char *custom_trst_script
;
1742 static char *custom_restart_script
;
1743 static uint32_t aice_count_to_check_dbger
= 30;
1745 static int aice_read_reg(uint32_t coreid
, uint32_t num
, uint32_t *val
);
1746 static int aice_write_reg(uint32_t coreid
, uint32_t num
, uint32_t val
);
1748 static int check_suppressed_exception(uint32_t coreid
, uint32_t dbger_value
)
1752 /* the default value of handling_suppressed_exception is false */
1753 static bool handling_suppressed_exception
;
1755 if (handling_suppressed_exception
)
1758 if ((dbger_value
& NDS_DBGER_ALL_SUPRS_EX
) == NDS_DBGER_ALL_SUPRS_EX
) {
1759 LOG_ERROR("<-- TARGET WARNING! Exception is detected and suppressed. -->");
1760 handling_suppressed_exception
= true;
1762 aice_read_reg(coreid
, IR4
, &ir4_value
);
1763 /* Clear IR6.SUPRS_EXC, IR6.IMP_EXC */
1764 aice_read_reg(coreid
, IR6
, &ir6_value
);
1766 * For MCU version(MSC_CFG.MCU == 1) like V3m
1767 * | SWID[30:16] | Reserved[15:10] | SUPRS_EXC[9] | IMP_EXC[8]
1768 * |VECTOR[7:5] | INST[4] | Exc Type[3:0] |
1770 * For non-MCU version(MSC_CFG.MCU == 0) like V3
1771 * | SWID[30:16] | Reserved[15:14] | SUPRS_EXC[13] | IMP_EXC[12]
1772 * | VECTOR[11:5] | INST[4] | Exc Type[3:0] |
1774 LOG_INFO("EVA: 0x%08x", ir4_value
);
1775 LOG_INFO("ITYPE: 0x%08x", ir6_value
);
1777 ir6_value
= ir6_value
& (~0x300); /* for MCU */
1778 ir6_value
= ir6_value
& (~0x3000); /* for non-MCU */
1779 aice_write_reg(coreid
, IR6
, ir6_value
);
1781 handling_suppressed_exception
= false;
1787 static int check_privilege(uint32_t coreid
, uint32_t dbger_value
)
1789 if ((dbger_value
& NDS_DBGER_ILL_SEC_ACC
) == NDS_DBGER_ILL_SEC_ACC
) {
1790 LOG_ERROR("<-- TARGET ERROR! Insufficient security privilege "
1791 "to execute the debug operations. -->");
1793 /* Clear DBGER.ILL_SEC_ACC */
1794 if (aice_write_misc(coreid
, NDS_EDM_MISC_DBGER
,
1795 NDS_DBGER_ILL_SEC_ACC
) != ERROR_OK
)
1802 static int aice_check_dbger(uint32_t coreid
, uint32_t expect_status
)
1805 uint32_t value_dbger
;
1808 aice_read_misc(coreid
, NDS_EDM_MISC_DBGER
, &value_dbger
);
1810 if ((value_dbger
& expect_status
) == expect_status
) {
1811 if (ERROR_OK
!= check_suppressed_exception(coreid
, value_dbger
))
1813 if (ERROR_OK
!= check_privilege(coreid
, value_dbger
))
1822 if (i
== aice_count_to_check_dbger
)
1823 then
= timeval_ms();
1824 if (i
>= aice_count_to_check_dbger
) {
1825 if ((timeval_ms() - then
) > 1000) {
1826 LOG_ERROR("Timeout (1000ms) waiting for $DBGER status "
1827 "being 0x%08x", expect_status
);
1837 static int aice_execute_dim(uint32_t coreid
, uint32_t *insts
, uint8_t n_inst
)
1840 if (aice_write_dim(coreid
, insts
, n_inst
) != ERROR_OK
)
1843 /** clear DBGER.DPED */
1844 if (aice_write_misc(coreid
, NDS_EDM_MISC_DBGER
, NDS_DBGER_DPED
) != ERROR_OK
)
1848 if (aice_do_execute(coreid
) != ERROR_OK
)
1851 /** read DBGER.DPED */
1852 if (aice_check_dbger(coreid
, NDS_DBGER_DPED
) != ERROR_OK
) {
1853 LOG_ERROR("<-- TARGET ERROR! Debug operations do not finish properly: "
1854 "0x%08x 0x%08x 0x%08x 0x%08x. -->",
1865 static int aice_read_reg(uint32_t coreid
, uint32_t num
, uint32_t *val
)
1867 LOG_DEBUG("aice_read_reg, reg_no: 0x%08x", num
);
1869 uint32_t instructions
[4]; /** execute instructions in DIM */
1871 if (NDS32_REG_TYPE_GPR
== nds32_reg_type(num
)) { /* general registers */
1872 instructions
[0] = MTSR_DTR(num
);
1873 instructions
[1] = DSB
;
1874 instructions
[2] = NOP
;
1875 instructions
[3] = BEQ_MINUS_12
;
1876 } else if (NDS32_REG_TYPE_SPR
== nds32_reg_type(num
)) { /* user special registers */
1877 instructions
[0] = MFUSR_G0(0, nds32_reg_sr_index(num
));
1878 instructions
[1] = MTSR_DTR(0);
1879 instructions
[2] = DSB
;
1880 instructions
[3] = BEQ_MINUS_12
;
1881 } else if (NDS32_REG_TYPE_AUMR
== nds32_reg_type(num
)) { /* audio registers */
1882 if ((CB_CTL
<= num
) && (num
<= CBE3
)) {
1883 instructions
[0] = AMFAR2(0, nds32_reg_sr_index(num
));
1884 instructions
[1] = MTSR_DTR(0);
1885 instructions
[2] = DSB
;
1886 instructions
[3] = BEQ_MINUS_12
;
1888 instructions
[0] = AMFAR(0, nds32_reg_sr_index(num
));
1889 instructions
[1] = MTSR_DTR(0);
1890 instructions
[2] = DSB
;
1891 instructions
[3] = BEQ_MINUS_12
;
1893 } else if (NDS32_REG_TYPE_FPU
== nds32_reg_type(num
)) { /* fpu registers */
1895 instructions
[0] = FMFCSR
;
1896 instructions
[1] = MTSR_DTR(0);
1897 instructions
[2] = DSB
;
1898 instructions
[3] = BEQ_MINUS_12
;
1899 } else if (FPCFG
== num
) {
1900 instructions
[0] = FMFCFG
;
1901 instructions
[1] = MTSR_DTR(0);
1902 instructions
[2] = DSB
;
1903 instructions
[3] = BEQ_MINUS_12
;
1905 if (FS0
<= num
&& num
<= FS31
) { /* single precision */
1906 instructions
[0] = FMFSR(0, nds32_reg_sr_index(num
));
1907 instructions
[1] = MTSR_DTR(0);
1908 instructions
[2] = DSB
;
1909 instructions
[3] = BEQ_MINUS_12
;
1910 } else if (FD0
<= num
&& num
<= FD31
) { /* double precision */
1911 instructions
[0] = FMFDR(0, nds32_reg_sr_index(num
));
1912 instructions
[1] = MTSR_DTR(0);
1913 instructions
[2] = DSB
;
1914 instructions
[3] = BEQ_MINUS_12
;
1917 } else { /* system registers */
1918 instructions
[0] = MFSR(0, nds32_reg_sr_index(num
));
1919 instructions
[1] = MTSR_DTR(0);
1920 instructions
[2] = DSB
;
1921 instructions
[3] = BEQ_MINUS_12
;
1924 aice_execute_dim(coreid
, instructions
, 4);
1926 uint32_t value_edmsw
;
1927 aice_read_edmsr(coreid
, NDS_EDM_SR_EDMSW
, &value_edmsw
);
1928 if (value_edmsw
& NDS_EDMSW_WDV
)
1929 aice_read_dtr(coreid
, val
);
1931 LOG_ERROR("<-- TARGET ERROR! The debug target failed to update "
1932 "the DTR register. -->");
1939 static int aice_usb_read_reg(uint32_t coreid
, uint32_t num
, uint32_t *val
)
1941 LOG_DEBUG("aice_usb_read_reg");
1944 *val
= core_info
[coreid
].r0_backup
;
1945 } else if (num
== R1
) {
1946 *val
= core_info
[coreid
].r1_backup
;
1947 } else if (num
== DR41
) {
1948 /* As target is halted, OpenOCD will backup DR41/DR42/DR43.
1949 * As user wants to read these registers, OpenOCD should return
1950 * the backup values, instead of reading the real values.
1951 * As user wants to write these registers, OpenOCD should write
1952 * to the backup values, instead of writing to real registers. */
1953 *val
= core_info
[coreid
].edmsw_backup
;
1954 } else if (num
== DR42
) {
1955 *val
= core_info
[coreid
].edm_ctl_backup
;
1956 } else if ((core_info
[coreid
].target_dtr_valid
== true) && (num
== DR43
)) {
1957 *val
= core_info
[coreid
].target_dtr_backup
;
1959 if (ERROR_OK
!= aice_read_reg(coreid
, num
, val
))
1966 static int aice_write_reg(uint32_t coreid
, uint32_t num
, uint32_t val
)
1968 LOG_DEBUG("aice_write_reg, reg_no: 0x%08x, value: 0x%08x", num
, val
);
1970 uint32_t instructions
[4]; /** execute instructions in DIM */
1971 uint32_t value_edmsw
;
1973 aice_write_dtr(coreid
, val
);
1974 aice_read_edmsr(coreid
, NDS_EDM_SR_EDMSW
, &value_edmsw
);
1975 if (0 == (value_edmsw
& NDS_EDMSW_RDV
)) {
1976 LOG_ERROR("<-- TARGET ERROR! AICE failed to write to the DTR register. -->");
1980 if (NDS32_REG_TYPE_GPR
== nds32_reg_type(num
)) { /* general registers */
1981 instructions
[0] = MFSR_DTR(num
);
1982 instructions
[1] = DSB
;
1983 instructions
[2] = NOP
;
1984 instructions
[3] = BEQ_MINUS_12
;
1985 } else if (NDS32_REG_TYPE_SPR
== nds32_reg_type(num
)) { /* user special registers */
1986 instructions
[0] = MFSR_DTR(0);
1987 instructions
[1] = MTUSR_G0(0, nds32_reg_sr_index(num
));
1988 instructions
[2] = DSB
;
1989 instructions
[3] = BEQ_MINUS_12
;
1990 } else if (NDS32_REG_TYPE_AUMR
== nds32_reg_type(num
)) { /* audio registers */
1991 if ((CB_CTL
<= num
) && (num
<= CBE3
)) {
1992 instructions
[0] = MFSR_DTR(0);
1993 instructions
[1] = AMTAR2(0, nds32_reg_sr_index(num
));
1994 instructions
[2] = DSB
;
1995 instructions
[3] = BEQ_MINUS_12
;
1997 instructions
[0] = MFSR_DTR(0);
1998 instructions
[1] = AMTAR(0, nds32_reg_sr_index(num
));
1999 instructions
[2] = DSB
;
2000 instructions
[3] = BEQ_MINUS_12
;
2002 } else if (NDS32_REG_TYPE_FPU
== nds32_reg_type(num
)) { /* fpu registers */
2004 instructions
[0] = MFSR_DTR(0);
2005 instructions
[1] = FMTCSR
;
2006 instructions
[2] = DSB
;
2007 instructions
[3] = BEQ_MINUS_12
;
2008 } else if (FPCFG
== num
) {
2009 /* FPCFG is readonly */
2011 if (FS0
<= num
&& num
<= FS31
) { /* single precision */
2012 instructions
[0] = MFSR_DTR(0);
2013 instructions
[1] = FMTSR(0, nds32_reg_sr_index(num
));
2014 instructions
[2] = DSB
;
2015 instructions
[3] = BEQ_MINUS_12
;
2016 } else if (FD0
<= num
&& num
<= FD31
) { /* double precision */
2017 instructions
[0] = MFSR_DTR(0);
2018 instructions
[1] = FMTDR(0, nds32_reg_sr_index(num
));
2019 instructions
[2] = DSB
;
2020 instructions
[3] = BEQ_MINUS_12
;
2024 instructions
[0] = MFSR_DTR(0);
2025 instructions
[1] = MTSR(0, nds32_reg_sr_index(num
));
2026 instructions
[2] = DSB
;
2027 instructions
[3] = BEQ_MINUS_12
;
2030 return aice_execute_dim(coreid
, instructions
, 4);
2033 static int aice_usb_write_reg(uint32_t coreid
, uint32_t num
, uint32_t val
)
2035 LOG_DEBUG("aice_usb_write_reg");
2038 core_info
[coreid
].r0_backup
= val
;
2040 core_info
[coreid
].r1_backup
= val
;
2041 else if (num
== DR42
)
2042 /* As target is halted, OpenOCD will backup DR41/DR42/DR43.
2043 * As user wants to read these registers, OpenOCD should return
2044 * the backup values, instead of reading the real values.
2045 * As user wants to write these registers, OpenOCD should write
2046 * to the backup values, instead of writing to real registers. */
2047 core_info
[coreid
].edm_ctl_backup
= val
;
2048 else if ((core_info
[coreid
].target_dtr_valid
== true) && (num
== DR43
))
2049 core_info
[coreid
].target_dtr_backup
= val
;
2051 return aice_write_reg(coreid
, num
, val
);
2056 static int aice_usb_open(struct aice_port_param_s
*param
)
2058 const uint16_t vids
[] = { param
->vid
, 0 };
2059 const uint16_t pids
[] = { param
->pid
, 0 };
2060 struct jtag_libusb_device_handle
*devh
;
2062 if (jtag_libusb_open(vids
, pids
, &devh
) != ERROR_OK
)
2065 /* BE ***VERY CAREFUL*** ABOUT MAKING CHANGES IN THIS
2066 * AREA!!!!!!!!!!! The behavior of libusb is not completely
2067 * consistent across Windows, Linux, and Mac OS X platforms.
2068 * The actions taken in the following compiler conditionals may
2069 * not agree with published documentation for libusb, but were
2070 * found to be necessary through trials and tribulations. Even
2071 * little tweaks can break one or more platforms, so if you do
2072 * make changes test them carefully on all platforms before
2078 jtag_libusb_reset_device(devh
);
2083 /* reopen jlink after usb_reset
2084 * on win32 this may take a second or two to re-enumerate */
2086 while ((retval
= jtag_libusb_open(vids
, pids
, &devh
)) != ERROR_OK
) {
2092 if (ERROR_OK
!= retval
)
2098 /* usb_set_configuration required under win32 */
2099 struct jtag_libusb_device
*udev
= jtag_libusb_get_device(devh
);
2100 jtag_libusb_set_configuration(devh
, 0);
2101 jtag_libusb_claim_interface(devh
, 0);
2103 unsigned int aice_read_ep
;
2104 unsigned int aice_write_ep
;
2105 jtag_libusb_get_endpoints(udev
, &aice_read_ep
, &aice_write_ep
);
2107 aice_handler
.usb_read_ep
= aice_read_ep
;
2108 aice_handler
.usb_write_ep
= aice_write_ep
;
2109 aice_handler
.usb_handle
= devh
;
2114 static int aice_usb_read_reg_64(uint32_t coreid
, uint32_t num
, uint64_t *val
)
2116 LOG_DEBUG("aice_usb_read_reg_64, %s", nds32_reg_simple_name(num
));
2119 uint32_t high_value
;
2121 if (ERROR_OK
!= aice_read_reg(coreid
, num
, &value
))
2124 aice_read_reg(coreid
, R1
, &high_value
);
2126 LOG_DEBUG("low: 0x%08x, high: 0x%08x\n", value
, high_value
);
2128 if (data_endian
== AICE_BIG_ENDIAN
)
2129 *val
= (((uint64_t)high_value
) << 32) | value
;
2131 *val
= (((uint64_t)value
) << 32) | high_value
;
2136 static int aice_usb_write_reg_64(uint32_t coreid
, uint32_t num
, uint64_t val
)
2139 uint32_t high_value
;
2141 if (data_endian
== AICE_BIG_ENDIAN
) {
2142 value
= val
& 0xFFFFFFFF;
2143 high_value
= (val
>> 32) & 0xFFFFFFFF;
2145 high_value
= val
& 0xFFFFFFFF;
2146 value
= (val
>> 32) & 0xFFFFFFFF;
2149 LOG_DEBUG("aice_usb_write_reg_64, %s, low: 0x%08x, high: 0x%08x\n",
2150 nds32_reg_simple_name(num
), value
, high_value
);
2152 aice_write_reg(coreid
, R1
, high_value
);
2153 return aice_write_reg(coreid
, num
, value
);
2156 static int aice_get_version_info(void)
2158 uint32_t hardware_version
;
2159 uint32_t firmware_version
;
2160 uint32_t fpga_version
;
2162 if (aice_read_ctrl(AICE_READ_CTRL_GET_HARDWARE_VERSION
, &hardware_version
) != ERROR_OK
)
2165 if (aice_read_ctrl(AICE_READ_CTRL_GET_FIRMWARE_VERSION
, &firmware_version
) != ERROR_OK
)
2168 if (aice_read_ctrl(AICE_READ_CTRL_GET_FPGA_VERSION
, &fpga_version
) != ERROR_OK
)
2171 LOG_INFO("AICE version: hw_ver = 0x%x, fw_ver = 0x%x, fpga_ver = 0x%x",
2172 hardware_version
, firmware_version
, fpga_version
);
2177 #define LINE_BUFFER_SIZE 1024
2179 static int aice_execute_custom_script(const char *script
)
2182 char line_buffer
[LINE_BUFFER_SIZE
];
2186 uint32_t write_ctrl_value
;
2189 script_fd
= fopen(script
, "r");
2190 if (script_fd
== NULL
) {
2193 while (fgets(line_buffer
, LINE_BUFFER_SIZE
, script_fd
) != NULL
) {
2194 /* execute operations */
2196 op_str
= strstr(line_buffer
, "set");
2197 if (op_str
!= NULL
) {
2199 goto get_reset_type
;
2202 op_str
= strstr(line_buffer
, "clear");
2206 reset_str
= strstr(op_str
, "srst");
2207 if (reset_str
!= NULL
) {
2209 write_ctrl_value
= AICE_CUSTOM_DELAY_SET_SRST
;
2211 write_ctrl_value
= AICE_CUSTOM_DELAY_CLEAN_SRST
;
2214 reset_str
= strstr(op_str
, "dbgi");
2215 if (reset_str
!= NULL
) {
2217 write_ctrl_value
= AICE_CUSTOM_DELAY_SET_DBGI
;
2219 write_ctrl_value
= AICE_CUSTOM_DELAY_CLEAN_DBGI
;
2222 reset_str
= strstr(op_str
, "trst");
2223 if (reset_str
!= NULL
) {
2225 write_ctrl_value
= AICE_CUSTOM_DELAY_SET_TRST
;
2227 write_ctrl_value
= AICE_CUSTOM_DELAY_CLEAN_TRST
;
2233 delay
= strtoul(reset_str
+ 4, NULL
, 0);
2234 write_ctrl_value
|= (delay
<< 16);
2236 if (aice_write_ctrl(AICE_WRITE_CTRL_CUSTOM_DELAY
,
2237 write_ctrl_value
) != ERROR_OK
) {
2248 static int aice_usb_set_clock(int set_clock
)
2250 if (aice_write_ctrl(AICE_WRITE_CTRL_TCK_CONTROL
,
2251 AICE_TCK_CONTROL_TCK_SCAN
) != ERROR_OK
)
2254 /* Read out TCK_SCAN clock value */
2255 uint32_t scan_clock
;
2256 if (aice_read_ctrl(AICE_READ_CTRL_GET_ICE_STATE
, &scan_clock
) != ERROR_OK
)
2261 uint32_t scan_base_freq
;
2262 if (scan_clock
& 0x8)
2263 scan_base_freq
= 48000; /* 48 MHz */
2265 scan_base_freq
= 30000; /* 30 MHz */
2267 uint32_t set_base_freq
;
2268 if (set_clock
& 0x8)
2269 set_base_freq
= 48000;
2271 set_base_freq
= 30000;
2275 set_freq
= set_base_freq
>> (set_clock
& 0x7);
2276 scan_freq
= scan_base_freq
>> (scan_clock
& 0x7);
2278 if (scan_freq
< set_freq
) {
2279 LOG_ERROR("User specifies higher jtag clock than TCK_SCAN clock");
2283 if (aice_write_ctrl(AICE_WRITE_CTRL_TCK_CONTROL
, set_clock
) != ERROR_OK
)
2286 uint32_t check_speed
;
2287 if (aice_read_ctrl(AICE_READ_CTRL_GET_ICE_STATE
, &check_speed
) != ERROR_OK
)
2290 if (((int)check_speed
& 0x0F) != set_clock
) {
2291 LOG_ERROR("Set jtag clock failed");
2298 static int aice_edm_init(uint32_t coreid
)
2300 aice_write_edmsr(coreid
, NDS_EDM_SR_DIMBR
, 0xFFFF0000);
2301 aice_write_misc(coreid
, NDS_EDM_MISC_DIMIR
, 0);
2303 /* unconditionally try to turn on V3_EDM_MODE */
2304 uint32_t edm_ctl_value
;
2305 aice_read_edmsr(coreid
, NDS_EDM_SR_EDM_CTL
, &edm_ctl_value
);
2306 aice_write_edmsr(coreid
, NDS_EDM_SR_EDM_CTL
, edm_ctl_value
| 0x00000040);
2309 aice_write_misc(coreid
, NDS_EDM_MISC_DBGER
,
2310 NDS_DBGER_DPED
| NDS_DBGER_CRST
| NDS_DBGER_AT_MAX
);
2312 /* get EDM version */
2313 uint32_t value_edmcfg
;
2314 aice_read_edmsr(coreid
, NDS_EDM_SR_EDM_CFG
, &value_edmcfg
);
2315 core_info
[coreid
].edm_version
= (value_edmcfg
>> 16) & 0xFFFF;
2320 static bool is_v2_edm(uint32_t coreid
)
2322 if ((core_info
[coreid
].edm_version
& 0x1000) == 0)
2328 static int aice_init_edm_registers(uint32_t coreid
, bool clear_dex_use_psw
)
2330 /* enable DEH_SEL & MAX_STOP & V3_EDM_MODE & DBGI_MASK */
2331 uint32_t host_edm_ctl
= core_info
[coreid
].edm_ctl_backup
| 0xA000004F;
2332 if (clear_dex_use_psw
)
2333 /* After entering debug mode, OpenOCD may set
2334 * DEX_USE_PSW accidentally through backup value
2335 * of target EDM_CTL.
2336 * So, clear DEX_USE_PSW by force. */
2337 host_edm_ctl
&= ~(0x40000000);
2339 LOG_DEBUG("aice_init_edm_registers - EDM_CTL: 0x%08x", host_edm_ctl
);
2341 int result
= aice_write_edmsr(coreid
, NDS_EDM_SR_EDM_CTL
, host_edm_ctl
);
2347 * EDM_CTL will be modified by OpenOCD as debugging. OpenOCD has the
2348 * responsibility to keep EDM_CTL untouched after debugging.
2350 * There are two scenarios to consider:
2351 * 1. single step/running as debugging (running under debug session)
2352 * 2. detached from gdb (exit debug session)
2354 * So, we need to bakcup EDM_CTL before halted and restore it after
2355 * running. The difference of these two scenarios is EDM_CTL.DEH_SEL
2356 * is on for scenario 1, and off for scenario 2.
2358 static int aice_backup_edm_registers(uint32_t coreid
)
2360 int result
= aice_read_edmsr(coreid
, NDS_EDM_SR_EDM_CTL
,
2361 &core_info
[coreid
].edm_ctl_backup
);
2363 /* To call aice_backup_edm_registers() after DEX on, DEX_USE_PSW
2364 * may be not correct. (For example, hit breakpoint, then backup
2365 * EDM_CTL. EDM_CTL.DEX_USE_PSW will be cleared.) Because debug
2366 * interrupt will clear DEX_USE_PSW, DEX_USE_PSW is always off after
2367 * DEX is on. It only backups correct value before OpenOCD issues DBGI.
2368 * (Backup EDM_CTL, then issue DBGI actively (refer aice_usb_halt())) */
2369 if (core_info
[coreid
].edm_ctl_backup
& 0x40000000)
2370 core_info
[coreid
].dex_use_psw_on
= true;
2372 core_info
[coreid
].dex_use_psw_on
= false;
2374 LOG_DEBUG("aice_backup_edm_registers - EDM_CTL: 0x%08x, DEX_USE_PSW: %s",
2375 core_info
[coreid
].edm_ctl_backup
,
2376 core_info
[coreid
].dex_use_psw_on
? "on" : "off");
2381 static int aice_restore_edm_registers(uint32_t coreid
)
2383 LOG_DEBUG("aice_restore_edm_registers -");
2385 /* set DEH_SEL, because target still under EDM control */
2386 int result
= aice_write_edmsr(coreid
, NDS_EDM_SR_EDM_CTL
,
2387 core_info
[coreid
].edm_ctl_backup
| 0x80000000);
2392 static int aice_backup_tmp_registers(uint32_t coreid
)
2394 LOG_DEBUG("backup_tmp_registers -");
2396 /* backup target DTR first(if the target DTR is valid) */
2397 uint32_t value_edmsw
;
2398 aice_read_edmsr(coreid
, NDS_EDM_SR_EDMSW
, &value_edmsw
);
2399 core_info
[coreid
].edmsw_backup
= value_edmsw
;
2400 if (value_edmsw
& 0x1) { /* EDMSW.WDV == 1 */
2401 aice_read_dtr(coreid
, &core_info
[coreid
].target_dtr_backup
);
2402 core_info
[coreid
].target_dtr_valid
= true;
2404 LOG_DEBUG("Backup target DTR: 0x%08x", core_info
[coreid
].target_dtr_backup
);
2406 core_info
[coreid
].target_dtr_valid
= false;
2409 /* Target DTR has been backup, then backup $R0 and $R1 */
2410 aice_read_reg(coreid
, R0
, &core_info
[coreid
].r0_backup
);
2411 aice_read_reg(coreid
, R1
, &core_info
[coreid
].r1_backup
);
2413 /* backup host DTR(if the host DTR is valid) */
2414 if (value_edmsw
& 0x2) { /* EDMSW.RDV == 1*/
2415 /* read out host DTR and write into target DTR, then use aice_read_edmsr to
2417 uint32_t instructions
[4] = {
2418 MFSR_DTR(R0
), /* R0 has already been backup */
2423 aice_execute_dim(coreid
, instructions
, 4);
2425 aice_read_dtr(coreid
, &core_info
[coreid
].host_dtr_backup
);
2426 core_info
[coreid
].host_dtr_valid
= true;
2428 LOG_DEBUG("Backup host DTR: 0x%08x", core_info
[coreid
].host_dtr_backup
);
2430 core_info
[coreid
].host_dtr_valid
= false;
2433 LOG_DEBUG("r0: 0x%08x, r1: 0x%08x",
2434 core_info
[coreid
].r0_backup
, core_info
[coreid
].r1_backup
);
2439 static int aice_restore_tmp_registers(uint32_t coreid
)
2441 LOG_DEBUG("restore_tmp_registers - r0: 0x%08x, r1: 0x%08x",
2442 core_info
[coreid
].r0_backup
, core_info
[coreid
].r1_backup
);
2444 if (core_info
[coreid
].target_dtr_valid
) {
2445 uint32_t instructions
[4] = {
2446 SETHI(R0
, core_info
[coreid
].target_dtr_backup
>> 12),
2447 ORI(R0
, R0
, core_info
[coreid
].target_dtr_backup
& 0x00000FFF),
2451 aice_execute_dim(coreid
, instructions
, 4);
2453 instructions
[0] = MTSR_DTR(R0
);
2454 instructions
[1] = DSB
;
2455 instructions
[2] = NOP
;
2456 instructions
[3] = BEQ_MINUS_12
;
2457 aice_execute_dim(coreid
, instructions
, 4);
2459 LOG_DEBUG("Restore target DTR: 0x%08x", core_info
[coreid
].target_dtr_backup
);
2462 aice_write_reg(coreid
, R0
, core_info
[coreid
].r0_backup
);
2463 aice_write_reg(coreid
, R1
, core_info
[coreid
].r1_backup
);
2465 if (core_info
[coreid
].host_dtr_valid
) {
2466 aice_write_dtr(coreid
, core_info
[coreid
].host_dtr_backup
);
2468 LOG_DEBUG("Restore host DTR: 0x%08x", core_info
[coreid
].host_dtr_backup
);
2474 static int aice_open_device(struct aice_port_param_s
*param
)
2476 if (ERROR_OK
!= aice_usb_open(param
))
2479 if (ERROR_FAIL
== aice_get_version_info()) {
2480 LOG_ERROR("Cannot get AICE version!");
2484 LOG_INFO("AICE initialization started");
2486 /* attempt to reset Andes EDM */
2487 if (ERROR_FAIL
== aice_reset_box()) {
2488 LOG_ERROR("Cannot initial AICE box!");
2495 static int aice_usb_set_jtag_clock(uint32_t a_clock
)
2497 jtag_clock
= a_clock
;
2499 if (ERROR_OK
!= aice_usb_set_clock(a_clock
)) {
2500 LOG_ERROR("Cannot set AICE JTAG clock!");
2507 static int aice_usb_close(void)
2509 jtag_libusb_close(aice_handler
.usb_handle
);
2511 if (custom_srst_script
)
2512 free(custom_srst_script
);
2514 if (custom_trst_script
)
2515 free(custom_trst_script
);
2517 if (custom_restart_script
)
2518 free(custom_restart_script
);
2523 static int aice_core_init(uint32_t coreid
)
2525 core_info
[coreid
].access_channel
= NDS_MEMORY_ACC_CPU
;
2526 core_info
[coreid
].memory_select
= NDS_MEMORY_SELECT_AUTO
;
2527 core_info
[coreid
].core_state
= AICE_TARGET_UNKNOWN
;
2532 static int aice_usb_idcode(uint32_t *idcode
, uint8_t *num_of_idcode
)
2536 retval
= aice_scan_chain(idcode
, num_of_idcode
);
2537 if (ERROR_OK
== retval
) {
2538 for (int i
= 0; i
< *num_of_idcode
; i
++) {
2542 total_num_of_core
= *num_of_idcode
;
2548 static int aice_usb_halt(uint32_t coreid
)
2550 if (core_info
[coreid
].core_state
== AICE_TARGET_HALTED
) {
2551 LOG_DEBUG("aice_usb_halt check halted");
2555 LOG_DEBUG("aice_usb_halt");
2557 /** backup EDM registers */
2558 aice_backup_edm_registers(coreid
);
2559 /** init EDM for host debugging */
2560 /** no need to clear dex_use_psw, because dbgi will clear it */
2561 aice_init_edm_registers(coreid
, false);
2563 /** Clear EDM_CTL.DBGIM & EDM_CTL.DBGACKM */
2564 uint32_t edm_ctl_value
;
2565 aice_read_edmsr(coreid
, NDS_EDM_SR_EDM_CTL
, &edm_ctl_value
);
2566 if (edm_ctl_value
& 0x3)
2567 aice_write_edmsr(coreid
, NDS_EDM_SR_EDM_CTL
, edm_ctl_value
& ~(0x3));
2570 uint32_t acc_ctl_value
;
2572 core_info
[coreid
].debug_under_dex_on
= false;
2573 aice_read_misc(coreid
, NDS_EDM_MISC_DBGER
, &dbger
);
2575 if (dbger
& NDS_DBGER_AT_MAX
)
2576 LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level. -->");
2578 if (dbger
& NDS_DBGER_DEX
) {
2579 if (is_v2_edm(coreid
) == false) {
2580 /** debug 'debug mode'. use force_debug to issue dbgi */
2581 aice_read_misc(coreid
, NDS_EDM_MISC_ACC_CTL
, &acc_ctl_value
);
2582 acc_ctl_value
|= 0x8;
2583 aice_write_misc(coreid
, NDS_EDM_MISC_ACC_CTL
, acc_ctl_value
);
2584 core_info
[coreid
].debug_under_dex_on
= true;
2586 aice_write_misc(coreid
, NDS_EDM_MISC_EDM_CMDR
, 0);
2587 /* If CPU stalled due to AT_MAX, clear AT_MAX status. */
2588 if (dbger
& NDS_DBGER_AT_MAX
)
2589 aice_write_misc(coreid
, NDS_EDM_MISC_DBGER
, NDS_DBGER_AT_MAX
);
2592 /** Issue DBGI normally */
2593 aice_write_misc(coreid
, NDS_EDM_MISC_EDM_CMDR
, 0);
2594 /* If CPU stalled due to AT_MAX, clear AT_MAX status. */
2595 if (dbger
& NDS_DBGER_AT_MAX
)
2596 aice_write_misc(coreid
, NDS_EDM_MISC_DBGER
, NDS_DBGER_AT_MAX
);
2599 if (aice_check_dbger(coreid
, NDS_DBGER_DEX
) != ERROR_OK
) {
2600 LOG_ERROR("<-- TARGET ERROR! Unable to stop the debug target through DBGI. -->");
2604 if (core_info
[coreid
].debug_under_dex_on
) {
2605 if (core_info
[coreid
].dex_use_psw_on
== false) {
2606 /* under debug 'debug mode', force $psw to 'debug mode' bahavior */
2607 /* !!!NOTICE!!! this is workaround for debug 'debug mode'.
2608 * it is only for debugging 'debug exception handler' purpose.
2609 * after openocd detaches from target, target behavior is
2612 uint32_t debug_mode_ir0_value
;
2613 aice_read_reg(coreid
, IR0
, &ir0_value
);
2614 debug_mode_ir0_value
= ir0_value
| 0x408; /* turn on DEX, set POM = 1 */
2615 debug_mode_ir0_value
&= ~(0x000000C1); /* turn off DT/IT/GIE */
2616 aice_write_reg(coreid
, IR0
, debug_mode_ir0_value
);
2620 /** set EDM_CTL.DBGIM & EDM_CTL.DBGACKM after halt */
2621 if (edm_ctl_value
& 0x3)
2622 aice_write_edmsr(coreid
, NDS_EDM_SR_EDM_CTL
, edm_ctl_value
);
2624 /* backup r0 & r1 */
2625 aice_backup_tmp_registers(coreid
);
2626 core_info
[coreid
].core_state
= AICE_TARGET_HALTED
;
2631 static int aice_usb_state(uint32_t coreid
, enum aice_target_state_s
*state
)
2633 uint32_t dbger_value
;
2636 int result
= aice_read_misc(coreid
, NDS_EDM_MISC_DBGER
, &dbger_value
);
2638 if (ERROR_AICE_TIMEOUT
== result
) {
2639 if (aice_read_ctrl(AICE_READ_CTRL_GET_ICE_STATE
, &ice_state
) != ERROR_OK
) {
2640 LOG_ERROR("<-- AICE ERROR! AICE is unplugged. -->");
2644 if ((ice_state
& 0x20) == 0) {
2645 LOG_ERROR("<-- TARGET ERROR! Target is disconnected with AICE. -->");
2650 } else if (ERROR_AICE_DISCONNECT
== result
) {
2651 LOG_ERROR("<-- AICE ERROR! AICE is unplugged. -->");
2655 if ((dbger_value
& NDS_DBGER_ILL_SEC_ACC
) == NDS_DBGER_ILL_SEC_ACC
) {
2656 LOG_ERROR("<-- TARGET ERROR! Insufficient security privilege. -->");
2658 /* Clear ILL_SEC_ACC */
2659 aice_write_misc(coreid
, NDS_EDM_MISC_DBGER
, NDS_DBGER_ILL_SEC_ACC
);
2661 *state
= AICE_TARGET_RUNNING
;
2662 core_info
[coreid
].core_state
= AICE_TARGET_RUNNING
;
2663 } else if ((dbger_value
& NDS_DBGER_AT_MAX
) == NDS_DBGER_AT_MAX
) {
2664 /* Issue DBGI to exit cpu stall */
2665 aice_usb_halt(coreid
);
2667 /* Read OIPC to find out the trigger point */
2668 uint32_t ir11_value
;
2669 aice_read_reg(coreid
, IR11
, &ir11_value
);
2671 LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level; "
2672 "CPU is stalled at 0x%08x for debugging. -->", ir11_value
);
2674 *state
= AICE_TARGET_HALTED
;
2675 } else if ((dbger_value
& NDS_DBGER_CRST
) == NDS_DBGER_CRST
) {
2676 LOG_DEBUG("DBGER.CRST is on.");
2678 *state
= AICE_TARGET_RESET
;
2679 core_info
[coreid
].core_state
= AICE_TARGET_RUNNING
;
2682 aice_write_misc(coreid
, NDS_EDM_MISC_DBGER
, NDS_DBGER_CRST
);
2683 } else if ((dbger_value
& NDS_DBGER_DEX
) == NDS_DBGER_DEX
) {
2684 if (AICE_TARGET_RUNNING
== core_info
[coreid
].core_state
) {
2685 /* enter debug mode, init EDM registers */
2686 /* backup EDM registers */
2687 aice_backup_edm_registers(coreid
);
2688 /* init EDM for host debugging */
2689 aice_init_edm_registers(coreid
, true);
2690 aice_backup_tmp_registers(coreid
);
2691 core_info
[coreid
].core_state
= AICE_TARGET_HALTED
;
2692 } else if (AICE_TARGET_UNKNOWN
== core_info
[coreid
].core_state
) {
2693 /* debug 'debug mode', use force debug to halt core */
2694 aice_usb_halt(coreid
);
2696 *state
= AICE_TARGET_HALTED
;
2698 *state
= AICE_TARGET_RUNNING
;
2699 core_info
[coreid
].core_state
= AICE_TARGET_RUNNING
;
2705 static int aice_usb_reset(void)
2707 if (aice_reset_box() != ERROR_OK
)
2711 if (custom_trst_script
== NULL
) {
2712 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL
,
2713 AICE_JTAG_PIN_CONTROL_TRST
) != ERROR_OK
)
2716 /* custom trst operations */
2717 if (aice_execute_custom_script(custom_trst_script
) != ERROR_OK
)
2721 if (aice_usb_set_clock(jtag_clock
) != ERROR_OK
)
2727 static int aice_issue_srst(uint32_t coreid
)
2729 LOG_DEBUG("aice_issue_srst");
2731 /* After issuing srst, target will be running. So we need to restore EDM_CTL. */
2732 aice_restore_edm_registers(coreid
);
2734 if (custom_srst_script
== NULL
) {
2735 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL
,
2736 AICE_JTAG_PIN_CONTROL_SRST
) != ERROR_OK
)
2739 /* custom srst operations */
2740 if (aice_execute_custom_script(custom_srst_script
) != ERROR_OK
)
2744 /* wait CRST infinitely */
2745 uint32_t dbger_value
;
2748 if (aice_read_misc(coreid
,
2749 NDS_EDM_MISC_DBGER
, &dbger_value
) != ERROR_OK
)
2752 if (dbger_value
& NDS_DBGER_CRST
)
2760 core_info
[coreid
].host_dtr_valid
= false;
2761 core_info
[coreid
].target_dtr_valid
= false;
2763 core_info
[coreid
].core_state
= AICE_TARGET_RUNNING
;
2767 static int aice_issue_reset_hold(uint32_t coreid
)
2769 LOG_DEBUG("aice_issue_reset_hold");
2771 /* set no_dbgi_pin to 0 */
2772 uint32_t pin_status
;
2773 aice_read_ctrl(AICE_READ_CTRL_GET_JTAG_PIN_STATUS
, &pin_status
);
2774 if (pin_status
| 0x4)
2775 aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_STATUS
, pin_status
& (~0x4));
2778 if (custom_restart_script
== NULL
) {
2779 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL
,
2780 AICE_JTAG_PIN_CONTROL_RESTART
) != ERROR_OK
)
2783 /* custom restart operations */
2784 if (aice_execute_custom_script(custom_restart_script
) != ERROR_OK
)
2788 if (aice_check_dbger(coreid
, NDS_DBGER_CRST
| NDS_DBGER_DEX
) == ERROR_OK
) {
2789 aice_backup_tmp_registers(coreid
);
2790 core_info
[coreid
].core_state
= AICE_TARGET_HALTED
;
2794 /* set no_dbgi_pin to 1 */
2795 aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_STATUS
, pin_status
| 0x4);
2797 /* issue restart again */
2798 if (custom_restart_script
== NULL
) {
2799 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL
,
2800 AICE_JTAG_PIN_CONTROL_RESTART
) != ERROR_OK
)
2803 /* custom restart operations */
2804 if (aice_execute_custom_script(custom_restart_script
) != ERROR_OK
)
2808 if (aice_check_dbger(coreid
, NDS_DBGER_CRST
| NDS_DBGER_DEX
) == ERROR_OK
) {
2809 aice_backup_tmp_registers(coreid
);
2810 core_info
[coreid
].core_state
= AICE_TARGET_HALTED
;
2815 /* do software reset-and-hold */
2816 aice_issue_srst(coreid
);
2817 aice_usb_halt(coreid
);
2820 aice_read_reg(coreid
, IR3
, &value_ir3
);
2821 aice_write_reg(coreid
, PC
, value_ir3
& 0xFFFF0000);
2827 static int aice_issue_reset_hold_multi(void)
2829 uint32_t write_ctrl_value
= 0;
2832 write_ctrl_value
= AICE_CUSTOM_DELAY_SET_SRST
;
2833 write_ctrl_value
|= (0x200 << 16);
2834 if (aice_write_ctrl(AICE_WRITE_CTRL_CUSTOM_DELAY
,
2835 write_ctrl_value
) != ERROR_OK
)
2838 for (uint8_t i
= 0 ; i
< total_num_of_core
; i
++)
2839 aice_write_misc(i
, NDS_EDM_MISC_EDM_CMDR
, 0);
2842 write_ctrl_value
= AICE_CUSTOM_DELAY_CLEAN_SRST
;
2843 write_ctrl_value
|= (0x200 << 16);
2844 if (aice_write_ctrl(AICE_WRITE_CTRL_CUSTOM_DELAY
,
2845 write_ctrl_value
) != ERROR_OK
)
2848 for (uint8_t i
= 0; i
< total_num_of_core
; i
++)
2854 static int aice_usb_assert_srst(uint32_t coreid
, enum aice_srst_type_s srst
)
2856 if ((AICE_SRST
!= srst
) && (AICE_RESET_HOLD
!= srst
))
2860 if (aice_write_misc(coreid
, NDS_EDM_MISC_DBGER
,
2861 NDS_DBGER_CLEAR_ALL
) != ERROR_OK
)
2864 int result
= ERROR_OK
;
2865 if (AICE_SRST
== srst
)
2866 result
= aice_issue_srst(coreid
);
2868 if (1 == total_num_of_core
)
2869 result
= aice_issue_reset_hold(coreid
);
2871 result
= aice_issue_reset_hold_multi();
2874 /* Clear DBGER.CRST after reset to avoid 'core-reset checking' errors.
2875 * assert_srst is user-intentional reset behavior, so we could
2876 * clear DBGER.CRST safely.
2878 if (aice_write_misc(coreid
,
2879 NDS_EDM_MISC_DBGER
, NDS_DBGER_CRST
) != ERROR_OK
)
2885 static int aice_usb_run(uint32_t coreid
)
2887 LOG_DEBUG("aice_usb_run");
2889 uint32_t dbger_value
;
2890 if (aice_read_misc(coreid
,
2891 NDS_EDM_MISC_DBGER
, &dbger_value
) != ERROR_OK
)
2894 if ((dbger_value
& NDS_DBGER_DEX
) != NDS_DBGER_DEX
) {
2895 LOG_WARNING("<-- TARGET WARNING! The debug target exited "
2896 "the debug mode unexpectedly. -->");
2900 /* restore r0 & r1 before free run */
2901 aice_restore_tmp_registers(coreid
);
2902 core_info
[coreid
].core_state
= AICE_TARGET_RUNNING
;
2905 aice_write_misc(coreid
, NDS_EDM_MISC_DBGER
,
2906 NDS_DBGER_CLEAR_ALL
);
2908 /** restore EDM registers */
2909 /** OpenOCD should restore EDM_CTL **before** to exit debug state.
2910 * Otherwise, following instruction will read wrong EDM_CTL value.
2912 * pc -> mfsr $p0, EDM_CTL (single step)
2916 aice_restore_edm_registers(coreid
);
2918 /** execute instructions in DIM */
2919 uint32_t instructions
[4] = {
2925 int result
= aice_execute_dim(coreid
, instructions
, 4);
2930 static int aice_usb_step(uint32_t coreid
)
2932 LOG_DEBUG("aice_usb_step");
2935 uint32_t ir0_reg_num
;
2937 if (is_v2_edm(coreid
) == true)
2938 /* V2 EDM will push interrupt stack as debug exception */
2944 aice_read_reg(coreid
, ir0_reg_num
, &ir0_value
);
2945 if ((ir0_value
& 0x800) == 0) {
2947 ir0_value
|= (0x01 << 11);
2948 aice_write_reg(coreid
, ir0_reg_num
, ir0_value
);
2951 if (ERROR_FAIL
== aice_usb_run(coreid
))
2955 enum aice_target_state_s state
;
2958 if (aice_usb_state(coreid
, &state
) != ERROR_OK
)
2961 if (AICE_TARGET_HALTED
== state
)
2966 then
= timeval_ms();
2969 if ((timeval_ms() - then
) > 1000)
2970 LOG_WARNING("Timeout (1000ms) waiting for halt to complete");
2978 aice_read_reg(coreid
, ir0_reg_num
, &ir0_value
);
2979 ir0_value
&= ~(0x01 << 11);
2980 aice_write_reg(coreid
, ir0_reg_num
, ir0_value
);
2985 static int aice_usb_read_mem_b_bus(uint32_t coreid
, uint32_t address
, uint32_t *data
)
2987 return aice_read_mem_b(coreid
, address
, data
);
2990 static int aice_usb_read_mem_h_bus(uint32_t coreid
, uint32_t address
, uint32_t *data
)
2992 return aice_read_mem_h(coreid
, address
, data
);
2995 static int aice_usb_read_mem_w_bus(uint32_t coreid
, uint32_t address
, uint32_t *data
)
2997 return aice_read_mem(coreid
, address
, data
);
3000 static int aice_usb_read_mem_b_dim(uint32_t coreid
, uint32_t address
, uint32_t *data
)
3003 uint32_t instructions
[4] = {
3010 aice_execute_dim(coreid
, instructions
, 4);
3012 aice_read_dtr(coreid
, &value
);
3013 *data
= value
& 0xFF;
3018 static int aice_usb_read_mem_h_dim(uint32_t coreid
, uint32_t address
, uint32_t *data
)
3021 uint32_t instructions
[4] = {
3028 aice_execute_dim(coreid
, instructions
, 4);
3030 aice_read_dtr(coreid
, &value
);
3031 *data
= value
& 0xFFFF;
3036 static int aice_usb_read_mem_w_dim(uint32_t coreid
, uint32_t address
, uint32_t *data
)
3038 uint32_t instructions
[4] = {
3045 aice_execute_dim(coreid
, instructions
, 4);
3047 aice_read_dtr(coreid
, data
);
3052 static int aice_usb_set_address_dim(uint32_t coreid
, uint32_t address
)
3054 uint32_t instructions
[4] = {
3055 SETHI(R0
, address
>> 12),
3056 ORI(R0
, R0
, address
& 0x00000FFF),
3061 return aice_execute_dim(coreid
, instructions
, 4);
3064 static int aice_usb_read_memory_unit(uint32_t coreid
, uint32_t addr
, uint32_t size
,
3065 uint32_t count
, uint8_t *buffer
)
3067 LOG_DEBUG("aice_usb_read_memory_unit, addr: 0x%08x, size: %d, count: %d",
3070 if (NDS_MEMORY_ACC_CPU
== core_info
[coreid
].access_channel
)
3071 aice_usb_set_address_dim(coreid
, addr
);
3075 read_mem_func_t read_mem_func
;
3079 if (NDS_MEMORY_ACC_BUS
== core_info
[coreid
].access_channel
)
3080 read_mem_func
= aice_usb_read_mem_b_bus
;
3082 read_mem_func
= aice_usb_read_mem_b_dim
;
3084 for (i
= 0; i
< count
; i
++) {
3085 read_mem_func(coreid
, addr
, &value
);
3086 *buffer
++ = (uint8_t)value
;
3091 if (NDS_MEMORY_ACC_BUS
== core_info
[coreid
].access_channel
)
3092 read_mem_func
= aice_usb_read_mem_h_bus
;
3094 read_mem_func
= aice_usb_read_mem_h_dim
;
3096 for (i
= 0; i
< count
; i
++) {
3097 read_mem_func(coreid
, addr
, &value
);
3098 uint16_t svalue
= value
;
3099 memcpy(buffer
, &svalue
, sizeof(uint16_t));
3105 if (NDS_MEMORY_ACC_BUS
== core_info
[coreid
].access_channel
)
3106 read_mem_func
= aice_usb_read_mem_w_bus
;
3108 read_mem_func
= aice_usb_read_mem_w_dim
;
3110 for (i
= 0; i
< count
; i
++) {
3111 read_mem_func(coreid
, addr
, &value
);
3112 memcpy(buffer
, &value
, sizeof(uint32_t));
3122 static int aice_usb_write_mem_b_bus(uint32_t coreid
, uint32_t address
, uint32_t data
)
3124 return aice_write_mem_b(coreid
, address
, data
);
3127 static int aice_usb_write_mem_h_bus(uint32_t coreid
, uint32_t address
, uint32_t data
)
3129 return aice_write_mem_h(coreid
, address
, data
);
3132 static int aice_usb_write_mem_w_bus(uint32_t coreid
, uint32_t address
, uint32_t data
)
3134 return aice_write_mem(coreid
, address
, data
);
3137 static int aice_usb_write_mem_b_dim(uint32_t coreid
, uint32_t address
, uint32_t data
)
3139 uint32_t instructions
[4] = {
3146 aice_write_dtr(coreid
, data
& 0xFF);
3147 aice_execute_dim(coreid
, instructions
, 4);
3152 static int aice_usb_write_mem_h_dim(uint32_t coreid
, uint32_t address
, uint32_t data
)
3154 uint32_t instructions
[4] = {
3161 aice_write_dtr(coreid
, data
& 0xFFFF);
3162 aice_execute_dim(coreid
, instructions
, 4);
3167 static int aice_usb_write_mem_w_dim(uint32_t coreid
, uint32_t address
, uint32_t data
)
3169 uint32_t instructions
[4] = {
3176 aice_write_dtr(coreid
, data
);
3177 aice_execute_dim(coreid
, instructions
, 4);
3182 static int aice_usb_write_memory_unit(uint32_t coreid
, uint32_t addr
, uint32_t size
,
3183 uint32_t count
, const uint8_t *buffer
)
3185 LOG_DEBUG("aice_usb_write_memory_unit, addr: 0x%08x, size: %d, count: %d",
3188 if (NDS_MEMORY_ACC_CPU
== core_info
[coreid
].access_channel
)
3189 aice_usb_set_address_dim(coreid
, addr
);
3192 write_mem_func_t write_mem_func
;
3196 if (NDS_MEMORY_ACC_BUS
== core_info
[coreid
].access_channel
)
3197 write_mem_func
= aice_usb_write_mem_b_bus
;
3199 write_mem_func
= aice_usb_write_mem_b_dim
;
3201 for (i
= 0; i
< count
; i
++) {
3202 write_mem_func(coreid
, addr
, *buffer
);
3208 if (NDS_MEMORY_ACC_BUS
== core_info
[coreid
].access_channel
)
3209 write_mem_func
= aice_usb_write_mem_h_bus
;
3211 write_mem_func
= aice_usb_write_mem_h_dim
;
3213 for (i
= 0; i
< count
; i
++) {
3215 memcpy(&value
, buffer
, sizeof(uint16_t));
3217 write_mem_func(coreid
, addr
, value
);
3223 if (NDS_MEMORY_ACC_BUS
== core_info
[coreid
].access_channel
)
3224 write_mem_func
= aice_usb_write_mem_w_bus
;
3226 write_mem_func
= aice_usb_write_mem_w_dim
;
3228 for (i
= 0; i
< count
; i
++) {
3230 memcpy(&value
, buffer
, sizeof(uint32_t));
3232 write_mem_func(coreid
, addr
, value
);
3242 static int aice_bulk_read_mem(uint32_t coreid
, uint32_t addr
, uint32_t count
,
3245 uint32_t packet_size
;
3248 packet_size
= (count
>= 0x100) ? 0x100 : count
;
3252 if (aice_write_misc(coreid
, NDS_EDM_MISC_SBAR
, addr
) != ERROR_OK
)
3255 if (aice_fastread_mem(coreid
, buffer
,
3256 packet_size
) != ERROR_OK
)
3259 buffer
+= (packet_size
* 4);
3260 addr
+= (packet_size
* 4);
3261 count
-= packet_size
;
3267 static int aice_bulk_write_mem(uint32_t coreid
, uint32_t addr
, uint32_t count
,
3268 const uint8_t *buffer
)
3270 uint32_t packet_size
;
3273 packet_size
= (count
>= 0x100) ? 0x100 : count
;
3277 if (aice_write_misc(coreid
, NDS_EDM_MISC_SBAR
, addr
| 1) != ERROR_OK
)
3280 if (aice_fastwrite_mem(coreid
, buffer
,
3281 packet_size
) != ERROR_OK
)
3284 buffer
+= (packet_size
* 4);
3285 addr
+= (packet_size
* 4);
3286 count
-= packet_size
;
3292 static int aice_usb_bulk_read_mem(uint32_t coreid
, uint32_t addr
,
3293 uint32_t length
, uint8_t *buffer
)
3295 LOG_DEBUG("aice_usb_bulk_read_mem, addr: 0x%08x, length: 0x%08x", addr
, length
);
3299 if (NDS_MEMORY_ACC_CPU
== core_info
[coreid
].access_channel
)
3300 aice_usb_set_address_dim(coreid
, addr
);
3302 if (NDS_MEMORY_ACC_CPU
== core_info
[coreid
].access_channel
)
3303 retval
= aice_usb_read_memory_unit(coreid
, addr
, 4, length
/ 4, buffer
);
3305 retval
= aice_bulk_read_mem(coreid
, addr
, length
/ 4, buffer
);
3310 static int aice_usb_bulk_write_mem(uint32_t coreid
, uint32_t addr
,
3311 uint32_t length
, const uint8_t *buffer
)
3313 LOG_DEBUG("aice_usb_bulk_write_mem, addr: 0x%08x, length: 0x%08x", addr
, length
);
3317 if (NDS_MEMORY_ACC_CPU
== core_info
[coreid
].access_channel
)
3318 aice_usb_set_address_dim(coreid
, addr
);
3320 if (NDS_MEMORY_ACC_CPU
== core_info
[coreid
].access_channel
)
3321 retval
= aice_usb_write_memory_unit(coreid
, addr
, 4, length
/ 4, buffer
);
3323 retval
= aice_bulk_write_mem(coreid
, addr
, length
/ 4, buffer
);
3328 static int aice_usb_read_debug_reg(uint32_t coreid
, uint32_t addr
, uint32_t *val
)
3330 if (AICE_TARGET_HALTED
== core_info
[coreid
].core_state
) {
3331 if (NDS_EDM_SR_EDMSW
== addr
) {
3332 *val
= core_info
[coreid
].edmsw_backup
;
3333 } else if (NDS_EDM_SR_EDM_DTR
== addr
) {
3334 if (core_info
[coreid
].target_dtr_valid
) {
3335 /* if EDM_DTR has read out, clear it. */
3336 *val
= core_info
[coreid
].target_dtr_backup
;
3337 core_info
[coreid
].edmsw_backup
&= (~0x1);
3338 core_info
[coreid
].target_dtr_valid
= false;
3345 return aice_read_edmsr(coreid
, addr
, val
);
3348 static int aice_usb_write_debug_reg(uint32_t coreid
, uint32_t addr
, const uint32_t val
)
3350 if (AICE_TARGET_HALTED
== core_info
[coreid
].core_state
) {
3351 if (NDS_EDM_SR_EDM_DTR
== addr
) {
3352 core_info
[coreid
].host_dtr_backup
= val
;
3353 core_info
[coreid
].edmsw_backup
|= 0x2;
3354 core_info
[coreid
].host_dtr_valid
= true;
3358 return aice_write_edmsr(coreid
, addr
, val
);
3361 static int aice_usb_memory_access(uint32_t coreid
, enum nds_memory_access channel
)
3363 LOG_DEBUG("aice_usb_memory_access, access channel: %d", channel
);
3365 core_info
[coreid
].access_channel
= channel
;
3370 static int aice_usb_memory_mode(uint32_t coreid
, enum nds_memory_select mem_select
)
3372 if (core_info
[coreid
].memory_select
== mem_select
)
3375 LOG_DEBUG("aice_usb_memory_mode, memory select: %d", mem_select
);
3377 core_info
[coreid
].memory_select
= mem_select
;
3379 if (NDS_MEMORY_SELECT_AUTO
!= core_info
[coreid
].memory_select
)
3380 aice_write_misc(coreid
, NDS_EDM_MISC_ACC_CTL
,
3381 core_info
[coreid
].memory_select
- 1);
3383 aice_write_misc(coreid
, NDS_EDM_MISC_ACC_CTL
,
3384 NDS_MEMORY_SELECT_MEM
- 1);
3389 static int aice_usb_read_tlb(uint32_t coreid
, uint32_t virtual_address
,
3390 uint32_t *physical_address
)
3392 LOG_DEBUG("aice_usb_read_tlb, virtual address: 0x%08x", virtual_address
);
3394 uint32_t instructions
[4];
3395 uint32_t probe_result
;
3398 uint32_t access_page_size
;
3399 uint32_t virtual_offset
;
3400 uint32_t physical_page_number
;
3402 aice_write_dtr(coreid
, virtual_address
);
3404 /* probe TLB first */
3405 instructions
[0] = MFSR_DTR(R0
);
3406 instructions
[1] = TLBOP_TARGET_PROBE(R1
, R0
);
3407 instructions
[2] = DSB
;
3408 instructions
[3] = BEQ_MINUS_12
;
3409 aice_execute_dim(coreid
, instructions
, 4);
3411 aice_read_reg(coreid
, R1
, &probe_result
);
3413 if (probe_result
& 0x80000000)
3416 /* read TLB entry */
3417 aice_write_dtr(coreid
, probe_result
& 0x7FF);
3419 /* probe TLB first */
3420 instructions
[0] = MFSR_DTR(R0
);
3421 instructions
[1] = TLBOP_TARGET_READ(R0
);
3422 instructions
[2] = DSB
;
3423 instructions
[3] = BEQ_MINUS_12
;
3424 aice_execute_dim(coreid
, instructions
, 4);
3426 /* TODO: it should backup mr3, mr4 */
3427 aice_read_reg(coreid
, MR3
, &value_mr3
);
3428 aice_read_reg(coreid
, MR4
, &value_mr4
);
3430 access_page_size
= value_mr4
& 0xF;
3431 if (0 == access_page_size
) { /* 4K page */
3432 virtual_offset
= virtual_address
& 0x00000FFF;
3433 physical_page_number
= value_mr3
& 0xFFFFF000;
3434 } else if (1 == access_page_size
) { /* 8K page */
3435 virtual_offset
= virtual_address
& 0x00001FFF;
3436 physical_page_number
= value_mr3
& 0xFFFFE000;
3437 } else if (5 == access_page_size
) { /* 1M page */
3438 virtual_offset
= virtual_address
& 0x000FFFFF;
3439 physical_page_number
= value_mr3
& 0xFFF00000;
3444 *physical_address
= physical_page_number
| virtual_offset
;
3449 static int aice_usb_init_cache(uint32_t coreid
)
3451 LOG_DEBUG("aice_usb_init_cache");
3456 aice_read_reg(coreid
, CR1
, &value_cr1
);
3457 aice_read_reg(coreid
, CR2
, &value_cr2
);
3459 struct cache_info
*icache
= &core_info
[coreid
].icache
;
3461 icache
->set
= value_cr1
& 0x7;
3462 icache
->log2_set
= icache
->set
+ 6;
3463 icache
->set
= 64 << icache
->set
;
3464 icache
->way
= ((value_cr1
>> 3) & 0x7) + 1;
3465 icache
->line_size
= (value_cr1
>> 6) & 0x7;
3466 if (icache
->line_size
!= 0) {
3467 icache
->log2_line_size
= icache
->line_size
+ 2;
3468 icache
->line_size
= 8 << (icache
->line_size
- 1);
3470 icache
->log2_line_size
= 0;
3473 LOG_DEBUG("\ticache set: %d, way: %d, line size: %d, "
3474 "log2(set): %d, log2(line_size): %d",
3475 icache
->set
, icache
->way
, icache
->line_size
,
3476 icache
->log2_set
, icache
->log2_line_size
);
3478 struct cache_info
*dcache
= &core_info
[coreid
].dcache
;
3480 dcache
->set
= value_cr2
& 0x7;
3481 dcache
->log2_set
= dcache
->set
+ 6;
3482 dcache
->set
= 64 << dcache
->set
;
3483 dcache
->way
= ((value_cr2
>> 3) & 0x7) + 1;
3484 dcache
->line_size
= (value_cr2
>> 6) & 0x7;
3485 if (dcache
->line_size
!= 0) {
3486 dcache
->log2_line_size
= dcache
->line_size
+ 2;
3487 dcache
->line_size
= 8 << (dcache
->line_size
- 1);
3489 dcache
->log2_line_size
= 0;
3492 LOG_DEBUG("\tdcache set: %d, way: %d, line size: %d, "
3493 "log2(set): %d, log2(line_size): %d",
3494 dcache
->set
, dcache
->way
, dcache
->line_size
,
3495 dcache
->log2_set
, dcache
->log2_line_size
);
3497 core_info
[coreid
].cache_init
= true;
3502 static int aice_usb_dcache_inval_all(uint32_t coreid
)
3504 LOG_DEBUG("aice_usb_dcache_inval_all");
3508 uint32_t cache_index
;
3509 uint32_t instructions
[4];
3511 instructions
[0] = MFSR_DTR(R0
);
3512 instructions
[1] = L1D_IX_INVAL(R0
);
3513 instructions
[2] = DSB
;
3514 instructions
[3] = BEQ_MINUS_12
;
3516 struct cache_info
*dcache
= &core_info
[coreid
].dcache
;
3518 for (set_index
= 0; set_index
< dcache
->set
; set_index
++) {
3519 for (way_index
= 0; way_index
< dcache
->way
; way_index
++) {
3520 cache_index
= (way_index
<< (dcache
->log2_set
+ dcache
->log2_line_size
)) |
3521 (set_index
<< dcache
->log2_line_size
);
3523 if (ERROR_OK
!= aice_write_dtr(coreid
, cache_index
))
3526 if (ERROR_OK
!= aice_execute_dim(coreid
, instructions
, 4))
3534 static int aice_usb_dcache_va_inval(uint32_t coreid
, uint32_t address
)
3536 LOG_DEBUG("aice_usb_dcache_va_inval");
3538 uint32_t instructions
[4];
3540 aice_write_dtr(coreid
, address
);
3542 instructions
[0] = MFSR_DTR(R0
);
3543 instructions
[1] = L1D_VA_INVAL(R0
);
3544 instructions
[2] = DSB
;
3545 instructions
[3] = BEQ_MINUS_12
;
3547 return aice_execute_dim(coreid
, instructions
, 4);
3550 static int aice_usb_dcache_wb_all(uint32_t coreid
)
3552 LOG_DEBUG("aice_usb_dcache_wb_all");
3556 uint32_t cache_index
;
3557 uint32_t instructions
[4];
3559 instructions
[0] = MFSR_DTR(R0
);
3560 instructions
[1] = L1D_IX_WB(R0
);
3561 instructions
[2] = DSB
;
3562 instructions
[3] = BEQ_MINUS_12
;
3564 struct cache_info
*dcache
= &core_info
[coreid
].dcache
;
3566 for (set_index
= 0; set_index
< dcache
->set
; set_index
++) {
3567 for (way_index
= 0; way_index
< dcache
->way
; way_index
++) {
3568 cache_index
= (way_index
<< (dcache
->log2_set
+ dcache
->log2_line_size
)) |
3569 (set_index
<< dcache
->log2_line_size
);
3571 if (ERROR_OK
!= aice_write_dtr(coreid
, cache_index
))
3574 if (ERROR_OK
!= aice_execute_dim(coreid
, instructions
, 4))
3582 static int aice_usb_dcache_va_wb(uint32_t coreid
, uint32_t address
)
3584 LOG_DEBUG("aice_usb_dcache_va_wb");
3586 uint32_t instructions
[4];
3588 aice_write_dtr(coreid
, address
);
3590 instructions
[0] = MFSR_DTR(R0
);
3591 instructions
[1] = L1D_VA_WB(R0
);
3592 instructions
[2] = DSB
;
3593 instructions
[3] = BEQ_MINUS_12
;
3595 return aice_execute_dim(coreid
, instructions
, 4);
3598 static int aice_usb_icache_inval_all(uint32_t coreid
)
3600 LOG_DEBUG("aice_usb_icache_inval_all");
3604 uint32_t cache_index
;
3605 uint32_t instructions
[4];
3607 instructions
[0] = MFSR_DTR(R0
);
3608 instructions
[1] = L1I_IX_INVAL(R0
);
3609 instructions
[2] = ISB
;
3610 instructions
[3] = BEQ_MINUS_12
;
3612 struct cache_info
*icache
= &core_info
[coreid
].icache
;
3614 for (set_index
= 0; set_index
< icache
->set
; set_index
++) {
3615 for (way_index
= 0; way_index
< icache
->way
; way_index
++) {
3616 cache_index
= (way_index
<< (icache
->log2_set
+ icache
->log2_line_size
)) |
3617 (set_index
<< icache
->log2_line_size
);
3619 if (ERROR_OK
!= aice_write_dtr(coreid
, cache_index
))
3622 if (ERROR_OK
!= aice_execute_dim(coreid
, instructions
, 4))
3630 static int aice_usb_icache_va_inval(uint32_t coreid
, uint32_t address
)
3632 LOG_DEBUG("aice_usb_icache_va_inval");
3634 uint32_t instructions
[4];
3636 aice_write_dtr(coreid
, address
);
3638 instructions
[0] = MFSR_DTR(R0
);
3639 instructions
[1] = L1I_VA_INVAL(R0
);
3640 instructions
[2] = ISB
;
3641 instructions
[3] = BEQ_MINUS_12
;
3643 return aice_execute_dim(coreid
, instructions
, 4);
3646 static int aice_usb_cache_ctl(uint32_t coreid
, uint32_t subtype
, uint32_t address
)
3648 LOG_DEBUG("aice_usb_cache_ctl");
3652 if (core_info
[coreid
].cache_init
== false)
3653 aice_usb_init_cache(coreid
);
3656 case AICE_CACHE_CTL_L1D_INVALALL
:
3657 result
= aice_usb_dcache_inval_all(coreid
);
3659 case AICE_CACHE_CTL_L1D_VA_INVAL
:
3660 result
= aice_usb_dcache_va_inval(coreid
, address
);
3662 case AICE_CACHE_CTL_L1D_WBALL
:
3663 result
= aice_usb_dcache_wb_all(coreid
);
3665 case AICE_CACHE_CTL_L1D_VA_WB
:
3666 result
= aice_usb_dcache_va_wb(coreid
, address
);
3668 case AICE_CACHE_CTL_L1I_INVALALL
:
3669 result
= aice_usb_icache_inval_all(coreid
);
3671 case AICE_CACHE_CTL_L1I_VA_INVAL
:
3672 result
= aice_usb_icache_va_inval(coreid
, address
);
3675 result
= ERROR_FAIL
;
3682 static int aice_usb_set_retry_times(uint32_t a_retry_times
)
3684 aice_max_retry_times
= a_retry_times
;
3688 static int aice_usb_program_edm(uint32_t coreid
, char *command_sequence
)
3693 uint32_t data_value
;
3697 command_str
= strtok(command_sequence
, ";");
3698 if (command_str
== NULL
)
3703 /* process one command */
3704 while (command_str
[i
] == ' ' ||
3705 command_str
[i
] == '\n' ||
3706 command_str
[i
] == '\r' ||
3707 command_str
[i
] == '\t')
3710 /* skip ' ', '\r', '\n', '\t' */
3711 command_str
= command_str
+ i
;
3713 if (strncmp(command_str
, "write_misc", 10) == 0) {
3714 reg_name_0
= strstr(command_str
, "gen_port0");
3715 reg_name_1
= strstr(command_str
, "gen_port1");
3717 if (reg_name_0
!= NULL
) {
3718 data_value
= strtoul(reg_name_0
+ 9, NULL
, 0);
3720 if (aice_write_misc(coreid
,
3721 NDS_EDM_MISC_GEN_PORT0
, data_value
) != ERROR_OK
)
3724 } else if (reg_name_1
!= NULL
) {
3725 data_value
= strtoul(reg_name_1
+ 9, NULL
, 0);
3727 if (aice_write_misc(coreid
,
3728 NDS_EDM_MISC_GEN_PORT1
, data_value
) != ERROR_OK
)
3731 LOG_ERROR("program EDM, unsupported misc register: %s", command_str
);
3734 LOG_ERROR("program EDM, unsupported command: %s", command_str
);
3737 /* update command_str */
3738 command_str
= strtok(NULL
, ";");
3740 } while (command_str
!= NULL
);
3745 static int aice_usb_set_command_mode(enum aice_command_mode command_mode
)
3747 int retval
= ERROR_OK
;
3749 /* flush usb_packets_buffer as users change mode */
3750 retval
= aice_usb_packet_flush();
3752 if (AICE_COMMAND_MODE_BATCH
== command_mode
) {
3753 /* reset batch buffer */
3754 aice_command_mode
= AICE_COMMAND_MODE_NORMAL
;
3755 retval
= aice_write_ctrl(AICE_WRITE_CTRL_BATCH_CMD_BUF0_CTRL
, 0x40000);
3758 aice_command_mode
= command_mode
;
3763 static int aice_usb_execute(uint32_t coreid
, uint32_t *instructions
,
3764 uint32_t instruction_num
)
3767 uint8_t current_instruction_num
;
3768 uint32_t dim_instructions
[4] = {NOP
, NOP
, NOP
, BEQ_MINUS_12
};
3770 /* To execute 4 instructions as a special case */
3771 if (instruction_num
== 4)
3772 return aice_execute_dim(coreid
, instructions
, 4);
3774 for (i
= 0 ; i
< instruction_num
; i
+= 3) {
3775 if (instruction_num
- i
< 3) {
3776 current_instruction_num
= instruction_num
- i
;
3777 for (j
= current_instruction_num
; j
< 3 ; j
++)
3778 dim_instructions
[j
] = NOP
;
3780 current_instruction_num
= 3;
3783 memcpy(dim_instructions
, instructions
+ i
,
3784 current_instruction_num
* sizeof(uint32_t));
3787 if (aice_write_dim(coreid
,
3792 /** clear DBGER.DPED */
3793 if (aice_write_misc(coreid
,
3794 NDS_EDM_MISC_DBGER
, NDS_DBGER_DPED
) != ERROR_OK
)
3798 if (aice_do_execute(coreid
) != ERROR_OK
)
3801 /** check DBGER.DPED */
3802 if (aice_check_dbger(coreid
, NDS_DBGER_DPED
) != ERROR_OK
) {
3804 LOG_ERROR("<-- TARGET ERROR! Debug operations do not finish properly:"
3805 "0x%08x 0x%08x 0x%08x 0x%08x. -->",
3806 dim_instructions
[0],
3807 dim_instructions
[1],
3808 dim_instructions
[2],
3809 dim_instructions
[3]);
3817 static int aice_usb_set_custom_srst_script(const char *script
)
3819 custom_srst_script
= strdup(script
);
3824 static int aice_usb_set_custom_trst_script(const char *script
)
3826 custom_trst_script
= strdup(script
);
3831 static int aice_usb_set_custom_restart_script(const char *script
)
3833 custom_restart_script
= strdup(script
);
3838 static int aice_usb_set_count_to_check_dbger(uint32_t count_to_check
)
3840 aice_count_to_check_dbger
= count_to_check
;
3845 static int aice_usb_set_data_endian(uint32_t coreid
,
3846 enum aice_target_endian target_data_endian
)
3848 data_endian
= target_data_endian
;
3853 static int fill_profiling_batch_commands(uint32_t coreid
, uint32_t reg_no
)
3855 uint32_t dim_instructions
[4];
3857 aice_usb_set_command_mode(AICE_COMMAND_MODE_BATCH
);
3860 if (aice_write_misc(coreid
, NDS_EDM_MISC_EDM_CMDR
, 0) != ERROR_OK
)
3864 dim_instructions
[0] = MTSR_DTR(0);
3865 dim_instructions
[1] = DSB
;
3866 dim_instructions
[2] = NOP
;
3867 dim_instructions
[3] = BEQ_MINUS_12
;
3868 if (aice_write_dim(coreid
, dim_instructions
, 4) != ERROR_OK
)
3870 aice_read_dtr_to_buffer(coreid
, AICE_BATCH_DATA_BUFFER_0
);
3873 if (NDS32_REG_TYPE_GPR
== nds32_reg_type(reg_no
)) {
3874 /* general registers */
3875 dim_instructions
[0] = MTSR_DTR(reg_no
);
3876 dim_instructions
[1] = DSB
;
3877 dim_instructions
[2] = NOP
;
3878 dim_instructions
[3] = BEQ_MINUS_12
;
3879 } else if (NDS32_REG_TYPE_SPR
== nds32_reg_type(reg_no
)) {
3880 /* user special registers */
3881 dim_instructions
[0] = MFUSR_G0(0, nds32_reg_sr_index(reg_no
));
3882 dim_instructions
[1] = MTSR_DTR(0);
3883 dim_instructions
[2] = DSB
;
3884 dim_instructions
[3] = BEQ_MINUS_12
;
3885 } else { /* system registers */
3886 dim_instructions
[0] = MFSR(0, nds32_reg_sr_index(reg_no
));
3887 dim_instructions
[1] = MTSR_DTR(0);
3888 dim_instructions
[2] = DSB
;
3889 dim_instructions
[3] = BEQ_MINUS_12
;
3891 if (aice_write_dim(coreid
, dim_instructions
, 4) != ERROR_OK
)
3893 aice_read_dtr_to_buffer(coreid
, AICE_BATCH_DATA_BUFFER_1
);
3896 aice_write_dtr_from_buffer(coreid
, AICE_BATCH_DATA_BUFFER_0
);
3897 dim_instructions
[0] = MFSR_DTR(0);
3898 dim_instructions
[1] = DSB
;
3899 dim_instructions
[2] = NOP
;
3900 dim_instructions
[3] = IRET
; /* free run */
3901 if (aice_write_dim(coreid
, dim_instructions
, 4) != ERROR_OK
)
3904 aice_command_mode
= AICE_COMMAND_MODE_NORMAL
;
3906 /* use BATCH_BUFFER_WRITE to fill command-batch-buffer */
3907 if (aice_batch_buffer_write(AICE_BATCH_COMMAND_BUFFER_0
,
3908 usb_out_packets_buffer
,
3909 (usb_out_packets_buffer_length
+ 3) / 4) != ERROR_OK
)
3912 usb_out_packets_buffer_length
= 0;
3913 usb_in_packets_buffer_length
= 0;
3918 static int aice_usb_profiling(uint32_t coreid
, uint32_t interval
, uint32_t iteration
,
3919 uint32_t reg_no
, uint32_t *samples
, uint32_t *num_samples
)
3921 uint32_t iteration_count
;
3922 uint32_t this_iteration
;
3923 int retval
= ERROR_OK
;
3924 const uint32_t MAX_ITERATION
= 250;
3929 if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_DIM_SIZE
, 4) != ERROR_OK
)
3932 /* Use AICE_BATCH_DATA_BUFFER_0 to read/write $DTR.
3933 * Set it to circular buffer */
3934 if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_DATA_BUF0_CTRL
, 0xC0000) != ERROR_OK
)
3937 fill_profiling_batch_commands(coreid
, reg_no
);
3939 iteration_count
= 0;
3940 while (iteration_count
< iteration
) {
3941 if (iteration
- iteration_count
< MAX_ITERATION
)
3942 this_iteration
= iteration
- iteration_count
;
3944 this_iteration
= MAX_ITERATION
;
3946 /* set number of iterations */
3947 uint32_t val_iteration
;
3948 val_iteration
= interval
<< 16 | this_iteration
;
3949 if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_ITERATION
,
3950 val_iteration
) != ERROR_OK
) {
3951 retval
= ERROR_FAIL
;
3955 /* init AICE_WRITE_CTRL_BATCH_DATA_BUF1_CTRL to store $PC */
3956 if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_DATA_BUF1_CTRL
,
3957 0x40000) != ERROR_OK
) {
3958 retval
= ERROR_FAIL
;
3962 aice_usb_run(coreid
);
3964 /* enable BATCH command */
3965 if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_CTRL
,
3966 0x80000000) != ERROR_OK
) {
3967 aice_usb_halt(coreid
);
3968 retval
= ERROR_FAIL
;
3972 /* wait a while (AICE bug, workaround) */
3973 alive_sleep(this_iteration
);
3977 uint32_t batch_status
;
3981 aice_read_ctrl(AICE_READ_CTRL_BATCH_STATUS
, &batch_status
);
3983 if (batch_status
& 0x1) {
3985 } else if (batch_status
& 0xE) {
3986 aice_usb_halt(coreid
);
3987 retval
= ERROR_FAIL
;
3997 aice_usb_halt(coreid
);
3999 /* get samples from batch data buffer */
4000 if (aice_batch_buffer_read(AICE_BATCH_DATA_BUFFER_1
,
4001 samples
+ iteration_count
, this_iteration
) != ERROR_OK
) {
4002 retval
= ERROR_FAIL
;
4006 iteration_count
+= this_iteration
;
4010 *num_samples
= iteration_count
;
4016 struct aice_port_api_s aice_usb_api
= {
4018 .open
= aice_open_device
,
4020 .close
= aice_usb_close
,
4022 .idcode
= aice_usb_idcode
,
4024 .state
= aice_usb_state
,
4026 .reset
= aice_usb_reset
,
4028 .assert_srst
= aice_usb_assert_srst
,
4030 .run
= aice_usb_run
,
4032 .halt
= aice_usb_halt
,
4034 .step
= aice_usb_step
,
4036 .read_reg
= aice_usb_read_reg
,
4038 .write_reg
= aice_usb_write_reg
,
4040 .read_reg_64
= aice_usb_read_reg_64
,
4042 .write_reg_64
= aice_usb_write_reg_64
,
4044 .read_mem_unit
= aice_usb_read_memory_unit
,
4046 .write_mem_unit
= aice_usb_write_memory_unit
,
4048 .read_mem_bulk
= aice_usb_bulk_read_mem
,
4050 .write_mem_bulk
= aice_usb_bulk_write_mem
,
4052 .read_debug_reg
= aice_usb_read_debug_reg
,
4054 .write_debug_reg
= aice_usb_write_debug_reg
,
4056 .set_jtag_clock
= aice_usb_set_jtag_clock
,
4058 .memory_access
= aice_usb_memory_access
,
4060 .memory_mode
= aice_usb_memory_mode
,
4062 .read_tlb
= aice_usb_read_tlb
,
4064 .cache_ctl
= aice_usb_cache_ctl
,
4066 .set_retry_times
= aice_usb_set_retry_times
,
4068 .program_edm
= aice_usb_program_edm
,
4070 .set_command_mode
= aice_usb_set_command_mode
,
4072 .execute
= aice_usb_execute
,
4074 .set_custom_srst_script
= aice_usb_set_custom_srst_script
,
4076 .set_custom_trst_script
= aice_usb_set_custom_trst_script
,
4078 .set_custom_restart_script
= aice_usb_set_custom_restart_script
,
4080 .set_count_to_check_dbger
= aice_usb_set_count_to_check_dbger
,
4082 .set_data_endian
= aice_usb_set_data_endian
,
4084 .profiling
= aice_usb_profiling
,