893ba38c5ce510c8dd726a1d102ae9fdaec8cc0b
[openocd.git] / src / jtag / aice / aice_usb.h
1 /***************************************************************************
2 * Copyright (C) 2013 by Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
18 #ifndef __AICE_USB_H__
19 #define __AICE_USB_H__
20
21 #include "aice_port.h"
22
23 /* AICE USB timeout value */
24 #define AICE_USB_TIMEOUT 5000
25
26 /* AICE USB buffer size */
27 #define AICE_IN_BUFFER_SIZE 2048
28 #define AICE_OUT_BUFFER_SIZE 2048
29 #define AICE_IN_PACKETS_BUFFER_SIZE 2048
30 #define AICE_OUT_PACKETS_BUFFER_SIZE 2048
31 #define AICE_IN_BATCH_COMMAND_SIZE 512
32 #define AICE_OUT_BATCH_COMMAND_SIZE 512
33 #define AICE_IN_PACK_COMMAND_SIZE 2048
34 #define AICE_OUT_PACK_COMMAND_SIZE 2048
35
36 /* Constants for AICE command READ_CTRL */
37 #define AICE_READ_CTRL_GET_ICE_STATE 0x00
38 #define AICE_READ_CTRL_GET_HARDWARE_VERSION 0x01
39 #define AICE_READ_CTRL_GET_FPGA_VERSION 0x02
40 #define AICE_READ_CTRL_GET_FIRMWARE_VERSION 0x03
41 #define AICE_READ_CTRL_GET_JTAG_PIN_STATUS 0x04
42 #define AICE_READ_CTRL_BATCH_BUF_INFO 0x22
43 #define AICE_READ_CTRL_BATCH_STATUS 0x23
44 #define AICE_READ_CTRL_BATCH_BUF0_STATE 0x31
45 #define AICE_READ_CTRL_BATCH_BUF4_STATE 0x39
46 #define AICE_READ_CTRL_BATCH_BUF5_STATE 0x3b
47
48 /* Constants for AICE command WRITE_CTRL */
49 #define AICE_WRITE_CTRL_TCK_CONTROL 0x00
50 #define AICE_WRITE_CTRL_JTAG_PIN_CONTROL 0x01
51 #define AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS 0x02
52 #define AICE_WRITE_CTRL_RESERVED 0x03
53 #define AICE_WRITE_CTRL_JTAG_PIN_STATUS 0x04
54 #define AICE_WRITE_CTRL_CUSTOM_DELAY 0x0d
55 #define AICE_WRITE_CTRL_BATCH_CTRL 0x20
56 #define AICE_WRITE_CTRL_BATCH_ITERATION 0x21
57 #define AICE_WRITE_CTRL_BATCH_DIM_SIZE 0x22
58 #define AICE_WRITE_CTRL_BATCH_CMD_BUF0_CTRL 0x30
59 #define AICE_WRITE_CTRL_BATCH_DATA_BUF0_CTRL 0x38
60 #define AICE_WRITE_CTRL_BATCH_DATA_BUF1_CTRL 0x3a
61
62 #define AICE_BATCH_COMMAND_BUFFER_0 0x0
63 #define AICE_BATCH_COMMAND_BUFFER_1 0x1
64 #define AICE_BATCH_COMMAND_BUFFER_2 0x2
65 #define AICE_BATCH_COMMAND_BUFFER_3 0x3
66 #define AICE_BATCH_DATA_BUFFER_0 0x4
67 #define AICE_BATCH_DATA_BUFFER_1 0x5
68 #define AICE_BATCH_DATA_BUFFER_2 0x6
69 #define AICE_BATCH_DATA_BUFFER_3 0x7
70
71 /* Constants for AICE command WRITE_CTRL:TCK_CONTROL */
72 #define AICE_TCK_CONTROL_TCK3048 0x08
73
74 /* Constants for AICE command WRITE_CTRL:JTAG_PIN_CONTROL */
75 #define AICE_JTAG_PIN_CONTROL_SRST 0x01
76 #define AICE_JTAG_PIN_CONTROL_TRST 0x02
77 #define AICE_JTAG_PIN_CONTROL_STOP 0x04
78 #define AICE_JTAG_PIN_CONTROL_RESTART 0x08
79
80 /* Constants for AICE command WRITE_CTRL:TCK_CONTROL */
81 #define AICE_TCK_CONTROL_TCK_SCAN 0x10
82
83 /* Custom SRST/DBGI/TRST */
84 #define AICE_CUSTOM_DELAY_SET_SRST 0x01
85 #define AICE_CUSTOM_DELAY_CLEAN_SRST 0x02
86 #define AICE_CUSTOM_DELAY_SET_DBGI 0x04
87 #define AICE_CUSTOM_DELAY_CLEAN_DBGI 0x08
88 #define AICE_CUSTOM_DELAY_SET_TRST 0x10
89 #define AICE_CUSTOM_DELAY_CLEAN_TRST 0x20
90
91 struct aice_usb_handler_s {
92 unsigned int usb_read_ep;
93 unsigned int usb_write_ep;
94 struct jtag_libusb_device_handle *usb_handle;
95 };
96
97 struct cache_info {
98 uint32_t set;
99 uint32_t way;
100 uint32_t line_size;
101
102 uint32_t log2_set;
103 uint32_t log2_line_size;
104 };
105
106 struct aice_nds32_info {
107 uint32_t edm_version;
108 uint32_t r0_backup;
109 uint32_t r1_backup;
110 uint32_t host_dtr_backup;
111 uint32_t target_dtr_backup;
112 uint32_t edmsw_backup;
113 uint32_t edm_ctl_backup;
114 bool debug_under_dex_on;
115 bool dex_use_psw_on;
116 bool host_dtr_valid;
117 bool target_dtr_valid;
118 enum nds_memory_access access_channel;
119 enum nds_memory_select memory_select;
120 enum aice_target_state_s core_state;
121 bool cache_init;
122 struct cache_info icache;
123 struct cache_info dcache;
124 };
125
126 extern struct aice_port_api_s aice_usb_api;
127
128 int aice_read_ctrl(uint32_t address, uint32_t *data);
129 int aice_write_ctrl(uint32_t address, uint32_t data);
130
131 #endif

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