src/jtag/drivers/OpenULINK/include/reg_ezusb.h

   1 /***************************************************************************
   2  *   Copyright (C) 2011 by Martin Schmoelzer                               *
   3  *   <martin.schmoelzer@student.tuwien.ac.at>                              *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20
  21 #ifndef REG_EZUSB_H
  22 #define REG_EZUSB_H
  23
  24 /**
  25  * @file All information in this file was taken from the EZ-USB Technical
  26  * Reference Manual, Cypress Semiconductor, 3901 North First Street
  27  * San Jose, CA 95134 (www.cypress.com).
  28  *
  29  * The EZ-USB Technical Reference Manual is called "EZ-USB TRM" hereafter.
  30  *
  31  * The following bit name  definitions differ from those in the EZ-USB TRM:
  32  * - All lowercase characters in the EZ-USB TRM bit names have been converted
  33  *   to capitals (e. g. "WakeSRC" converted to "WAKESRC").
  34  * - CPUCS:  8051RES is named "RES8051".
  35  * - ISOCTL: Two MBZ ("Must Be Zero") bits are named "MBZ0" and "MBZ1".
  36  * - I2CS: STOP and START bits are preceded by "I2C_"
  37  * - INxCS, OUTxCS: the busy and stall bits are named "EPBSY" and "EPSTALL".
  38  * - TOGCTL: EZ-USB TRM bit names are preceded by "TOG_".
  39  */
  40
  41 /* Compiler-specific definitions of SBIT, SFR, SFRX, ... macros */
  42 #include <mcs51/compiler.h>
  43
  44 /* Bit vectors */
  45 #define bmBit0      0x01
  46 #define bmBit1      0x02
  47 #define bmBit2      0x04
  48 #define bmBit3      0x08
  49 #define bmBit4      0x10
  50 #define bmBit5      0x20
  51 #define bmBit6      0x40
  52 #define bmBit7      0x80
  53
  54 /***************************************************************************/
  55 /************************ Special Function Registers ***********************/
  56 /***************************************************************************/
  57
  58 /* See EZ-USB TRM, pp. A-9 - A-10 */
  59
  60 SFR(SP,             0x81);
  61 SFR(DPL0,           0x82);
  62 SFR(DPH0,           0x83);
  63 SFR(DPL1,           0x84);
  64 SFR(DPL2,           0x85);
  65
  66 SFR(DPS,            0x86);
  67   #define SEL       bmBit0
  68   // Bit 1 read-only, always reads '0'
  69   // Bit 2 read-only, always reads '0'
  70   // Bit 3 read-only, always reads '0'
  71   // Bit 4 read-only, always reads '0'
  72   // Bit 5 read-only, always reads '0'
  73   // Bit 6 read-only, always reads '0'
  74   // Bit 7 read-only, always reads '0'
  75
  76 SFR(PCON,           0x87);
  77   #define IDLE      bmBit0
  78   #define STOP      bmBit1
  79   #define GF0       bmBit2
  80   #define GF1       bmBit3
  81   // Bit 4 read-only, always reads '1'
  82   // Bit 5 read-only, always reads '1'
  83   // Bit 6 unused
  84   #define SMOD0     bmBit7
  85
  86 SFR(TCON,           0x88);
  87   SBIT(IT0,         0x88, 0);
  88   SBIT(IE0,         0x88, 1);
  89   SBIT(IT1,         0x88, 2);
  90   SBIT(IE1,         0x88, 3);
  91   SBIT(TR0,         0x88, 4);
  92   SBIT(TF0,         0x88, 5);
  93   SBIT(TR1,         0x88, 6);
  94   SBIT(TF1,         0x88, 7);
  95
  96 SFR(TMOD,           0x89);
  97 /* Some bits in this register share the same name in the EZ-USB TRM. Therefore,
  98  * we add a '0'/'1' to distinguish them */
  99   #define M00       bmBit0
 100   #define M01       bmBit1
 101   #define CT0       bmBit2
 102   #define GATE0     bmBit3
 103   #define M10       bmBit4
 104   #define M11       bmBit5
 105   #define CT1       bmBit6
 106   #define GATE1     bmBit7
 107
 108 SFR(TL0,            0x8A);
 109 SFR(TL1,            0x8B);
 110 SFR(TH0,            0x8C);
 111 SFR(TH1,            0x8D);
 112
 113 SFR(CKCON,          0x8E);
 114   #define MD0       bmBit0
 115   #define MD1       bmBit1
 116   #define MD2       bmBit2
 117   #define T0M       bmBit3
 118   #define T1M       bmBit4
 119   #define T2M       bmBit5
 120   // Bit 6 unused
 121   // Bit 7 unused
 122
 123 SFR(SPC_FNC,        0x8D);
 124   #define bmWRS     bmBit0
 125   // Bit 1 read-only, always reads '0'
 126   // Bit 2 read-only, always reads '0'
 127   // Bit 3 read-only, always reads '0'
 128   // Bit 4 read-only, always reads '0'
 129   // Bit 5 read-only, always reads '0'
 130   // Bit 6 read-only, always reads '0'
 131   // Bit 7 read-only, always reads '0'
 132
 133 SFR(EXIF,           0x91);
 134   // Bit 0 read-only, always reads '0'
 135   // Bit 1 read-only, always reads '0'
 136   // Bit 2 read-only, always reads '0'
 137   // Bit 3 read-only, always reads '1'
 138   #define USBINT    bmBit4
 139   #define I2CINT    bmBit5
 140   #define IE4       bmBit6
 141   #define IE5       bmBit7
 142
 143 /* Definition of the _XPAGE register, according to SDCC Compiler User Guide,
 144  * Version 3.0.1, Chapter 4, p. 61. Also see EZ-USB TRM, p. 2-4. */
 145 SFR(MPAGE,          0x92);
 146 SFR(_XPAGE,         0x92);
 147
 148 SFR(SCON0,          0x98);
 149   SBIT(RI_0,        0x98, 0);
 150   SBIT(TI_0,        0x98, 1);
 151   SBIT(RB8_0,       0x98, 2);
 152   SBIT(TB8_0,       0x98, 3);
 153   SBIT(REN_0,       0x98, 4);
 154   SBIT(SM2_0,       0x98, 5);
 155   SBIT(SM1_0,       0x98, 6);
 156   SBIT(SM0_0,       0x98, 7);
 157
 158 SFR(SBUF0,          0x99);
 159
 160 SFR(IE,             0xA8);
 161   SBIT(EX0,         0xA8, 0);
 162   SBIT(ET0,         0xA8, 1);
 163   SBIT(EX1,         0xA8, 2);
 164   SBIT(ET1,         0xA8, 3);
 165   SBIT(ES0,         0xA8, 4);
 166   SBIT(ET2,         0xA8, 5);
 167   SBIT(ES1,         0xA8, 6);
 168   SBIT(EA,          0xA8, 7);
 169
 170 SFR(IP,             0xB8);
 171   SBIT(PX0,         0xB8, 0);
 172   SBIT(PT0,         0xB8, 1);
 173   SBIT(PX1,         0xB8, 2);
 174   SBIT(PT1,         0xB8, 3);
 175   SBIT(PS0,         0xB8, 4);
 176   SBIT(PT2,         0xB8, 5);
 177   SBIT(PS1,         0xB8, 6);
 178   // Bit 7 read-only, always reads '1'
 179
 180 SFR(SCON1,          0xC0);
 181   SBIT(RI_1,        0xC0, 0);
 182   SBIT(TI_1,        0xC0, 1);
 183   SBIT(RB8_1,       0xC0, 2);
 184   SBIT(TB8_1,       0xC0, 3);
 185   SBIT(REN_1,       0xC0, 4);
 186   SBIT(SM2_1,       0xC0, 5);
 187   SBIT(SM1_1,       0xC0, 6);
 188   SBIT(SM0_1,       0xC0, 7);
 189
 190 SFR(SBUF1,          0xC1);
 191
 192 SFR(T2CON,          0xC8);
 193   SBIT(CPRL2,       0xC8, 0);
 194   SBIT(CT2,         0xC8, 1);
 195   SBIT(TR2,         0xC8, 2);
 196   SBIT(EXEN2,       0xC8, 3);
 197   SBIT(TCLK,        0xC8, 4);
 198   SBIT(RCLK,        0xC8, 5);
 199   SBIT(EXF2,        0xC8, 6);
 200   SBIT(TF2,         0xC8, 7);
 201
 202 SFR(RCAP2L,         0xCA);
 203 SFR(RCAP2H,         0xCB);
 204 SFR(TL2,            0xCC);
 205 SFR(TH2,            0xCD);
 206
 207 SFR(PSW,            0xD0);
 208   SBIT(P,           0xD0, 0);
 209   SBIT(F1,          0xD0, 1);
 210   SBIT(OV,          0xD0, 2);
 211   SBIT(RS0,         0xD0, 3);
 212   SBIT(RS1,         0xD0, 4);
 213   SBIT(F0,          0xD0, 5);
 214   SBIT(AC,          0xD0, 6);
 215   SBIT(CY,          0xD0, 7);
 216
 217 SFR(EICON,          0xD8);
 218   // Bit 0 read-only, always reads '0'
 219   // Bit 1 read-only, always reads '0'
 220   // Bit 2 read-only, always reads '0'
 221   SBIT(INT6,        0xD8, 3);
 222   SBIT(RESI,        0xD8, 4);
 223   SBIT(ERESI,       0xD8, 5);
 224   // Bit 6 read-only, always reads '1'
 225   SBIT(SMOD1,       0xD8, 7);
 226
 227 SFR(ACC,            0xE0);
 228
 229 SFR(EIE,            0xE8);
 230   SBIT(EUSB,        0xE8, 0);
 231   SBIT(EI2C,        0xE8, 1);
 232   SBIT(EX4,         0xE8, 2);
 233   SBIT(EX5,         0xE8, 3);
 234   SBIT(EWDI,        0xE8, 4);
 235   // Bit 5 read-only, always reads '1'
 236   // Bit 6 read-only, always reads '1'
 237   // Bit 7 read-only, always reads '1'
 238
 239 SFR(B,              0xF0);
 240
 241 SFR(EIP,            0xF8);
 242   SBIT(PUSB,        0xF8, 0);
 243   SBIT(PI2C,        0xF8, 1);
 244   SBIT(PX4,         0xF8, 2);
 245   SBIT(PX5,         0xF8, 3);
 246   SBIT(PX6,         0xF8, 4);
 247   // Bit 5 read-only, always reads '1'
 248   // Bit 6 read-only, always reads '1'
 249   // Bit 7 read-only, always reads '1'
 250
 251 /***************************************************************************/
 252 /***************************** XDATA Registers *****************************/
 253 /***************************************************************************/
 254
 255 /************************ Endpoint 0-7 Data Buffers ************************/
 256 SFRX(OUT7BUF[64],   0x7B40);
 257 SFRX(IN7BUF[64],    0x7B80);
 258 SFRX(OUT6BUF[64],   0x7BC0);
 259 SFRX(IN6BUF[64],    0x7C00);
 260 SFRX(OUT5BUF[64],   0x7C40);
 261 SFRX(IN5BUF[64],    0x7C80);
 262 SFRX(OUT4BUF[64],   0x7CC0);
 263 SFRX(IN4BUF[64],    0x7D00);
 264 SFRX(OUT3BUF[64],   0x7D40);
 265 SFRX(IN3BUF[64],    0x7D80);
 266 SFRX(OUT2BUF[64],   0x7DC0);
 267 SFRX(IN2BUF[64],    0x7E00);
 268 SFRX(OUT1BUF[64],   0x7E40);
 269 SFRX(IN1BUF[64],    0x7E80);
 270 SFRX(OUT0BUF[64],   0x7EC0);
 271 SFRX(IN0BUF[64],    0x7F00);
 272 // 0x7F40 - 0x7F5F reserved
 273
 274 /**************************** Isochronous Data *****************************/
 275 SFRX(OUT8DATA,      0x7F60);
 276 SFRX(OUT9DATA,      0x7F61);
 277 SFRX(OUT10DATA,     0x7F62);
 278 SFRX(OUT11DATA,     0x7F63);
 279 SFRX(OUT12DATA,     0x7F64);
 280 SFRX(OUT13DATA,     0x7F65);
 281 SFRX(OUT14DATA,     0x7F66);
 282 SFRX(OUT15DATA,     0x7F67);
 283
 284 SFRX(IN8DATA,       0x7F68);
 285 SFRX(IN9DATA,       0x7F69);
 286 SFRX(IN10DATA,      0x7F6A);
 287 SFRX(IN11DATA,      0x7F6B);
 288 SFRX(IN12DATA,      0x7F6C);
 289 SFRX(IN13DATA,      0x7F6D);
 290 SFRX(IN14DATA,      0x7F6E);
 291 SFRX(IN15DATA,      0x7F6F);
 292
 293 /************************* Isochronous Byte Counts *************************/
 294 SFRX(OUT8BCH,       0x7F70);
 295 SFRX(OUT8BCL,       0x7F71);
 296 SFRX(OUT9BCH,       0x7F72);
 297 SFRX(OUT9BCL,       0x7F73);
 298 SFRX(OUT10BCH,      0x7F74);
 299 SFRX(OUT10BCL,      0x7F75);
 300 SFRX(OUT11BCH,      0x7F76);
 301 SFRX(OUT11BCL,      0x7F77);
 302 SFRX(OUT12BCH,      0x7F78);
 303 SFRX(OUT12BCL,      0x7F79);
 304 SFRX(OUT13BCH,      0x7F7A);
 305 SFRX(OUT13BCL,      0x7F7B);
 306 SFRX(OUT14BCH,      0x7F7C);
 307 SFRX(OUT14BCL,      0x7F7D);
 308 SFRX(OUT15BCH,      0x7F7E);
 309 SFRX(OUT16BCL,      0x7F7F);
 310
 311 /****************************** CPU Registers ******************************/
 312 SFRX(CPUCS,         0x7F92);
 313   #define RES8051   bmBit0
 314   #define CLK24OE   bmBit1
 315   // Bit 2 read-only, always reads '0'
 316   // Bit 3 read-only, always reads '0'
 317   // Bits 4...7: Chip Revision
 318
 319 SFRX(PORTACFG,      0x7F93);
 320   #define T0OUT     bmBit0
 321   #define T1OUT     bmBit1
 322   #define OE        bmBit2
 323   #define CS        bmBit3
 324   #define FWR       bmBit4
 325   #define FRD       bmBit5
 326   #define RXD0OUT   bmBit6
 327   #define RXD1OUT   bmBit7
 328
 329 SFRX(PORTBCFG,      0x7F94);
 330   #define T2        bmBit0
 331   #define T2EX      bmBit1
 332   #define RXD1      bmBit2
 333   #define TXD1      bmBit3
 334   #define INT4      bmBit4
 335   #define INT5      bmBit5
 336   #define INT6      bmBit6
 337   #define T2OUT     bmBit7
 338
 339 SFRX(PORTCCFG,      0x7F95);
 340   #define RXD0      bmBit0
 341   #define TXD0      bmBit1
 342   #define INT0      bmBit2
 343   #define INT1      bmBit3
 344   #define T0        bmBit4
 345   #define T1        bmBit5
 346   #define WR        bmBit6
 347   #define RD        bmBit7
 348
 349 /*********************** Input-Output Port Registers ***********************/
 350 SFRX(OUTA,          0x7F96);
 351   #define OUTA0     bmBit0
 352   #define OUTA1     bmBit1
 353   #define OUTA2     bmBit2
 354   #define OUTA3     bmBit3
 355   #define OUTA4     bmBit4
 356   #define OUTA5     bmBit5
 357   #define OUTA6     bmBit6
 358   #define OUTA7     bmBit7
 359
 360 SFRX(OUTB,          0x7F97);
 361   #define OUTB0     bmBit0
 362   #define OUTB1     bmBit1
 363   #define OUTB2     bmBit2
 364   #define OUTB3     bmBit3
 365   #define OUTB4     bmBit4
 366   #define OUTB5     bmBit5
 367   #define OUTB6     bmBit6
 368   #define OUTB7     bmBit7
 369
 370 SFRX(OUTC,          0x7F98);
 371   #define OUTC0     bmBit0
 372   #define OUTC1     bmBit1
 373   #define OUTC2     bmBit2
 374   #define OUTC3     bmBit3
 375   #define OUTC4     bmBit4
 376   #define OUTC5     bmBit5
 377   #define OUTC6     bmBit6
 378   #define OUTC7     bmBit7
 379
 380 SFRX(PINSA,         0x7F99);
 381   #define PINA0     bmBit0
 382   #define PINA1     bmBit1
 383   #define PINA2     bmBit2
 384   #define PINA3     bmBit3
 385   #define PINA4     bmBit4
 386   #define PINA5     bmBit5
 387   #define PINA6     bmBit6
 388   #define PINA7     bmBit7
 389
 390 SFRX(PINSB,         0x7F9A);
 391   #define PINB0     bmBit0
 392   #define PINB1     bmBit1
 393   #define PINB2     bmBit2
 394   #define PINB3     bmBit3
 395   #define PINB4     bmBit4
 396   #define PINB5     bmBit5
 397   #define PINB6     bmBit6
 398   #define PINB7     bmBit7
 399
 400 SFRX(PINSC,         0x7F9B);
 401   #define PINC0     bmBit0
 402   #define PINC1     bmBit1
 403   #define PINC2     bmBit2
 404   #define PINC3     bmBit3
 405   #define PINC4     bmBit4
 406   #define PINC5     bmBit5
 407   #define PINC6     bmBit6
 408   #define PINC7     bmBit7
 409
 410 SFRX(OEA,           0x7F9C);
 411   #define OEA0      bmBit0
 412   #define OEA1      bmBit1
 413   #define OEA2      bmBit2
 414   #define OEA3      bmBit3
 415   #define OEA4      bmBit4
 416   #define OEA5      bmBit5
 417   #define OEA6      bmBit6
 418   #define OEA7      bmBit7
 419
 420 SFRX(OEB,           0x7F9D);
 421   #define OEB0      bmBit0
 422   #define OEB1      bmBit1
 423   #define OEB2      bmBit2
 424   #define OEB3      bmBit3
 425   #define OEB4      bmBit4
 426   #define OEB5      bmBit5
 427   #define OEB6      bmBit6
 428   #define OEB7      bmBit7
 429
 430 SFRX(OEC,           0x7F9E);
 431   #define OEC0      bmBit0
 432   #define OEC1      bmBit1
 433   #define OEC2      bmBit2
 434   #define OEC3      bmBit3
 435   #define OEC4      bmBit4
 436   #define OEC5      bmBit5
 437   #define OEC6      bmBit6
 438   #define OEC7      bmBit7
 439
 440 // 0x7F9F reserved
 441
 442 /****************** Isochronous Control/Status Registers *******************/
 443 SFRX(ISOERR,        0x7FA0);
 444   #define ISO8ERR   bmBit0
 445   #define ISO9ERR   bmBit1
 446   #define ISO10ERR  bmBit2
 447   #define ISO11ERR  bmBit3
 448   #define ISO12ERR  bmBit4
 449   #define ISO13ERR  bmBit5
 450   #define ISO14ERR  bmBit6
 451   #define ISO15ERR  bmBit7
 452
 453 SFRX(ISOCTL,        0x7FA1);
 454   #define ISODISAB  bmBit0
 455   #define MBZ0      bmBit1
 456   #define MBZ1      bmBit2
 457   #define PPSTAT    bmBit3
 458   // Bit 4 unused
 459   // Bit 5 unused
 460   // Bit 6 unused
 461   // Bit 7 unused
 462
 463 SFRX(ZBCOUT,        0x7FA2);
 464   #define EP8       bmBit0
 465   #define EP9       bmBit1
 466   #define EP10      bmBit2
 467   #define EP11      bmBit3
 468   #define EP12      bmBit4
 469   #define EP13      bmBit5
 470   #define EP14      bmBit6
 471   #define EP15      bmBit7
 472
 473 // 0x7FA3 reserved
 474 // 0x7FA4 reserved
 475
 476 /****************************** I2C Registers ******************************/
 477 SFRX(I2CS,          0x7FA5);
 478   #define DONE      bmBit0
 479   #define ACK       bmBit1
 480   #define BERR      bmBit2
 481   #define ID0       bmBit3
 482   #define ID1       bmBit4
 483   #define LASTRD    bmBit5
 484   #define I2C_STOP  bmBit6
 485   #define I2C_START bmBit7
 486
 487 SFRX(I2DAT,         0x7FA6);
 488 // 0x7FA7 reserved
 489
 490 /******************************* Interrupts ********************************/
 491 SFRX(IVEC,          0x7FA8);
 492   // Bit 0 read-only, always reads '0'
 493   // Bit 1 read-only, always reads '0'
 494   #define IV0       bmBit2
 495   #define IV1       bmBit3
 496   #define IV2       bmBit4
 497   #define IV3       bmBit5
 498   #define IV4       bmBit6
 499   // Bit 7 read-only, always reads '0'
 500
 501 SFRX(IN07IRQ,       0x7FA9);
 502   #define IN0IR     bmBit0
 503   #define IN1IR     bmBit1
 504   #define IN2IR     bmBit2
 505   #define IN3IR     bmBit3
 506   #define IN4IR     bmBit4
 507   #define IN5IR     bmBit5
 508   #define IN6IR     bmBit6
 509   #define IN7IR     bmBit7
 510
 511 SFRX(OUT07IRQ,      0x7FAA);
 512   #define OUT0IR    bmBit0
 513   #define OUT1IR    bmBit1
 514   #define OUT2IR    bmBit2
 515   #define OUT3IR    bmBit3
 516   #define OUT4IR    bmBit4
 517   #define OUT5IR    bmBit5
 518   #define OUT6IR    bmBit6
 519   #define OUT7IR    bmBit7
 520
 521 SFRX(USBIRQ,        0x7FAB);
 522   #define SUDAVIR   bmBit0
 523   #define SOFIR     bmBit1
 524   #define SUTOKIR   bmBit2
 525   #define SUSPIR    bmBit3
 526   #define URESIR    bmBit4
 527   // Bit 5 unused
 528   // Bit 6 unused
 529   // Bit 7 unused
 530
 531 SFRX(IN07IEN,       0x7FAC);
 532   #define IN0IEN    bmBit0
 533   #define IN1IEN    bmBit1
 534   #define IN2IEN    bmBit2
 535   #define IN3IEN    bmBit3
 536   #define IN4IEN    bmBit4
 537   #define IN5IEN    bmBit5
 538   #define IN6IEN    bmBit6
 539   #define IN7IEN    bmBit7
 540
 541 SFRX(OUT07IEN,      0x7FAD);
 542   #define OUT0IEN   bmBit0
 543   #define OUT1IEN   bmBit1
 544   #define OUT2IEN   bmBit2
 545   #define OUT3IEN   bmBit3
 546   #define OUT4IEN   bmBit4
 547   #define OUT5IEN   bmBit5
 548   #define OUT6IEN   bmBit6
 549   #define OUT7IEN   bmBit7
 550
 551 SFRX(USBIEN,        0x7FAE);
 552   #define SUDAVIE   bmBit0
 553   #define SOFIE     bmBit1
 554   #define SUTOKIE   bmBit2
 555   #define SUSPIE    bmBit3
 556   #define URESIE    bmBit4
 557   // Bit 5 unused
 558   // Bit 6 unused
 559   // Bit 7 unused
 560
 561 SFRX(USBBAV,        0x7FAF);
 562   #define AVEN      bmBit0
 563   #define BPEN      bmBit1
 564   #define BPPULSE   bmBit2
 565   #define BREAK     bmBit3
 566   // Bit 4 unused
 567   // Bit 5 unused
 568   // Bit 6 unused
 569   // Bit 7 unused
 570
 571 // 0x7FB0 reserved
 572 // 0x7FB1 reserved
 573 SFRX(BPADDRH,       0x7FB2);
 574 SFRX(BPADDRL,       0x7FB3);
 575
 576 /****************************** Endpoints 0-7 ******************************/
 577 SFRX(EP0CS,         0x7FB4);
 578   #define EP0STALL  bmBit0
 579   #define HSNAK     bmBit1
 580   #define IN0BSY    bmBit2
 581   #define OUT0BSY   bmBit3
 582   // Bit 4 unused
 583   // Bit 5 unused
 584   // Bit 6 unused
 585   // Bit 7 unused
 586
 587 SFRX(IN0BC,         0x7FB5);
 588 SFRX(IN1CS,         0x7FB6);
 589 SFRX(IN1BC,         0x7FB7);
 590 SFRX(IN2CS,         0x7FB8);
 591 SFRX(IN2BC,         0x7FB9);
 592 SFRX(IN3CS,         0x7FBA);
 593 SFRX(IN3BC,         0x7FBB);
 594 SFRX(IN4CS,         0x7FBC);
 595 SFRX(IN4BC,         0x7FBD);
 596 SFRX(IN5CS,         0x7FBE);
 597 SFRX(IN5BC,         0x7FBF);
 598 SFRX(IN6CS,         0x7FC0);
 599 SFRX(IN6BC,         0x7FC1);
 600 SFRX(IN7CS,         0x7FC2);
 601 SFRX(IN7BC,         0x7FC3);
 602 // 0x7FC4 reserved
 603 SFRX(OUT0BC,        0x7FC5);
 604 SFRX(OUT1CS,        0x7FC6);
 605 SFRX(OUT1BC,        0x7FC7);
 606 SFRX(OUT2CS,        0x7FC8);
 607 SFRX(OUT2BC,        0x7FC9);
 608 SFRX(OUT3CS,        0x7FCA);
 609 SFRX(OUT3BC,        0x7FCB);
 610 SFRX(OUT4CS,        0x7FCC);
 611 SFRX(OUT4BC,        0x7FCD);
 612 SFRX(OUT5CS,        0x7FCE);
 613 SFRX(OUT5BC,        0x7FCF);
 614 SFRX(OUT6CS,        0x7FD0);
 615 SFRX(OUT6BC,        0x7FD1);
 616 SFRX(OUT7CS,        0x7FD2);
 617 SFRX(OUT7BC,        0x7FD3);
 618
 619 /* The INxSTALL, OUTxSTALL, INxBSY and OUTxBSY bits are the same for all
 620  * INxCS/OUTxCS registers. For better readability, we define them only once */
 621 #define EPSTALL     bmBit0
 622 #define EPBSY       bmBit1
 623
 624 /************************** Global USB Registers ***************************/
 625 SFRX(SUDPTRH,       0x7FD4);
 626 SFRX(SUDPTRL,       0x7FD5);
 627
 628 SFRX(USBCS,         0x7FD6);
 629   #define SIGRSUME  bmBit0
 630   #define RENUM     bmBit1
 631   #define DISCOE    bmBit2
 632   #define DISCON    bmBit3
 633   // Bit 4 unused
 634   // Bit 5 unused
 635   // Bit 6 unused
 636   #define WAKESRC   bmBit7
 637
 638 SFRX(TOGCTL,        0x7FD7);
 639   #define TOG_EP0   bmBit0
 640   #define TOG_EP1   bmBit1
 641   #define TOG_EP2   bmBit2
 642   // Bit 3 is read-only, always reads '0'
 643   #define TOG_IO    bmBit4
 644   #define TOG_R     bmBit5
 645   #define TOG_S     bmBit6
 646   #define TOG_Q     bmBit7
 647
 648 SFRX(USBFRAMEL,     0x7FD8);
 649 SFRX(USBFRAMEH,     0x7FD9);
 650 // 0x7FDA reserved
 651 SFRX(FNADDR,        0x7FDB);
 652 // 0x7FDC reserved
 653
 654 SFRX(USBPAIR,       0x7FDD);
 655   #define PR2IN     bmBit0
 656   #define PR4IN     bmBit1
 657   #define PR6IN     bmBit2
 658   #define PR2OUT    bmBit3
 659   #define PR4OUT    bmBit4
 660   #define PR6OUT    bmBit5
 661   // Bit 6 unused
 662   #define ISOSEND0  bmBit7
 663
 664 SFRX(IN07VAL,       0x7FDE);
 665   // Bit 0 is read-only, always reads '1'
 666   #define IN1VAL    bmBit1
 667   #define IN2VAL    bmBit2
 668   #define IN3VAL    bmBit3
 669   #define IN4VAL    bmBit4
 670   #define IN5VAL    bmBit5
 671   #define IN6VAL    bmBit6
 672   #define IN7VAL    bmBit7
 673
 674 SFRX(OUT07VAL,      0x7FDF);
 675   // Bit 0 is read-only, always reads '1'
 676   #define OUT1VAL   bmBit1
 677   #define OUT2VAL   bmBit2
 678   #define OUT3VAL   bmBit3
 679   #define OUT4VAL   bmBit4
 680   #define OUT5VAL   bmBit5
 681   #define OUT6VAL   bmBit6
 682   #define OUT7VAL   bmBit7
 683
 684 SFRX(INISOVAL,      0x7FE0);
 685   #define IN8VAL    bmBit0
 686   #define IN9VAL    bmBit1
 687   #define IN10VAL   bmBit2
 688   #define IN11VAL   bmBit3
 689   #define IN12VAL   bmBit4
 690   #define IN13VAL   bmBit5
 691   #define IN14VAL   bmBit6
 692   #define IN15VAL   bmBit7
 693
 694 SFRX(OUTISOVAL,     0x7FE1);
 695   #define OUT8VAL   bmBit0
 696   #define OUT9VAL   bmBit1
 697   #define OUT10VAL  bmBit2
 698   #define OUT11VAL  bmBit3
 699   #define OUT12VAL  bmBit4
 700   #define OUT13VAL  bmBit5
 701   #define OUT14VAL  bmBit6
 702   #define OUT15VAL  bmBit7
 703
 704 SFRX(FASTXFR,       0x7FE2);
 705   #define WMOD0     bmBit0
 706   #define WMOD1     bmBit1
 707   #define WPOL      bmBit2
 708   #define RMOD0     bmBit3
 709   #define RMOD1     bmBit4
 710   #define RPOL      bmBit5
 711   #define FBLK      bmBit6
 712   #define FISO      bmBit7
 713
 714 SFRX(AUTOPTRH,      0x7FE3);
 715 SFRX(AUTOPTRL,      0x7FE4);
 716 SFRX(AUTODATA,      0x7FE5);
 717 // 0x7FE6 reserved
 718 // 0x7FE7 reserved
 719
 720 /******************************* Setup Data ********************************/
 721 SFRX(SETUPDAT[8],   0x7FE8);
 722
 723 /************************* Isochronous FIFO sizes **************************/
 724 SFRX(OUT8ADDR,      0x7FF0);
 725 SFRX(OUT9ADDR,      0x7FF1);
 726 SFRX(OUT10ADDR,     0x7FF2);
 727 SFRX(OUT11ADDR,     0x7FF3);
 728 SFRX(OUT12ADDR,     0x7FF4);
 729 SFRX(OUT13ADDR,     0x7FF5);
 730 SFRX(OUT14ADDR,     0x7FF6);
 731 SFRX(OUT15ADDR,     0x7FF7);
 732
 733 SFRX(IN8ADDR,       0x7FF8);
 734 SFRX(IN9ADDR,       0x7FF9);
 735 SFRX(IN10ADDR,      0x7FFA);
 736 SFRX(IN11ADDR,      0x7FFB);
 737 SFRX(IN12ADDR,      0x7FFC);
 738 SFRX(IN13ADDR,      0x7FFD);
 739 SFRX(IN14ADDR,      0x7FFE);
 740 SFRX(IN15ADDR,      0x7FFF);
 741
 742 #endif