src/jtag/ep93xx.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "log.h"
  25 #include "jtag.h"
  26 #include "bitbang.h"
  27
  28 #define TDO_BIT         1
  29 #define TDI_BIT         2
  30 #define TCK_BIT         4
  31 #define TMS_BIT         8
  32 #define TRST_BIT        16
  33 #define SRST_BIT        32
  34 #define VCC_BIT         64
  35
  36 /* system includes */
  37 #include <sys/io.h>
  38 #include <string.h>
  39 #include <stdlib.h>
  40 #include <stdio.h>
  41 #include <sys/mman.h>
  42 #include <unistd.h>
  43 #include <fcntl.h>
  44
  45 static u8 output_value = 0x0;
  46 static int dev_mem_fd;
  47 static void *gpio_controller;
  48 static volatile u8 *gpio_data_register;
  49 static volatile u8 *gpio_data_direction_register;
  50
  51 /* low level command set
  52  */
  53 int ep93xx_read(void);
  54 void ep93xx_write(int tck, int tms, int tdi);
  55 void ep93xx_reset(int trst, int srst);
  56
  57 int ep93xx_speed(int speed);
  58 int ep93xx_register_commands(struct command_context_s *cmd_ctx);
  59 int ep93xx_init(void);
  60 int ep93xx_quit(void);
  61
  62 struct timespec ep93xx_zzzz;
  63
  64 jtag_interface_t ep93xx_interface =
  65 {
  66         .name = "ep93xx",
  67
  68         .execute_queue = bitbang_execute_queue,
  69
  70         .support_pathmove = 0,
  71
  72         .speed = ep93xx_speed,
  73         .register_commands = ep93xx_register_commands,
  74         .init = ep93xx_init,
  75         .quit = ep93xx_quit,
  76 };
  77
  78 bitbang_interface_t ep93xx_bitbang =
  79 {
  80         .read = ep93xx_read,
  81         .write = ep93xx_write,
  82         .reset = ep93xx_reset
  83 };
  84
  85 int ep93xx_read(void)
  86 {
  87         return !!(*gpio_data_register & TDO_BIT);
  88 }
  89
  90 void ep93xx_write(int tck, int tms, int tdi)
  91 {
  92         if (tck)
  93                 output_value |= TCK_BIT;
  94         else
  95                 output_value &= TCK_BIT;
  96
  97         if (tms)
  98                 output_value |= TMS_BIT;
  99         else
 100                 output_value &= TMS_BIT;
 101
 102         if (tdi)
 103                 output_value |= TDI_BIT;
 104         else
 105                 output_value &= TDI_BIT;
 106
 107         *gpio_data_register = output_value;
 108         nanosleep(ep93xx_zzzz);
 109 }
 110
 111 /* (1) assert or (0) deassert reset lines */
 112 void ep93xx_reset(int trst, int srst)
 113 {
 114         if (trst == 0)
 115                 output_value |= TRST_BIT;
 116         else if (trst == 1)
 117                 output_value &= TRST_BIT;
 118
 119         if (srst == 0)
 120                 output_value |= SRST_BIT;
 121         else if (srst == 1)
 122                 output_value &= SRST_BIT;
 123
 124         *gpio_data_register = output_value;
 125         nanosleep(ep93xx_zzzz);
 126 }
 127
 128 int ep93xx_speed(int speed)
 129 {
 130
 131         return ERROR_OK;
 132 }
 133
 134 int ep93xx_register_commands(struct command_context_s *cmd_ctx)
 135 {
 136
 137         return ERROR_OK;
 138 }
 139
 140 static int set_gonk_mode(void)
 141 {
 142         void *syscon;
 143         u32 devicecfg;
 144
 145         syscon = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
 146                         MAP_SHARED, dev_mem_fd, 0x80930000);
 147         if (syscon == MAP_FAILED) {
 148                 perror("mmap");
 149                 return ERROR_JTAG_INIT_FAILED;
 150         }
 151
 152         devicecfg = *((volatile int *)(syscon + 0x80));
 153         *((volatile int *)(syscon + 0xc0)) = 0xaa;
 154         *((volatile int *)(syscon + 0x80)) = devicecfg | 0x08000000;
 155
 156         munmap(syscon, 4096);
 157
 158         return ERROR_OK;
 159 }
 160
 161 int ep93xx_init(void)
 162 {
 163         int ret;
 164
 165         bitbang_interface = &ep93xx_bitbang;
 166
 167         ep93xx_zzzz.tv_sec = 0;
 168         ep93xx_zzzz.tv_nsec = 10000000;
 169
 170         dev_mem_fd = open("/dev/mem", O_RDWR | O_SYNC);
 171         if (dev_mem_fd < 0) {
 172                 perror("open");
 173                 return ERROR_JTAG_INIT_FAILED;
 174         }
 175
 176         gpio_controller = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
 177                                 MAP_SHARED, dev_mem_fd, 0x80840000);
 178         if (gpio_controller == MAP_FAILED) {
 179                 perror("mmap");
 180                 close(dev_mem_fd);
 181                 return ERROR_JTAG_INIT_FAILED;
 182         }
 183
 184         ret = set_gonk_mode();
 185         if (ret != ERROR_OK) {
 186                 munmap(gpio_controller, 4096);
 187                 close(dev_mem_fd);
 188                 return ret;
 189         }
 190
 191 #if 0
 192         /* Use GPIO port A.  */
 193         gpio_data_register = gpio_controller + 0x00;
 194         gpio_data_direction_register = gpio_controller + 0x10;
 195
 196
 197         /* Use GPIO port B.  */
 198         gpio_data_register = gpio_controller + 0x04;
 199         gpio_data_direction_register = gpio_controller + 0x14;
 200
 201         /* Use GPIO port C.  */
 202         gpio_data_register = gpio_controller + 0x08;
 203         gpio_data_direction_register = gpio_controller + 0x18;
 204
 205         /* Use GPIO port D.  */
 206         gpio_data_register = gpio_controller + 0x0c;
 207         gpio_data_direction_register = gpio_controller + 0x1c;
 208 #endif
 209
 210         /* Use GPIO port C.  */
 211         gpio_data_register = gpio_controller + 0x08;
 212         gpio_data_direction_register = gpio_controller + 0x18;
 213
 214         printf("gpio_data_register      = %08x\n", gpio_data_register);
 215         printf("gpio_data_direction_reg = %08x\n", gpio_data_direction_register);
 216         /*
 217          * Configure bit 0 (TDO) as an input, and bits 1-5 (TDI, TCK
 218          * TMS, TRST, SRST) as outputs.  Drive TDI and TCK low, and
 219          * TMS/TRST/SRST high.
 220          */
 221         output_value = TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
 222         *gpio_data_register = output_value;
 223         nanosleep(ep93xx_zzzz);
 224
 225         /*
 226          * Configure the direction register.  1 = output, 0 = input.
 227          */
 228         *gpio_data_direction_register =
 229                 TDI_BIT | TCK_BIT | TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
 230
 231         nanosleep(ep93xx_zzzz);
 232         return ERROR_OK;
 233 }
 234
 235 int ep93xx_quit(void)
 236 {
 237
 238         return ERROR_OK;
 239 }