src/jtag/ep93xx.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #include "config.h"
  21 #include "log.h"
  22 #include "jtag.h"
  23 #include "bitbang.h"
  24
  25 #define TDO_BIT         1
  26 #define TDI_BIT         2
  27 #define TCK_BIT         4
  28 #define TMS_BIT         8
  29 #define TRST_BIT        16
  30 #define SRST_BIT        32
  31 #define VCC_BIT         64
  32
  33 /* system includes */
  34 #include <sys/io.h>
  35 #include <string.h>
  36 #include <stdlib.h>
  37 #include <stdio.h>
  38 #include <sys/mman.h>
  39 #include <unistd.h>
  40 #include <fcntl.h>
  41
  42 static u8 output_value = 0x0;
  43 static int dev_mem_fd;
  44 static void *gpio_controller;
  45 static volatile u8 *gpio_data_register;
  46 static volatile u8 *gpio_data_direction_register;
  47
  48 /* low level command set
  49  */
  50 int ep93xx_read(void);
  51 void ep93xx_write(int tck, int tms, int tdi);
  52 void ep93xx_reset(int trst, int srst);
  53
  54 int ep93xx_speed(int speed);
  55 int ep93xx_register_commands(struct command_context_s *cmd_ctx);
  56 int ep93xx_init(void);
  57 int ep93xx_quit(void);
  58
  59 struct timespec ep93xx_zzzz;
  60
  61 jtag_interface_t ep93xx_interface =
  62 {
  63         .name = "ep93xx",
  64
  65         .execute_queue = bitbang_execute_queue,
  66
  67         .support_statemove = 0,
  68
  69         .speed = ep93xx_speed,
  70         .register_commands = ep93xx_register_commands,
  71         .init = ep93xx_init,
  72         .quit = ep93xx_quit,
  73 };
  74
  75 bitbang_interface_t ep93xx_bitbang =
  76 {
  77         .read = ep93xx_read,
  78         .write = ep93xx_write,
  79         .reset = ep93xx_reset
  80 };
  81
  82 int ep93xx_read(void)
  83 {
  84         return !!(*gpio_data_register & TDO_BIT);
  85 }
  86
  87 void ep93xx_write(int tck, int tms, int tdi)
  88 {
  89         if (tck)
  90                 output_value |= TCK_BIT;
  91         else
  92                 output_value &= TCK_BIT;
  93
  94         if (tms)
  95                 output_value |= TMS_BIT;
  96         else
  97                 output_value &= TMS_BIT;
  98
  99         if (tdi)
 100                 output_value |= TDI_BIT;
 101         else
 102                 output_value &= TDI_BIT;
 103
 104         *gpio_data_register = output_value;
 105         nanosleep(ep93xx_zzzz);
 106 }
 107
 108 /* (1) assert or (0) deassert reset lines */
 109 void ep93xx_reset(int trst, int srst)
 110 {
 111         if (trst == 0)
 112                 output_value |= TRST_BIT;
 113         else if (trst == 1)
 114                 output_value &= TRST_BIT;
 115
 116         if (srst == 0)
 117                 output_value |= SRST_BIT;
 118         else if (srst == 1)
 119                 output_value &= SRST_BIT;
 120
 121         *gpio_data_register = output_value;
 122         nanosleep(ep93xx_zzzz);
 123 }
 124
 125 int ep93xx_speed(int speed)
 126 {
 127
 128         return ERROR_OK;
 129 }
 130
 131 int ep93xx_register_commands(struct command_context_s *cmd_ctx)
 132 {
 133
 134         return ERROR_OK;
 135 }
 136
 137 static int set_gonk_mode(void)
 138 {
 139         void *syscon;
 140         u32 devicecfg;
 141
 142         syscon = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
 143                         MAP_SHARED, dev_mem_fd, 0x80930000);
 144         if (syscon == MAP_FAILED) {
 145                 perror("mmap");
 146                 return ERROR_JTAG_INIT_FAILED;
 147         }
 148
 149         devicecfg = *((volatile int *)(syscon + 0x80));
 150         *((volatile int *)(syscon + 0xc0)) = 0xaa;
 151         *((volatile int *)(syscon + 0x80)) = devicecfg | 0x08000000;
 152
 153         munmap(syscon, 4096);
 154
 155         return ERROR_OK;
 156 }
 157
 158 int ep93xx_init(void)
 159 {
 160         int ret;
 161
 162         bitbang_interface = &ep93xx_bitbang;
 163
 164         ep93xx_zzzz.tv_sec = 0;
 165         ep93xx_zzzz.tv_nsec = 10000000;
 166
 167         dev_mem_fd = open("/dev/mem", O_RDWR | O_SYNC);
 168         if (dev_mem_fd < 0) {
 169                 perror("open");
 170                 return ERROR_JTAG_INIT_FAILED;
 171         }
 172
 173         gpio_controller = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
 174                                 MAP_SHARED, dev_mem_fd, 0x80840000);
 175         if (gpio_controller == MAP_FAILED) {
 176                 perror("mmap");
 177                 close(dev_mem_fd);
 178                 return ERROR_JTAG_INIT_FAILED;
 179         }
 180
 181         ret = set_gonk_mode();
 182         if (ret != ERROR_OK) {
 183                 munmap(gpio_controller, 4096);
 184                 close(dev_mem_fd);
 185                 return ret;
 186         }
 187
 188 #if 0
 189         /* Use GPIO port A.  */
 190         gpio_data_register = gpio_controller + 0x00;
 191         gpio_data_direction_register = gpio_controller + 0x10;
 192
 193
 194         /* Use GPIO port B.  */
 195         gpio_data_register = gpio_controller + 0x04;
 196         gpio_data_direction_register = gpio_controller + 0x14;
 197
 198         /* Use GPIO port C.  */
 199         gpio_data_register = gpio_controller + 0x08;
 200         gpio_data_direction_register = gpio_controller + 0x18;
 201
 202         /* Use GPIO port D.  */
 203         gpio_data_register = gpio_controller + 0x0c;
 204         gpio_data_direction_register = gpio_controller + 0x1c;
 205 #endif
 206
 207         /* Use GPIO port C.  */
 208         gpio_data_register = gpio_controller + 0x08;
 209         gpio_data_direction_register = gpio_controller + 0x18;
 210
 211         printf("gpio_data_register      = %08x\n", gpio_data_register);
 212         printf("gpio_data_direction_reg = %08x\n", gpio_data_direction_register);
 213         /*
 214          * Configure bit 0 (TDO) as an input, and bits 1-5 (TDI, TCK
 215          * TMS, TRST, SRST) as outputs.  Drive TDI and TCK low, and
 216          * TMS/TRST/SRST high.
 217          */
 218         output_value = TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
 219         *gpio_data_register = output_value;
 220         nanosleep(ep93xx_zzzz);
 221
 222         /*
 223          * Configure the direction register.  1 = output, 0 = input.
 224          */
 225         *gpio_data_direction_register =
 226                 TDI_BIT | TCK_BIT | TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
 227
 228         nanosleep(ep93xx_zzzz);
 229         return ERROR_OK;
 230 }
 231
 232 int ep93xx_quit(void)
 233 {
 234
 235         return ERROR_OK;
 236 }