1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
42 static u8 output_value
= 0x0;
43 static int dev_mem_fd
;
44 static void *gpio_controller
;
45 static volatile u8
*gpio_data_register
;
46 static volatile u8
*gpio_data_direction_register
;
48 /* low level command set
50 int ep93xx_read(void);
51 void ep93xx_write(int tck
, int tms
, int tdi
);
52 void ep93xx_reset(int trst
, int srst
);
54 int ep93xx_speed(int speed
);
55 int ep93xx_register_commands(struct command_context_s
*cmd_ctx
);
56 int ep93xx_init(void);
57 int ep93xx_quit(void);
59 struct timespec ep93xx_zzzz
;
61 jtag_interface_t ep93xx_interface
=
65 .execute_queue
= bitbang_execute_queue
,
67 .support_statemove
= 0,
69 .speed
= ep93xx_speed
,
70 .register_commands
= ep93xx_register_commands
,
75 bitbang_interface_t ep93xx_bitbang
=
78 .write
= ep93xx_write
,
84 return !!(*gpio_data_register
& TDO_BIT
);
87 void ep93xx_write(int tck
, int tms
, int tdi
)
90 output_value
|= TCK_BIT
;
92 output_value
&= TCK_BIT
;
95 output_value
|= TMS_BIT
;
97 output_value
&= TMS_BIT
;
100 output_value
|= TDI_BIT
;
102 output_value
&= TDI_BIT
;
104 *gpio_data_register
= output_value
;
105 nanosleep(ep93xx_zzzz
);
108 /* (1) assert or (0) deassert reset lines */
109 void ep93xx_reset(int trst
, int srst
)
112 output_value
|= TRST_BIT
;
114 output_value
&= TRST_BIT
;
117 output_value
|= SRST_BIT
;
119 output_value
&= SRST_BIT
;
121 *gpio_data_register
= output_value
;
122 nanosleep(ep93xx_zzzz
);
125 int ep93xx_speed(int speed
)
131 int ep93xx_register_commands(struct command_context_s
*cmd_ctx
)
137 static int set_gonk_mode(void)
142 syscon
= mmap(NULL
, 4096, PROT_READ
| PROT_WRITE
,
143 MAP_SHARED
, dev_mem_fd
, 0x80930000);
144 if (syscon
== MAP_FAILED
) {
146 return ERROR_JTAG_INIT_FAILED
;
149 devicecfg
= *((volatile int *)(syscon
+ 0x80));
150 *((volatile int *)(syscon
+ 0xc0)) = 0xaa;
151 *((volatile int *)(syscon
+ 0x80)) = devicecfg
| 0x08000000;
153 munmap(syscon
, 4096);
158 int ep93xx_init(void)
162 bitbang_interface
= &ep93xx_bitbang
;
164 ep93xx_zzzz
.tv_sec
= 0;
165 ep93xx_zzzz
.tv_nsec
= 10000000;
167 dev_mem_fd
= open("/dev/mem", O_RDWR
| O_SYNC
);
168 if (dev_mem_fd
< 0) {
170 return ERROR_JTAG_INIT_FAILED
;
173 gpio_controller
= mmap(NULL
, 4096, PROT_READ
| PROT_WRITE
,
174 MAP_SHARED
, dev_mem_fd
, 0x80840000);
175 if (gpio_controller
== MAP_FAILED
) {
178 return ERROR_JTAG_INIT_FAILED
;
181 ret
= set_gonk_mode();
182 if (ret
!= ERROR_OK
) {
183 munmap(gpio_controller
, 4096);
189 /* Use GPIO port A. */
190 gpio_data_register
= gpio_controller
+ 0x00;
191 gpio_data_direction_register
= gpio_controller
+ 0x10;
194 /* Use GPIO port B. */
195 gpio_data_register
= gpio_controller
+ 0x04;
196 gpio_data_direction_register
= gpio_controller
+ 0x14;
198 /* Use GPIO port C. */
199 gpio_data_register
= gpio_controller
+ 0x08;
200 gpio_data_direction_register
= gpio_controller
+ 0x18;
202 /* Use GPIO port D. */
203 gpio_data_register
= gpio_controller
+ 0x0c;
204 gpio_data_direction_register
= gpio_controller
+ 0x1c;
207 /* Use GPIO port C. */
208 gpio_data_register
= gpio_controller
+ 0x08;
209 gpio_data_direction_register
= gpio_controller
+ 0x18;
211 printf("gpio_data_register = %08x\n", gpio_data_register
);
212 printf("gpio_data_direction_reg = %08x\n", gpio_data_direction_register
);
214 * Configure bit 0 (TDO) as an input, and bits 1-5 (TDI, TCK
215 * TMS, TRST, SRST) as outputs. Drive TDI and TCK low, and
216 * TMS/TRST/SRST high.
218 output_value
= TMS_BIT
| TRST_BIT
| SRST_BIT
| VCC_BIT
;
219 *gpio_data_register
= output_value
;
220 nanosleep(ep93xx_zzzz
);
223 * Configure the direction register. 1 = output, 0 = input.
225 *gpio_data_direction_register
=
226 TDI_BIT
| TCK_BIT
| TMS_BIT
| TRST_BIT
| SRST_BIT
| VCC_BIT
;
228 nanosleep(ep93xx_zzzz
);
232 int ep93xx_quit(void)
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