aa62ad5b14cbfeded29571b2bc980afeb4fdca89
[openocd.git] / src / jtag / ep93xx.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "log.h"
25 #include "jtag.h"
26 #include "bitbang.h"
27
28 #define TDO_BIT 1
29 #define TDI_BIT 2
30 #define TCK_BIT 4
31 #define TMS_BIT 8
32 #define TRST_BIT 16
33 #define SRST_BIT 32
34 #define VCC_BIT 64
35
36 /* system includes */
37 #include <string.h>
38 #include <stdlib.h>
39 #include <stdio.h>
40 #include <sys/mman.h>
41 #include <unistd.h>
42 #include <fcntl.h>
43
44 static u8 output_value = 0x0;
45 static int dev_mem_fd;
46 static void *gpio_controller;
47 static volatile u8 *gpio_data_register;
48 static volatile u8 *gpio_data_direction_register;
49
50 /* low level command set
51 */
52 int ep93xx_read(void);
53 void ep93xx_write(int tck, int tms, int tdi);
54 void ep93xx_reset(int trst, int srst);
55
56 int ep93xx_speed(int speed);
57 int ep93xx_register_commands(struct command_context_s *cmd_ctx);
58 int ep93xx_init(void);
59 int ep93xx_quit(void);
60
61 struct timespec ep93xx_zzzz;
62
63 jtag_interface_t ep93xx_interface =
64 {
65 .name = "ep93xx",
66
67 .execute_queue = bitbang_execute_queue,
68
69 .speed = ep93xx_speed,
70 .register_commands = ep93xx_register_commands,
71 .init = ep93xx_init,
72 .quit = ep93xx_quit,
73 };
74
75 bitbang_interface_t ep93xx_bitbang =
76 {
77 .read = ep93xx_read,
78 .write = ep93xx_write,
79 .reset = ep93xx_reset,
80 .blink = 0;
81 };
82
83 int ep93xx_read(void)
84 {
85 return !!(*gpio_data_register & TDO_BIT);
86 }
87
88 void ep93xx_write(int tck, int tms, int tdi)
89 {
90 if (tck)
91 output_value |= TCK_BIT;
92 else
93 output_value &= TCK_BIT;
94
95 if (tms)
96 output_value |= TMS_BIT;
97 else
98 output_value &= TMS_BIT;
99
100 if (tdi)
101 output_value |= TDI_BIT;
102 else
103 output_value &= TDI_BIT;
104
105 *gpio_data_register = output_value;
106 nanosleep(ep93xx_zzzz);
107 }
108
109 /* (1) assert or (0) deassert reset lines */
110 void ep93xx_reset(int trst, int srst)
111 {
112 if (trst == 0)
113 output_value |= TRST_BIT;
114 else if (trst == 1)
115 output_value &= TRST_BIT;
116
117 if (srst == 0)
118 output_value |= SRST_BIT;
119 else if (srst == 1)
120 output_value &= SRST_BIT;
121
122 *gpio_data_register = output_value;
123 nanosleep(ep93xx_zzzz);
124 }
125
126 int ep93xx_speed(int speed)
127 {
128
129 return ERROR_OK;
130 }
131
132 int ep93xx_register_commands(struct command_context_s *cmd_ctx)
133 {
134
135 return ERROR_OK;
136 }
137
138 static int set_gonk_mode(void)
139 {
140 void *syscon;
141 u32 devicecfg;
142
143 syscon = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
144 MAP_SHARED, dev_mem_fd, 0x80930000);
145 if (syscon == MAP_FAILED) {
146 perror("mmap");
147 return ERROR_JTAG_INIT_FAILED;
148 }
149
150 devicecfg = *((volatile int *)(syscon + 0x80));
151 *((volatile int *)(syscon + 0xc0)) = 0xaa;
152 *((volatile int *)(syscon + 0x80)) = devicecfg | 0x08000000;
153
154 munmap(syscon, 4096);
155
156 return ERROR_OK;
157 }
158
159 int ep93xx_init(void)
160 {
161 int ret;
162
163 bitbang_interface = &ep93xx_bitbang;
164
165 ep93xx_zzzz.tv_sec = 0;
166 ep93xx_zzzz.tv_nsec = 10000000;
167
168 dev_mem_fd = open("/dev/mem", O_RDWR | O_SYNC);
169 if (dev_mem_fd < 0) {
170 perror("open");
171 return ERROR_JTAG_INIT_FAILED;
172 }
173
174 gpio_controller = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
175 MAP_SHARED, dev_mem_fd, 0x80840000);
176 if (gpio_controller == MAP_FAILED) {
177 perror("mmap");
178 close(dev_mem_fd);
179 return ERROR_JTAG_INIT_FAILED;
180 }
181
182 ret = set_gonk_mode();
183 if (ret != ERROR_OK) {
184 munmap(gpio_controller, 4096);
185 close(dev_mem_fd);
186 return ret;
187 }
188
189 #if 0
190 /* Use GPIO port A. */
191 gpio_data_register = gpio_controller + 0x00;
192 gpio_data_direction_register = gpio_controller + 0x10;
193
194
195 /* Use GPIO port B. */
196 gpio_data_register = gpio_controller + 0x04;
197 gpio_data_direction_register = gpio_controller + 0x14;
198
199 /* Use GPIO port C. */
200 gpio_data_register = gpio_controller + 0x08;
201 gpio_data_direction_register = gpio_controller + 0x18;
202
203 /* Use GPIO port D. */
204 gpio_data_register = gpio_controller + 0x0c;
205 gpio_data_direction_register = gpio_controller + 0x1c;
206 #endif
207
208 /* Use GPIO port C. */
209 gpio_data_register = gpio_controller + 0x08;
210 gpio_data_direction_register = gpio_controller + 0x18;
211
212 INFO("gpio_data_register = %p\n", gpio_data_register);
213 INFO("gpio_data_direction_reg = %p\n", gpio_data_direction_register);
214 /*
215 * Configure bit 0 (TDO) as an input, and bits 1-5 (TDI, TCK
216 * TMS, TRST, SRST) as outputs. Drive TDI and TCK low, and
217 * TMS/TRST/SRST high.
218 */
219 output_value = TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
220 *gpio_data_register = output_value;
221 nanosleep(ep93xx_zzzz);
222
223 /*
224 * Configure the direction register. 1 = output, 0 = input.
225 */
226 *gpio_data_direction_register =
227 TDI_BIT | TCK_BIT | TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
228
229 nanosleep(ep93xx_zzzz);
230 return ERROR_OK;
231 }
232
233 int ep93xx_quit(void)
234 {
235
236 return ERROR_OK;
237 }

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)