src/jtag/swd.h

   1 /***************************************************************************
   2  *   Copyright (C) 2009-2010 by David Brownell                             *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  16  ***************************************************************************/
  17
  18 #ifndef OPENOCD_JTAG_SWD_H
  19 #define OPENOCD_JTAG_SWD_H
  20
  21 #include <target/arm_adi_v5.h>
  22
  23 /* Bits in SWD command packets, written from host to target
  24  * first bit on the wire is START
  25  */
  26 #define SWD_CMD_START   (1 << 0)        /* always set */
  27 #define SWD_CMD_APnDP   (1 << 1)        /* set only for AP access */
  28 #define SWD_CMD_RnW     (1 << 2)                /* set only for read access */
  29 #define SWD_CMD_A32     (3 << 3)                /* bits A[3:2] of register addr */
  30 #define SWD_CMD_PARITY  (1 << 5)        /* parity of APnDP|RnW|A32 */
  31 #define SWD_CMD_STOP    (0 << 6)        /* always clear for synch SWD */
  32 #define SWD_CMD_PARK    (1 << 7)        /* driven high by host */
  33 /* followed by TRN, 3-bits of ACK, TRN */
  34
  35 /**
  36  * Construct a "cmd" byte, in lSB bit order, which swd_driver.read_reg()
  37  * and swd_driver.write_reg() methods will use directly.
  38  */
  39 static inline uint8_t swd_cmd(bool is_read, bool is_ap, uint8_t regnum)
  40 {
  41         uint8_t cmd = (is_ap ? SWD_CMD_APnDP : 0)
  42                 | (is_read ? SWD_CMD_RnW : 0)
  43                 | ((regnum & 0xc) << 1);
  44
  45         /* 8 cmd bits 4:1 may be set */
  46         if (parity_u32(cmd))
  47                 cmd |= SWD_CMD_PARITY;
  48
  49         /* driver handles START, STOP, and TRN */
  50
  51         return cmd;
  52 }
  53
  54 /* SWD_ACK_* bits are defined in <target/arm_adi_v5.h> */
  55
  56 /**
  57  * Line reset.
  58  *
  59  * Line reset is at least 50 SWCLK cycles with SWDIO driven high, followed
  60  * by at least one idle (low) cycle.
  61  */
  62 static const uint8_t swd_seq_line_reset[] = {
  63         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x03
  64 };
  65 static const unsigned swd_seq_line_reset_len = 51;
  66
  67 /**
  68  * JTAG-to-SWD sequence.
  69  *
  70  * The JTAG-to-SWD sequence is at least 50 TCK/SWCLK cycles with TMS/SWDIO
  71  * high, putting either interface logic into reset state, followed by a
  72  * specific 16-bit sequence and finally a line reset in case the SWJ-DP was
  73  * already in SWD mode.
  74  */
  75 static const uint8_t swd_seq_jtag_to_swd[] = {
  76         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7b, 0x9e,
  77         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0f,
  78 };
  79 static const unsigned swd_seq_jtag_to_swd_len = 118;
  80
  81 /**
  82  * SWD-to-JTAG sequence.
  83  *
  84  * The SWD-to-JTAG sequence is at least 50 TCK/SWCLK cycles with TMS/SWDIO
  85  * high, putting either interface logic into reset state, followed by a
  86  * specific 16-bit sequence and finally at least 5 TCK cycles to put the
  87  * JTAG TAP in TLR.
  88  */
  89 static const uint8_t swd_seq_swd_to_jtag[] = {
  90         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0x9c, 0xff
  91 };
  92 static const unsigned swd_seq_swd_to_jtag_len = 71;
  93
  94 /**
  95  * SWD-to-dormant sequence.
  96  *
  97  * This is at least 50 SWCLK cycles with SWDIO high to put the interface
  98  * in reset state, followed by a specific 16-bit sequence.
  99  */
 100 static const uint8_t swd_seq_swd_to_dormant[] = {
 101         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0x8e, 0x03
 102 };
 103 static const unsigned swd_seq_swd_to_dormant_len = 66;
 104
 105 /**
 106  * Dormant-to-SWD sequence.
 107  *
 108  * This is at least 8 TCK/SWCLK cycles with TMS/SWDIO high to abort any ongoing
 109  * selection alert sequence, followed by a specific 128-bit selection alert
 110  * sequence, followed by 4 TCK/SWCLK cycles with TMS/SWDIO low, followed by
 111  * a specific protocol-dependent activation code. For SWD the activation code
 112  * is an 8-bit sequence. The sequence ends with a line reset.
 113  */
 114 static const uint8_t swd_seq_dormant_to_swd[] = {
 115         0xff,
 116         0x92, 0xf3, 0x09, 0x62, 0x95, 0x2d, 0x85, 0x86,
 117         0xe9, 0xaf, 0xdd, 0xe3, 0xa2, 0x0e, 0xbc, 0x19,
 118         0x10, 0xfa, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f
 119 };
 120 static const unsigned swd_seq_dormant_to_swd_len = 199;
 121
 122 enum swd_special_seq {
 123         LINE_RESET,
 124         JTAG_TO_SWD,
 125         SWD_TO_JTAG,
 126         SWD_TO_DORMANT,
 127         DORMANT_TO_SWD,
 128 };
 129
 130 struct swd_driver {
 131         /**
 132          * Initialize the debug link so it can perform SWD operations.
 133          *
 134          * As an example, this would switch a dual-mode debug adapter
 135          * into SWD mode and out of JTAG mode.
 136          *
 137          * @return ERROR_OK on success, else a negative fault code.
 138          */
 139         int (*init)(void);
 140
 141         /**
 142          * Set the SWCLK frequency of the SWD link.
 143          *
 144          * The driver should round the desired value, downwards if possible, to
 145          * the nearest supported frequency. A negative value should be ignored
 146          * and can be used to query the current setting. If the driver does not
 147          * support a variable frequency a fixed, nominal, value should be
 148          * returned.
 149          *
 150          * If the frequency is increased, it must not apply before the currently
 151          * queued transactions are executed. If the frequency is lowered, it may
 152          * apply immediately.
 153          *
 154          * @param hz The desired frequency in Hz.
 155          * @return The actual resulting frequency after rounding.
 156          */
 157         int_least32_t (*frequency)(int_least32_t hz);
 158
 159         /**
 160          * Queue a special SWDIO sequence.
 161          *
 162          * @param seq The special sequence to generate.
 163          * @return ERROR_OK if the sequence was queued, negative error if the
 164          * sequence is unsupported.
 165          */
 166         int (*switch_seq)(enum swd_special_seq seq);
 167
 168         /**
 169          * Queued read of an AP or DP register.
 170          *
 171          * @param Command byte with APnDP/RnW/addr/parity bits
 172          * @param Where to store value to read from register
 173          * @param ap_delay_hint Number of idle cycles that may be
 174          * needed after an AP access to avoid WAITs
 175          */
 176         void (*read_reg)(uint8_t cmd, uint32_t *value, uint32_t ap_delay_hint);
 177
 178         /**
 179          * Queued write of an AP or DP register.
 180          *
 181          * @param Command byte with APnDP/RnW/addr/parity bits
 182          * @param Value to be written to the register
 183          * @param ap_delay_hint Number of idle cycles that may be
 184          * needed after an AP access to avoid WAITs
 185          */
 186         void (*write_reg)(uint8_t cmd, uint32_t value, uint32_t ap_delay_hint);
 187
 188         /**
 189          * Execute any queued transactions and collect the result.
 190          *
 191          * @return ERROR_OK on success, Ack response code on WAIT/FAULT
 192          * or negative error code on other kinds of failure.
 193          */
 194         int (*run)(void);
 195
 196         /**
 197          * Configures data collection from the Single-wire
 198          * trace (SWO) signal.
 199          * @param swo true if SWO data collection should be routed.
 200          *
 201          * For example,  some debug adapters include a UART which
 202          * is normally connected to a microcontroller's UART TX,
 203          * but which may instead be connected to SWO for use in
 204          * collecting ITM (and possibly ETM) trace data.
 205          *
 206          * @return ERROR_OK on success, else a negative fault code.
 207          */
 208         int *(*trace)(bool swo);
 209 };
 210
 211 int swd_init_reset(struct command_context *cmd_ctx);
 212 void swd_add_reset(int req_srst);
 213
 214 #endif /* OPENOCD_JTAG_SWD_H */