src/jtag/swd.h

   1 /***************************************************************************
   2  *   Copyright (C) 2009-2010 by David Brownell                             *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  18  ***************************************************************************/
  19
  20 #ifndef SWD_H
  21 #define SWD_H
  22
  23 /* Bits in SWD command packets, written from host to target
  24  * first bit on the wire is START
  25  */
  26 #define SWD_CMD_START   (1 << 0)        /* always set */
  27 #define SWD_CMD_APnDP   (1 << 1)        /* set only for AP access */
  28 #define SWD_CMD_RnW     (1 << 2)                /* set only for read access */
  29 #define SWD_CMD_A32     (3 << 3)                /* bits A[3:2] of register addr */
  30 #define SWD_CMD_PARITY  (1 << 5)        /* parity of APnDP|RnW|A32 */
  31 #define SWD_CMD_STOP    (0 << 6)        /* always clear for synch SWD */
  32 #define SWD_CMD_PARK    (0 << 7)        /* not driven by host (pull high) */
  33 /* followed by TRN, 3-bits of ACK, TRN */
  34
  35 /**
  36  * Construct a "cmd" byte, in lSB bit order, which swd_driver.read_reg()
  37  * and swd_driver.write_reg() methods will use directly.
  38  */
  39 static inline uint8_t swd_cmd(bool is_read, bool is_ap, uint8_t regnum)
  40 {
  41         uint8_t cmd = (is_ap ? SWD_CMD_APnDP : 0)
  42                 | (is_read ? SWD_CMD_RnW : 0)
  43                 | ((regnum & 0xc) << 1);
  44
  45         /* 8 cmd bits 4:1 may be set */
  46         if (parity_u32(cmd))
  47                 cmd |= SWD_CMD_PARITY;
  48
  49         /* driver handles START, STOP, and TRN */
  50
  51         return cmd;
  52 }
  53
  54 /* SWD_ACK_* bits are defined in <target/arm_adi_v5.h> */
  55
  56 /*
  57  * FOR NOW  ... SWD driver ops are synchronous and return ACK
  58  * status ... no queuing.
  59  *
  60  * Individual ops are request/response, and fast-fail permits much
  61  * better fault handling.  Upper layers may queue if desired.
  62  */
  63
  64 struct swd_driver {
  65         /**
  66          * Initialize the debug link so it can perform
  67          * synchronous SWD operations.
  68          * @param trn value from WCR: how many clocks
  69          * to not drive the SWDIO line at certain points in
  70          * the SWD protocol (at least 1 clock).
  71          *
  72          * As an example, this would switch a dual-mode debug adapter
  73          * into SWD mode and out of JTAG mode.
  74           *
  75           * @return ERROR_OK on success, else a negative fault code.
  76          */
  77         int (*init)(uint8_t trn);
  78
  79
  80          /**
  81           * Synchronous read of an AP or DP register.
  82           *
  83           * @param cmd with APnDP/RnW/addr/parity bits
  84           * @param where to store value to read from register
  85           *
  86           * @return SWD_ACK_* code for the transaction
  87           *             or (negative) fault code
  88           */
  89          int (*read_reg)(uint8_t cmd, uint32_t *value);
  90
  91          /**
  92           * Synchronous write of an AP or DP register.
  93           *
  94           * @param cmd with APnDP/RnW/addr/parity bits
  95           * @param value to be written to the register
  96           *
  97           * @return SWD_ACK_* code for the transaction
  98           *             or (negative) fault code
  99           */
 100          int (*write_reg)(uint8_t cmd, uint32_t value);
 101
 102         /**
 103          * Configures data collection from the Single-wire
 104          * trace (SWO) signal.
 105          * @param swo true if SWO data collection should be routed.
 106          *
 107          * For example,  some debug adapters include a UART which
 108          * is normally connected to a microcontroller's UART TX,
 109          * but which may instead be connected to SWO for use in
 110          * collecting ITM (and possibly ETM) trace data.
 111           *
 112           * @return ERROR_OK on success, else a negative fault code.
 113          */
 114         int *(*trace)(bool swo);
 115 };
 116
 117 int swd_init_reset(struct command_context *cmd_ctx);
 118 void swd_add_reset(int req_srst);
 119
 120 bool transport_is_swd(void);
 121 bool transport_is_cmsis_dap(void);
 122
 123 #endif /* SWD_H */