src/jtag/swd.h

   1 /***************************************************************************
   2  *   Copyright (C) 2009-2010 by David Brownell                             *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  18  ***************************************************************************/
  19
  20 #ifndef SWD_H
  21 #define SWD_H
  22
  23 #include <target/arm_adi_v5.h>
  24
  25 /* Bits in SWD command packets, written from host to target
  26  * first bit on the wire is START
  27  */
  28 #define SWD_CMD_START   (1 << 0)        /* always set */
  29 #define SWD_CMD_APnDP   (1 << 1)        /* set only for AP access */
  30 #define SWD_CMD_RnW     (1 << 2)                /* set only for read access */
  31 #define SWD_CMD_A32     (3 << 3)                /* bits A[3:2] of register addr */
  32 #define SWD_CMD_PARITY  (1 << 5)        /* parity of APnDP|RnW|A32 */
  33 #define SWD_CMD_STOP    (0 << 6)        /* always clear for synch SWD */
  34 #define SWD_CMD_PARK    (1 << 7)        /* driven high by host */
  35 /* followed by TRN, 3-bits of ACK, TRN */
  36
  37 /**
  38  * Construct a "cmd" byte, in lSB bit order, which swd_driver.read_reg()
  39  * and swd_driver.write_reg() methods will use directly.
  40  */
  41 static inline uint8_t swd_cmd(bool is_read, bool is_ap, uint8_t regnum)
  42 {
  43         uint8_t cmd = (is_ap ? SWD_CMD_APnDP : 0)
  44                 | (is_read ? SWD_CMD_RnW : 0)
  45                 | ((regnum & 0xc) << 1);
  46
  47         /* 8 cmd bits 4:1 may be set */
  48         if (parity_u32(cmd))
  49                 cmd |= SWD_CMD_PARITY;
  50
  51         /* driver handles START, STOP, and TRN */
  52
  53         return cmd;
  54 }
  55
  56 /* SWD_ACK_* bits are defined in <target/arm_adi_v5.h> */
  57
  58 /**
  59  * Line reset.
  60  *
  61  * Line reset is at least 50 SWCLK cycles with SWDIO driven high, followed
  62  * by at least one idle (low) cycle.
  63  */
  64 static const uint8_t swd_seq_line_reset[] = {
  65         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x03
  66 };
  67 static const unsigned swd_seq_line_reset_len = 51;
  68
  69 /**
  70  * JTAG-to-SWD sequence.
  71  *
  72  * The JTAG-to-SWD sequence is at least 50 TCK/SWCLK cycles with TMS/SWDIO
  73  * high, putting either interface logic into reset state, followed by a
  74  * specific 16-bit sequence and finally a line reset in case the SWJ-DP was
  75  * already in SWD mode.
  76  */
  77 static const uint8_t swd_seq_jtag_to_swd[] = {
  78         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7b, 0x9e,
  79         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0f,
  80 };
  81 static const unsigned swd_seq_jtag_to_swd_len = 118;
  82
  83 /**
  84  * SWD-to-JTAG sequence.
  85  *
  86  * The SWD-to-JTAG sequence is at least 50 TCK/SWCLK cycles with TMS/SWDIO
  87  * high, putting either interface logic into reset state, followed by a
  88  * specific 16-bit sequence and finally at least 5 TCK cycles to put the
  89  * JTAG TAP in TLR.
  90  */
  91 static const uint8_t swd_seq_swd_to_jtag[] = {
  92         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0x9c, 0xff
  93 };
  94 static const unsigned swd_seq_swd_to_jtag_len = 71;
  95
  96 /**
  97  * SWD-to-dormant sequence.
  98  *
  99  * This is at least 50 SWCLK cycles with SWDIO high to put the interface
 100  * in reset state, followed by a specific 16-bit sequence.
 101  */
 102 static const uint8_t swd_seq_swd_to_dormant[] = {
 103         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0x8e, 0x03
 104 };
 105 static const unsigned swd_seq_swd_to_dormant_len = 66;
 106
 107 /**
 108  * Dormant-to-SWD sequence.
 109  *
 110  * This is at least 8 TCK/SWCLK cycles with TMS/SWDIO high to abort any ongoing
 111  * selection alert sequence, followed by a specific 128-bit selection alert
 112  * sequence, followed by 4 TCK/SWCLK cycles with TMS/SWDIO low, followed by
 113  * a specific protocol-dependent activation code. For SWD the activation code
 114  * is an 8-bit sequence. The sequence ends with a line reset.
 115  */
 116 static const uint8_t swd_seq_dormant_to_swd[] = {
 117         0xff,
 118         0x92, 0xf3, 0x09, 0x62, 0x95, 0x2d, 0x85, 0x86,
 119         0xe9, 0xaf, 0xdd, 0xe3, 0xa2, 0x0e, 0xbc, 0x19,
 120         0x10, 0xfa, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f
 121 };
 122 static const unsigned swd_seq_dormant_to_swd_len = 199;
 123
 124 enum swd_special_seq {
 125         LINE_RESET,
 126         JTAG_TO_SWD,
 127         SWD_TO_JTAG,
 128         SWD_TO_DORMANT,
 129         DORMANT_TO_SWD,
 130 };
 131
 132 struct swd_driver {
 133         /**
 134          * Initialize the debug link so it can perform SWD operations.
 135          *
 136          * As an example, this would switch a dual-mode debug adapter
 137          * into SWD mode and out of JTAG mode.
 138          *
 139          * @return ERROR_OK on success, else a negative fault code.
 140          */
 141         int (*init)(void);
 142
 143         /**
 144          * Set the SWCLK frequency of the SWD link.
 145          *
 146          * The driver should round the desired value, downwards if possible, to
 147          * the nearest supported frequency. A negative value should be ignored
 148          * and can be used to query the current setting. If the driver does not
 149          * support a variable frequency a fixed, nominal, value should be
 150          * returned.
 151          *
 152          * If the frequency is increased, it must not apply before the currently
 153          * queued transactions are executed. If the frequency is lowered, it may
 154          * apply immediately.
 155          *
 156          * @param dap The DAP controlled by the SWD link.
 157          * @param hz The desired frequency in Hz.
 158          * @return The actual resulting frequency after rounding.
 159          */
 160         int_least32_t (*frequency)(struct adiv5_dap *dap, int_least32_t hz);
 161
 162         /**
 163          * Queue a special SWDIO sequence.
 164          *
 165          * @param dap The DAP controlled by the SWD link.
 166          * @param seq The special sequence to generate.
 167          * @return ERROR_OK if the sequence was queued, negative error if the
 168          * sequence is unsupported.
 169          */
 170         int (*switch_seq)(struct adiv5_dap *dap, enum swd_special_seq seq);
 171
 172         /**
 173          * Queued read of an AP or DP register.
 174          *
 175          * @param dap The DAP controlled by the SWD link.
 176          * @param Command byte with APnDP/RnW/addr/parity bits
 177          * @param Where to store value to read from register
 178          */
 179         void (*read_reg)(struct adiv5_dap *dap, uint8_t cmd, uint32_t *value);
 180
 181         /**
 182          * Queued write of an AP or DP register.
 183          *
 184          * @param dap The DAP controlled by the SWD link.
 185          * @param Command byte with APnDP/RnW/addr/parity bits
 186          * @param Value to be written to the register
 187          */
 188         void (*write_reg)(struct adiv5_dap *dap, uint8_t cmd, uint32_t value);
 189
 190         /**
 191          * Execute any queued transactions and collect the result.
 192          *
 193          * @param dap The DAP controlled by the SWD link.
 194          * @return ERROR_OK on success, Ack response code on WAIT/FAULT
 195          * or negative error code on other kinds of failure.
 196          */
 197         int (*run)(struct adiv5_dap *dap);
 198
 199         /**
 200          * Configures data collection from the Single-wire
 201          * trace (SWO) signal.
 202          * @param swo true if SWO data collection should be routed.
 203          *
 204          * For example,  some debug adapters include a UART which
 205          * is normally connected to a microcontroller's UART TX,
 206          * but which may instead be connected to SWO for use in
 207          * collecting ITM (and possibly ETM) trace data.
 208          *
 209          * @return ERROR_OK on success, else a negative fault code.
 210          */
 211         int *(*trace)(struct adiv5_dap *dap, bool swo);
 212 };
 213
 214 int swd_init_reset(struct command_context *cmd_ctx);
 215 void swd_add_reset(int req_srst);
 216
 217 bool transport_is_swd(void);
 218 bool transport_is_cmsis_dap(void);
 219
 220 #endif /* SWD_H */