debug-feature: jtagtcpip, reduce performance impact of ping times
[openocd.git] / src / jtag / zy1000 / zy1000.c
1 /***************************************************************************
2 * Copyright (C) 2007-2010 by Øyvind Harboe *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
19
20 /* This file supports the zy1000 debugger: http://www.zylin.com/zy1000.html
21 *
22 * The zy1000 is a standalone debugger that has a web interface and
23 * requires no drivers on the developer host as all communication
24 * is via TCP/IP. The zy1000 gets it performance(~400-700kBytes/s
25 * DCC downloads @ 16MHz target) as it has an FPGA to hardware
26 * accelerate the JTAG commands, while offering *very* low latency
27 * between OpenOCD and the FPGA registers.
28 *
29 * The disadvantage of the zy1000 is that it has a feeble CPU compared to
30 * a PC(ca. 50-500 DMIPS depending on how one counts it), whereas a PC
31 * is on the order of 10000 DMIPS(i.e. at a factor of 20-200).
32 *
33 * The zy1000 revc hardware is using an Altera Nios CPU, whereas the
34 * revb is using ARM7 + Xilinx.
35 *
36 * See Zylin web pages or contact Zylin for more information.
37 *
38 * The reason this code is in OpenOCD rather than OpenOCD linked with the
39 * ZY1000 code is that OpenOCD is the long road towards getting
40 * libopenocd into place. libopenocd will support both low performance,
41 * low latency systems(embedded) and high performance high latency
42 * systems(PCs).
43 */
44 #ifdef HAVE_CONFIG_H
45 #include "config.h"
46 #endif
47
48 #include <target/embeddedice.h>
49 #include <jtag/minidriver.h>
50 #include <jtag/interface.h>
51 #include <time.h>
52 #include <helper/time_support.h>
53
54 #include <netinet/tcp.h>
55
56 #if BUILD_ECOSBOARD
57 #include "zy1000_version.h"
58
59 #include <cyg/hal/hal_io.h> // low level i/o
60 #include <cyg/hal/hal_diag.h>
61
62 #ifdef CYGPKG_HAL_NIOS2
63 #include <cyg/hal/io.h>
64 #include <cyg/firmwareutil/firmwareutil.h>
65 #endif
66
67 #define ZYLIN_VERSION GIT_ZY1000_VERSION
68 #define ZYLIN_DATE __DATE__
69 #define ZYLIN_TIME __TIME__
70 #define ZYLIN_OPENOCD GIT_OPENOCD_VERSION
71 #define ZYLIN_OPENOCD_VERSION "ZY1000 " ZYLIN_VERSION " " ZYLIN_DATE
72
73 #endif
74
75
76 /* The software needs to check if it's in RCLK mode or not */
77 static bool zy1000_rclk = false;
78
79 static int zy1000_khz(int khz, int *jtag_speed)
80 {
81 if (khz == 0)
82 {
83 *jtag_speed = 0;
84 }
85 else
86 {
87 *jtag_speed = 64000/khz;
88 }
89 return ERROR_OK;
90 }
91
92 static int zy1000_speed_div(int speed, int *khz)
93 {
94 if (speed == 0)
95 {
96 *khz = 0;
97 }
98 else
99 {
100 *khz = 64000/speed;
101 }
102
103 return ERROR_OK;
104 }
105
106 static bool readPowerDropout(void)
107 {
108 uint32_t state;
109 // sample and clear power dropout
110 ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x80);
111 ZY1000_PEEK(ZY1000_JTAG_BASE + 0x10, state);
112 bool powerDropout;
113 powerDropout = (state & 0x80) != 0;
114 return powerDropout;
115 }
116
117
118 static bool readSRST(void)
119 {
120 uint32_t state;
121 // sample and clear SRST sensing
122 ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x00000040);
123 ZY1000_PEEK(ZY1000_JTAG_BASE + 0x10, state);
124 bool srstAsserted;
125 srstAsserted = (state & 0x40) != 0;
126 return srstAsserted;
127 }
128
129 static int zy1000_srst_asserted(int *srst_asserted)
130 {
131 *srst_asserted = readSRST();
132 return ERROR_OK;
133 }
134
135 static int zy1000_power_dropout(int *dropout)
136 {
137 *dropout = readPowerDropout();
138 return ERROR_OK;
139 }
140
141 void zy1000_reset(int trst, int srst)
142 {
143 LOG_DEBUG("zy1000 trst=%d, srst=%d", trst, srst);
144
145 /* flush the JTAG FIFO. Not flushing the queue before messing with
146 * reset has such interesting bugs as causing hard to reproduce
147 * RCLK bugs as RCLK will stop responding when TRST is asserted
148 */
149 waitIdle();
150
151 if (!srst)
152 {
153 ZY1000_POKE(ZY1000_JTAG_BASE + 0x14, 0x00000001);
154 }
155 else
156 {
157 /* Danger!!! if clk != 0 when in
158 * idle in TAP_IDLE, reset halt on str912 will fail.
159 */
160 ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x00000001);
161 }
162
163 if (!trst)
164 {
165 ZY1000_POKE(ZY1000_JTAG_BASE + 0x14, 0x00000002);
166 }
167 else
168 {
169 /* assert reset */
170 ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x00000002);
171 }
172
173 if (trst||(srst && (jtag_get_reset_config() & RESET_SRST_PULLS_TRST)))
174 {
175 /* we're now in the RESET state until trst is deasserted */
176 ZY1000_POKE(ZY1000_JTAG_BASE + 0x20, TAP_RESET);
177 } else
178 {
179 /* We'll get RCLK failure when we assert TRST, so clear any false positives here */
180 ZY1000_POKE(ZY1000_JTAG_BASE + 0x14, 0x400);
181 }
182
183 /* wait for srst to float back up */
184 if ((!srst && ((jtag_get_reset_config() & RESET_TRST_PULLS_SRST) == 0))||
185 (!srst && !trst && (jtag_get_reset_config() & RESET_TRST_PULLS_SRST)))
186 {
187 bool first = true;
188 long long start = 0;
189 long total = 0;
190 for (;;)
191 {
192 // We don't want to sense our own reset, so we clear here.
193 // There is of course a timing hole where we could loose
194 // a "real" reset.
195 if (!readSRST())
196 {
197 if (total > 1)
198 {
199 LOG_USER("SRST took %dms to deassert", (int)total);
200 }
201 break;
202 }
203
204 if (first)
205 {
206 first = false;
207 start = timeval_ms();
208 }
209
210 total = timeval_ms() - start;
211
212 keep_alive();
213
214 if (total > 5000)
215 {
216 LOG_ERROR("SRST took too long to deassert: %dms", (int)total);
217 break;
218 }
219 }
220
221 }
222 }
223
224 int zy1000_speed(int speed)
225 {
226 /* flush JTAG master FIFO before setting speed */
227 waitIdle();
228
229 zy1000_rclk = false;
230
231 if (speed == 0)
232 {
233 /*0 means RCLK*/
234 ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x100);
235 zy1000_rclk = true;
236 LOG_DEBUG("jtag_speed using RCLK");
237 }
238 else
239 {
240 if (speed > 8190 || speed < 2)
241 {
242 LOG_USER("valid ZY1000 jtag_speed=[8190,2]. Divisor is 64MHz / even values between 8190-2, i.e. min 7814Hz, max 32MHz");
243 return ERROR_INVALID_ARGUMENTS;
244 }
245
246 LOG_USER("jtag_speed %d => JTAG clk=%f", speed, 64.0/(float)speed);
247 ZY1000_POKE(ZY1000_JTAG_BASE + 0x14, 0x100);
248 ZY1000_POKE(ZY1000_JTAG_BASE + 0x1c, speed&~1);
249 }
250 return ERROR_OK;
251 }
252
253 static bool savePower;
254
255
256 static void setPower(bool power)
257 {
258 savePower = power;
259 if (power)
260 {
261 ZY1000_POKE(ZY1000_JTAG_BASE + 0x14, 0x8);
262 } else
263 {
264 ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x8);
265 }
266 }
267
268 COMMAND_HANDLER(handle_power_command)
269 {
270 switch (CMD_ARGC)
271 {
272 case 1: {
273 bool enable;
274 COMMAND_PARSE_ON_OFF(CMD_ARGV[0], enable);
275 setPower(enable);
276 // fall through
277 }
278 case 0:
279 LOG_INFO("Target power %s", savePower ? "on" : "off");
280 break;
281 default:
282 return ERROR_INVALID_ARGUMENTS;
283 }
284
285 return ERROR_OK;
286 }
287
288 #if !BUILD_ECOSBOARD
289 static char *tcp_server = "notspecified";
290 static int jim_zy1000_server(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
291 {
292 if (argc != 2)
293 return JIM_ERR;
294
295 tcp_server = strdup(Jim_GetString(argv[1], NULL));
296
297 return JIM_OK;
298 }
299 #endif
300
301 #if BUILD_ECOSBOARD
302 /* Give TELNET a way to find out what version this is */
303 static int jim_zy1000_version(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
304 {
305 if ((argc < 1) || (argc > 3))
306 return JIM_ERR;
307 const char *version_str = NULL;
308
309 if (argc == 1)
310 {
311 version_str = ZYLIN_OPENOCD_VERSION;
312 } else
313 {
314 const char *str = Jim_GetString(argv[1], NULL);
315 const char *str2 = NULL;
316 if (argc > 2)
317 str2 = Jim_GetString(argv[2], NULL);
318 if (strcmp("openocd", str) == 0)
319 {
320 version_str = ZYLIN_OPENOCD;
321 }
322 else if (strcmp("zy1000", str) == 0)
323 {
324 version_str = ZYLIN_VERSION;
325 }
326 else if (strcmp("date", str) == 0)
327 {
328 version_str = ZYLIN_DATE;
329 }
330 else if (strcmp("time", str) == 0)
331 {
332 version_str = ZYLIN_TIME;
333 }
334 else if (strcmp("pcb", str) == 0)
335 {
336 #ifdef CYGPKG_HAL_NIOS2
337 version_str="c";
338 #else
339 version_str="b";
340 #endif
341 }
342 #ifdef CYGPKG_HAL_NIOS2
343 else if (strcmp("fpga", str) == 0)
344 {
345
346 /* return a list of 32 bit integers to describe the expected
347 * and actual FPGA
348 */
349 static char *fpga_id = "0x12345678 0x12345678 0x12345678 0x12345678";
350 uint32_t id, timestamp;
351 HAL_READ_UINT32(SYSID_BASE, id);
352 HAL_READ_UINT32(SYSID_BASE+4, timestamp);
353 sprintf(fpga_id, "0x%08x 0x%08x 0x%08x 0x%08x", id, timestamp, SYSID_ID, SYSID_TIMESTAMP);
354 version_str = fpga_id;
355 if ((argc>2) && (strcmp("time", str2) == 0))
356 {
357 time_t last_mod = timestamp;
358 char * t = ctime (&last_mod) ;
359 t[strlen(t)-1] = 0;
360 version_str = t;
361 }
362 }
363 #endif
364
365 else
366 {
367 return JIM_ERR;
368 }
369 }
370
371 Jim_SetResult(interp, Jim_NewStringObj(interp, version_str, -1));
372
373 return JIM_OK;
374 }
375 #endif
376
377 #ifdef CYGPKG_HAL_NIOS2
378
379
380 struct info_forward
381 {
382 void *data;
383 struct cyg_upgrade_info *upgraded_file;
384 };
385
386 static void report_info(void *data, const char * format, va_list args)
387 {
388 char *s = alloc_vprintf(format, args);
389 LOG_USER_N("%s", s);
390 free(s);
391 }
392
393 struct cyg_upgrade_info firmware_info =
394 {
395 (uint8_t *)0x84000000,
396 "/ram/firmware.phi",
397 "Firmware",
398 0x0300000,
399 0x1f00000 -
400 0x0300000,
401 "ZylinNiosFirmware\n",
402 report_info,
403 };
404
405 static int jim_zy1000_writefirmware(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
406 {
407 if (argc != 2)
408 return JIM_ERR;
409
410 int length;
411 const char *str = Jim_GetString(argv[1], &length);
412
413 /* */
414 int tmpFile;
415 if ((tmpFile = open(firmware_info.file, O_RDWR | O_CREAT | O_TRUNC)) <= 0)
416 {
417 return JIM_ERR;
418 }
419 bool success;
420 success = write(tmpFile, str, length) == length;
421 close(tmpFile);
422 if (!success)
423 return JIM_ERR;
424
425 if (!cyg_firmware_upgrade(NULL, firmware_info))
426 return JIM_ERR;
427
428 return JIM_OK;
429 }
430 #endif
431
432 static int
433 zylinjtag_Jim_Command_powerstatus(Jim_Interp *interp,
434 int argc,
435 Jim_Obj * const *argv)
436 {
437 if (argc != 1)
438 {
439 Jim_WrongNumArgs(interp, 1, argv, "powerstatus");
440 return JIM_ERR;
441 }
442
443 bool dropout = readPowerDropout();
444
445 Jim_SetResult(interp, Jim_NewIntObj(interp, dropout));
446
447 return JIM_OK;
448 }
449
450
451
452 int zy1000_quit(void)
453 {
454
455 return ERROR_OK;
456 }
457
458
459
460 int interface_jtag_execute_queue(void)
461 {
462 uint32_t empty;
463
464 waitIdle();
465
466 /* We must make sure to write data read back to memory location before we return
467 * from this fn
468 */
469 zy1000_flush_readqueue();
470
471 if (zy1000_rclk)
472 {
473 /* Only check for errors when using RCLK to speed up
474 * jtag over TCP/IP
475 */
476 ZY1000_PEEK(ZY1000_JTAG_BASE + 0x10, empty);
477 /* clear JTAG error register */
478 ZY1000_POKE(ZY1000_JTAG_BASE + 0x14, 0x400);
479
480 if ((empty&0x400) != 0)
481 {
482 LOG_WARNING("RCLK timeout");
483 /* the error is informative only as we don't want to break the firmware if there
484 * is a false positive.
485 */
486 // return ERROR_FAIL;
487 }
488 }
489 return ERROR_OK;
490 }
491
492
493
494
495 static void writeShiftValue(uint8_t *data, int bits);
496
497 // here we shuffle N bits out/in
498 static __inline void scanBits(const uint8_t *out_value, uint8_t *in_value, int num_bits, bool pause_now, tap_state_t shiftState, tap_state_t end_state)
499 {
500 tap_state_t pause_state = shiftState;
501 for (int j = 0; j < num_bits; j += 32)
502 {
503 int k = num_bits - j;
504 if (k > 32)
505 {
506 k = 32;
507 /* we have more to shift out */
508 } else if (pause_now)
509 {
510 /* this was the last to shift out this time */
511 pause_state = end_state;
512 }
513
514 // we have (num_bits + 7)/8 bytes of bits to toggle out.
515 // bits are pushed out LSB to MSB
516 uint32_t value;
517 value = 0;
518 if (out_value != NULL)
519 {
520 for (int l = 0; l < k; l += 8)
521 {
522 value|=out_value[(j + l)/8]<<l;
523 }
524 }
525 /* mask away unused bits for easier debugging */
526 if (k < 32)
527 {
528 value&=~(((uint32_t)0xffffffff) << k);
529 } else
530 {
531 /* Shifting by >= 32 is not defined by the C standard
532 * and will in fact shift by &0x1f bits on nios */
533 }
534
535 shiftValueInner(shiftState, pause_state, k, value);
536
537 if (in_value != NULL)
538 {
539 writeShiftValue(in_value + (j/8), k);
540 }
541 }
542 }
543
544 static __inline void scanFields(int num_fields, const struct scan_field *fields, tap_state_t shiftState, tap_state_t end_state)
545 {
546 for (int i = 0; i < num_fields; i++)
547 {
548 scanBits(fields[i].out_value,
549 fields[i].in_value,
550 fields[i].num_bits,
551 (i == num_fields-1),
552 shiftState,
553 end_state);
554 }
555 }
556
557 int interface_jtag_add_ir_scan(struct jtag_tap *active, const struct scan_field *fields, tap_state_t state)
558 {
559 int scan_size = 0;
560 struct jtag_tap *tap, *nextTap;
561 tap_state_t pause_state = TAP_IRSHIFT;
562
563 for (tap = jtag_tap_next_enabled(NULL); tap!= NULL; tap = nextTap)
564 {
565 nextTap = jtag_tap_next_enabled(tap);
566 if (nextTap==NULL)
567 {
568 pause_state = state;
569 }
570 scan_size = tap->ir_length;
571
572 /* search the list */
573 if (tap == active)
574 {
575 scanFields(1, fields, TAP_IRSHIFT, pause_state);
576 /* update device information */
577 buf_cpy(fields[0].out_value, tap->cur_instr, scan_size);
578
579 tap->bypass = 0;
580 } else
581 {
582 /* if a device isn't listed, set it to BYPASS */
583 assert(scan_size <= 32);
584 shiftValueInner(TAP_IRSHIFT, pause_state, scan_size, 0xffffffff);
585
586 tap->bypass = 1;
587 }
588 }
589
590 return ERROR_OK;
591 }
592
593
594
595
596
597 int interface_jtag_add_plain_ir_scan(int num_bits, const uint8_t *out_bits, uint8_t *in_bits, tap_state_t state)
598 {
599 scanBits(out_bits, in_bits, num_bits, true, TAP_IRSHIFT, state);
600 return ERROR_OK;
601 }
602
603 int interface_jtag_add_dr_scan(struct jtag_tap *active, int num_fields, const struct scan_field *fields, tap_state_t state)
604 {
605 struct jtag_tap *tap, *nextTap;
606 tap_state_t pause_state = TAP_DRSHIFT;
607 for (tap = jtag_tap_next_enabled(NULL); tap!= NULL; tap = nextTap)
608 {
609 nextTap = jtag_tap_next_enabled(tap);
610 if (nextTap==NULL)
611 {
612 pause_state = state;
613 }
614
615 /* Find a range of fields to write to this tap */
616 if (tap == active)
617 {
618 assert(!tap->bypass);
619
620 scanFields(num_fields, fields, TAP_DRSHIFT, pause_state);
621 } else
622 {
623 /* Shift out a 0 for disabled tap's */
624 assert(tap->bypass);
625 shiftValueInner(TAP_DRSHIFT, pause_state, 1, 0);
626 }
627 }
628 return ERROR_OK;
629 }
630
631 int interface_jtag_add_plain_dr_scan(int num_bits, const uint8_t *out_bits, uint8_t *in_bits, tap_state_t state)
632 {
633 scanBits(out_bits, in_bits, num_bits, true, TAP_DRSHIFT, state);
634 return ERROR_OK;
635 }
636
637 int interface_jtag_add_tlr()
638 {
639 setCurrentState(TAP_RESET);
640 return ERROR_OK;
641 }
642
643
644 int interface_jtag_add_reset(int req_trst, int req_srst)
645 {
646 zy1000_reset(req_trst, req_srst);
647 return ERROR_OK;
648 }
649
650 static int zy1000_jtag_add_clocks(int num_cycles, tap_state_t state, tap_state_t clockstate)
651 {
652 /* num_cycles can be 0 */
653 setCurrentState(clockstate);
654
655 /* execute num_cycles, 32 at the time. */
656 int i;
657 for (i = 0; i < num_cycles; i += 32)
658 {
659 int num;
660 num = 32;
661 if (num_cycles-i < num)
662 {
663 num = num_cycles-i;
664 }
665 shiftValueInner(clockstate, clockstate, num, 0);
666 }
667
668 #if !TEST_MANUAL()
669 /* finish in end_state */
670 setCurrentState(state);
671 #else
672 tap_state_t t = TAP_IDLE;
673 /* test manual drive code on any target */
674 int tms;
675 uint8_t tms_scan = tap_get_tms_path(t, state);
676 int tms_count = tap_get_tms_path_len(tap_get_state(), tap_get_end_state());
677
678 for (i = 0; i < tms_count; i++)
679 {
680 tms = (tms_scan >> i) & 1;
681 waitIdle();
682 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, tms);
683 }
684 waitIdle();
685 ZY1000_POKE(ZY1000_JTAG_BASE + 0x20, state);
686 #endif
687
688 return ERROR_OK;
689 }
690
691 int interface_jtag_add_runtest(int num_cycles, tap_state_t state)
692 {
693 return zy1000_jtag_add_clocks(num_cycles, state, TAP_IDLE);
694 }
695
696 int interface_jtag_add_clocks(int num_cycles)
697 {
698 return zy1000_jtag_add_clocks(num_cycles, cmd_queue_cur_state, cmd_queue_cur_state);
699 }
700
701 int interface_add_tms_seq(unsigned num_bits, const uint8_t *seq, enum tap_state state)
702 {
703 /*wait for the fifo to be empty*/
704 waitIdle();
705
706 for (unsigned i = 0; i < num_bits; i++)
707 {
708 int tms;
709
710 if (((seq[i/8] >> (i % 8)) & 1) == 0)
711 {
712 tms = 0;
713 }
714 else
715 {
716 tms = 1;
717 }
718
719 waitIdle();
720 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, tms);
721 }
722
723 waitIdle();
724 if (state != TAP_INVALID)
725 {
726 ZY1000_POKE(ZY1000_JTAG_BASE + 0x20, state);
727 } else
728 {
729 /* this would be normal if we are switching to SWD mode */
730 }
731 return ERROR_OK;
732 }
733
734 int interface_jtag_add_pathmove(int num_states, const tap_state_t *path)
735 {
736 int state_count;
737 int tms = 0;
738
739 state_count = 0;
740
741 tap_state_t cur_state = cmd_queue_cur_state;
742
743 uint8_t seq[16];
744 memset(seq, 0, sizeof(seq));
745 assert(num_states < (int)((sizeof(seq) * 8)));
746
747 while (num_states)
748 {
749 if (tap_state_transition(cur_state, false) == path[state_count])
750 {
751 tms = 0;
752 }
753 else if (tap_state_transition(cur_state, true) == path[state_count])
754 {
755 tms = 1;
756 }
757 else
758 {
759 LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition", tap_state_name(cur_state), tap_state_name(path[state_count]));
760 exit(-1);
761 }
762
763 seq[state_count/8] = seq[state_count/8] | (tms << (state_count % 8));
764
765 cur_state = path[state_count];
766 state_count++;
767 num_states--;
768 }
769
770 return interface_add_tms_seq(state_count, seq, cur_state);
771 }
772
773 static void jtag_pre_post_bits(struct jtag_tap *tap, int *pre, int *post)
774 {
775 /* bypass bits before and after */
776 int pre_bits = 0;
777 int post_bits = 0;
778
779 bool found = false;
780 struct jtag_tap *cur_tap, *nextTap;
781 for (cur_tap = jtag_tap_next_enabled(NULL); cur_tap!= NULL; cur_tap = nextTap)
782 {
783 nextTap = jtag_tap_next_enabled(cur_tap);
784 if (cur_tap == tap)
785 {
786 found = true;
787 } else
788 {
789 if (found)
790 {
791 post_bits++;
792 } else
793 {
794 pre_bits++;
795 }
796 }
797 }
798 *pre = pre_bits;
799 *post = post_bits;
800 }
801
802 /*
803 static const int embeddedice_num_bits[] = {32, 6};
804 uint32_t values[2];
805
806 values[0] = value;
807 values[1] = (1 << 5) | reg_addr;
808
809 jtag_add_dr_out(tap,
810 2,
811 embeddedice_num_bits,
812 values,
813 TAP_IDLE);
814 */
815
816 void embeddedice_write_dcc(struct jtag_tap *tap, int reg_addr, uint8_t *buffer, int little, int count)
817 {
818 #if 0
819 int i;
820 for (i = 0; i < count; i++)
821 {
822 embeddedice_write_reg_inner(tap, reg_addr, fast_target_buffer_get_u32(buffer, little));
823 buffer += 4;
824 }
825 #else
826 int pre_bits;
827 int post_bits;
828 jtag_pre_post_bits(tap, &pre_bits, &post_bits);
829
830 if ((pre_bits > 32) || (post_bits + 6 > 32))
831 {
832 int i;
833 for (i = 0; i < count; i++)
834 {
835 embeddedice_write_reg_inner(tap, reg_addr, fast_target_buffer_get_u32(buffer, little));
836 buffer += 4;
837 }
838 } else
839 {
840 int i;
841 for (i = 0; i < count; i++)
842 {
843 /* Fewer pokes means we get to use the FIFO more efficiently */
844 shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, pre_bits, 0);
845 shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, 32, fast_target_buffer_get_u32(buffer, little));
846 /* Danger! here we need to exit into the TAP_IDLE state to make
847 * DCC pick up this value.
848 */
849 shiftValueInner(TAP_DRSHIFT, TAP_IDLE, 6 + post_bits, (reg_addr | (1 << 5)));
850 buffer += 4;
851 }
852 }
853 #endif
854 }
855
856
857
858 int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap * tap, uint32_t opcode, uint32_t * data, size_t count)
859 {
860 /* bypass bits before and after */
861 int pre_bits;
862 int post_bits;
863 jtag_pre_post_bits(tap, &pre_bits, &post_bits);
864 post_bits+=2;
865
866 if ((pre_bits > 32) || (post_bits > 32))
867 {
868 int arm11_run_instr_data_to_core_noack_inner_default(struct jtag_tap * tap, uint32_t opcode, uint32_t * data, size_t count);
869 return arm11_run_instr_data_to_core_noack_inner_default(tap, opcode, data, count);
870 } else
871 {
872 static const int bits[] = {32, 2};
873 uint32_t values[] = {0, 0};
874
875 /* FIX!!!!!! the target_write_memory() API started this nasty problem
876 * with unaligned uint32_t * pointers... */
877 const uint8_t *t = (const uint8_t *)data;
878
879 while (--count > 0)
880 {
881 #if 1
882 /* Danger! This code doesn't update cmd_queue_cur_state, so
883 * invoking jtag_add_pathmove() before jtag_add_dr_out() after
884 * this loop would fail!
885 */
886 shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, pre_bits, 0);
887
888 uint32_t value;
889 value = *t++;
890 value |= (*t++<<8);
891 value |= (*t++<<16);
892 value |= (*t++<<24);
893
894 shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, 32, value);
895 /* minimum 2 bits */
896 shiftValueInner(TAP_DRSHIFT, TAP_DRPAUSE, post_bits, 0);
897
898 /* copy & paste from arm11_dbgtap.c */
899 //TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
900 /* KLUDGE! we have to flush the fifo or the Nios CPU locks up.
901 * This is probably a bug in the Avalon bus(cross clocking bridge?)
902 * or in the jtag registers module.
903 */
904 waitIdle();
905 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 1);
906 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 1);
907 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 0);
908 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 0);
909 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 0);
910 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 1);
911 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 0);
912 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 0);
913 /* we don't have to wait for the queue to empty here */
914 ZY1000_POKE(ZY1000_JTAG_BASE + 0x20, TAP_DRSHIFT);
915 waitIdle();
916 #else
917 static const tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] =
918 {
919 TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
920 };
921
922 values[0] = *t++;
923 values[0] |= (*t++<<8);
924 values[0] |= (*t++<<16);
925 values[0] |= (*t++<<24);
926
927 jtag_add_dr_out(tap,
928 2,
929 bits,
930 values,
931 TAP_IDLE);
932
933 jtag_add_pathmove(ARRAY_SIZE(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay),
934 arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay);
935 #endif
936 }
937
938 values[0] = *t++;
939 values[0] |= (*t++<<8);
940 values[0] |= (*t++<<16);
941 values[0] |= (*t++<<24);
942
943 /* This will happen on the last iteration updating cmd_queue_cur_state
944 * so we don't have to track it during the common code path
945 */
946 jtag_add_dr_out(tap,
947 2,
948 bits,
949 values,
950 TAP_IDLE);
951
952 return jtag_execute_queue();
953 }
954 }
955
956
957 static const struct command_registration zy1000_commands[] = {
958 {
959 .name = "power",
960 .handler = handle_power_command,
961 .mode = COMMAND_ANY,
962 .help = "Turn power switch to target on/off. "
963 "With no arguments, prints status.",
964 .usage = "('on'|'off)",
965 },
966 #if BUILD_ECOSBOARD
967 {
968 .name = "zy1000_version",
969 .mode = COMMAND_ANY,
970 .jim_handler = jim_zy1000_version,
971 .help = "Print version info for zy1000.",
972 .usage = "['openocd'|'zy1000'|'date'|'time'|'pcb'|'fpga']",
973 },
974 #else
975 {
976 .name = "zy1000_server",
977 .mode = COMMAND_ANY,
978 .jim_handler = jim_zy1000_server,
979 .help = "Tcpip address for ZY1000 server.",
980 .usage = "address",
981 },
982 #endif
983 {
984 .name = "powerstatus",
985 .mode = COMMAND_ANY,
986 .jim_handler = zylinjtag_Jim_Command_powerstatus,
987 .help = "Returns power status of target",
988 },
989 #ifdef CYGPKG_HAL_NIOS2
990 {
991 .name = "updatezy1000firmware",
992 .mode = COMMAND_ANY,
993 .jim_handler = jim_zy1000_writefirmware,
994 .help = "writes firmware to flash",
995 /* .usage = "some_string", */
996 },
997 #endif
998 COMMAND_REGISTRATION_DONE
999 };
1000
1001
1002 static int tcp_ip = -1;
1003
1004 /* Write large packets if we can */
1005 static size_t out_pos;
1006 static uint8_t out_buffer[16384];
1007 static size_t in_pos;
1008 static size_t in_write;
1009 static uint8_t in_buffer[16384];
1010
1011 static bool flush_writes(void)
1012 {
1013 bool ok = (write(tcp_ip, out_buffer, out_pos) == (int)out_pos);
1014 out_pos = 0;
1015 return ok;
1016 }
1017
1018 static bool writeLong(uint32_t l)
1019 {
1020 int i;
1021 for (i = 0; i < 4; i++)
1022 {
1023 uint8_t c = (l >> (i*8))&0xff;
1024 out_buffer[out_pos++] = c;
1025 if (out_pos >= sizeof(out_buffer))
1026 {
1027 if (!flush_writes())
1028 {
1029 return false;
1030 }
1031 }
1032 }
1033 return true;
1034 }
1035
1036 static bool readLong(uint32_t *out_data)
1037 {
1038 if (out_pos > 0)
1039 {
1040 if (!flush_writes())
1041 {
1042 return false;
1043 }
1044 }
1045
1046 uint32_t data = 0;
1047 int i;
1048 for (i = 0; i < 4; i++)
1049 {
1050 uint8_t c;
1051 if (in_pos == in_write)
1052 {
1053 /* read more */
1054 int t;
1055 t = read(tcp_ip, in_buffer, sizeof(in_buffer));
1056 if (t < 1)
1057 {
1058 return false;
1059 }
1060 in_write = (size_t) t;
1061 in_pos = 0;
1062 }
1063 c = in_buffer[in_pos++];
1064
1065 data |= (c << (i*8));
1066 }
1067 *out_data = data;
1068 return true;
1069 }
1070
1071 enum ZY1000_CMD
1072 {
1073 ZY1000_CMD_POKE = 0x0,
1074 ZY1000_CMD_PEEK = 0x8,
1075 ZY1000_CMD_SLEEP = 0x1,
1076 ZY1000_CMD_WAITIDLE = 2
1077 };
1078
1079
1080 #if !BUILD_ECOSBOARD
1081
1082 #include <sys/socket.h> /* for socket(), connect(), send(), and recv() */
1083 #include <arpa/inet.h> /* for sockaddr_in and inet_addr() */
1084
1085 /* We initialize this late since we need to know the server address
1086 * first.
1087 */
1088 static void tcpip_open(void)
1089 {
1090 if (tcp_ip >= 0)
1091 return;
1092
1093 struct sockaddr_in echoServAddr; /* Echo server address */
1094
1095 /* Create a reliable, stream socket using TCP */
1096 if ((tcp_ip = socket(PF_INET, SOCK_STREAM, IPPROTO_TCP)) < 0)
1097 {
1098 fprintf(stderr, "Failed to connect to zy1000 server\n");
1099 exit(-1);
1100 }
1101
1102 /* Construct the server address structure */
1103 memset(&echoServAddr, 0, sizeof(echoServAddr)); /* Zero out structure */
1104 echoServAddr.sin_family = AF_INET; /* Internet address family */
1105 echoServAddr.sin_addr.s_addr = inet_addr(tcp_server); /* Server IP address */
1106 echoServAddr.sin_port = htons(7777); /* Server port */
1107
1108 /* Establish the connection to the echo server */
1109 if (connect(tcp_ip, (struct sockaddr *) &echoServAddr, sizeof(echoServAddr)) < 0)
1110 {
1111 fprintf(stderr, "Failed to connect to zy1000 server\n");
1112 exit(-1);
1113 }
1114
1115 int flag = 1;
1116 setsockopt(tcp_ip, /* socket affected */
1117 IPPROTO_TCP, /* set option at TCP level */
1118 TCP_NODELAY, /* name of option */
1119 (char *)&flag, /* the cast is historical cruft */
1120 sizeof(int)); /* length of option value */
1121
1122 }
1123
1124
1125 /* send a poke */
1126 void zy1000_tcpout(uint32_t address, uint32_t data)
1127 {
1128 tcpip_open();
1129 if (!writeLong((ZY1000_CMD_POKE << 24) | address)||
1130 !writeLong(data))
1131 {
1132 fprintf(stderr, "Could not write to zy1000 server\n");
1133 exit(-1);
1134 }
1135 }
1136
1137 /* By sending the wait to the server, we avoid a readback
1138 * of status. Radically improves performance for this operation
1139 * with long ping times.
1140 */
1141 void waitIdle(void)
1142 {
1143 tcpip_open();
1144 if (!writeLong((ZY1000_CMD_WAITIDLE << 24)))
1145 {
1146 fprintf(stderr, "Could not write to zy1000 server\n");
1147 exit(-1);
1148 }
1149 }
1150
1151 uint32_t zy1000_tcpin(uint32_t address)
1152 {
1153 tcpip_open();
1154
1155 zy1000_flush_readqueue();
1156
1157 uint32_t data;
1158 if (!writeLong((ZY1000_CMD_PEEK << 24) | address)||
1159 !readLong(&data))
1160 {
1161 fprintf(stderr, "Could not read from zy1000 server\n");
1162 exit(-1);
1163 }
1164 return data;
1165 }
1166
1167 int interface_jtag_add_sleep(uint32_t us)
1168 {
1169 tcpip_open();
1170 if (!writeLong((ZY1000_CMD_SLEEP << 24))||
1171 !writeLong(us))
1172 {
1173 fprintf(stderr, "Could not read from zy1000 server\n");
1174 exit(-1);
1175 }
1176 return ERROR_OK;
1177 }
1178
1179 /* queue a readback */
1180 #define readqueue_size 16384
1181 static struct
1182 {
1183 uint8_t *dest;
1184 int bits;
1185 } readqueue[readqueue_size];
1186
1187 static int readqueue_pos = 0;
1188
1189 /* flush the readqueue, this means reading any data that
1190 * we're expecting and store them into the final position
1191 */
1192 void zy1000_flush_readqueue(void)
1193 {
1194 if (readqueue_pos == 0)
1195 {
1196 /* simply debugging by allowing easy breakpoints when there
1197 * is something to do. */
1198 return;
1199 }
1200 int i;
1201 tcpip_open();
1202 for (i = 0; i < readqueue_pos; i++)
1203 {
1204 uint32_t value;
1205 if (!readLong(&value))
1206 {
1207 fprintf(stderr, "Could not read from zy1000 server\n");
1208 exit(-1);
1209 }
1210
1211 uint8_t *in_value = readqueue[i].dest;
1212 int k = readqueue[i].bits;
1213
1214 // we're shifting in data to MSB, shift data to be aligned for returning the value
1215 value >>= 32-k;
1216
1217 for (int l = 0; l < k; l += 8)
1218 {
1219 in_value[l/8]=(value >> l)&0xff;
1220 }
1221 }
1222 readqueue_pos = 0;
1223 }
1224
1225 static void writeShiftValue(uint8_t *data, int bits)
1226 {
1227 waitIdle();
1228
1229 if (!writeLong((ZY1000_CMD_PEEK << 24) | (ZY1000_JTAG_BASE + 0xc)))
1230 {
1231 fprintf(stderr, "Could not read from zy1000 server\n");
1232 exit(-1);
1233 }
1234
1235 if (readqueue_pos >= readqueue_size)
1236 {
1237 zy1000_flush_readqueue();
1238 }
1239
1240 readqueue[readqueue_pos].dest = data;
1241 readqueue[readqueue_pos].bits = bits;
1242 readqueue_pos++;
1243 }
1244
1245 #else
1246
1247 static void writeShiftValue(uint8_t *data, int bits)
1248 {
1249 uint32_t value;
1250 waitIdle();
1251 ZY1000_PEEK(ZY1000_JTAG_BASE + 0xc, value);
1252 VERBOSE(LOG_INFO("getShiftValue %08x", value));
1253
1254 // data in, LSB to MSB
1255 // we're shifting in data to MSB, shift data to be aligned for returning the value
1256 value >>= 32 - bits;
1257
1258 for (int l = 0; l < bits; l += 8)
1259 {
1260 data[l/8]=(value >> l)&0xff;
1261 }
1262 }
1263
1264 #endif
1265
1266 #if BUILD_ECOSBOARD
1267 static char tcpip_stack[2048];
1268 static cyg_thread tcpip_thread_object;
1269 static cyg_handle_t tcpip_thread_handle;
1270
1271 static char watchdog_stack[2048];
1272 static cyg_thread watchdog_thread_object;
1273 static cyg_handle_t watchdog_thread_handle;
1274
1275 /* Infinite loop peeking & poking */
1276 static void tcpipserver(void)
1277 {
1278 for (;;)
1279 {
1280 uint32_t address;
1281 if (!readLong(&address))
1282 return;
1283 enum ZY1000_CMD c = (address >> 24) & 0xff;
1284 address &= 0xffffff;
1285 switch (c)
1286 {
1287 case ZY1000_CMD_POKE:
1288 {
1289 uint32_t data;
1290 if (!readLong(&data))
1291 return;
1292 address &= ~0x80000000;
1293 ZY1000_POKE(address + ZY1000_JTAG_BASE, data);
1294 break;
1295 }
1296 case ZY1000_CMD_PEEK:
1297 {
1298 uint32_t data;
1299 ZY1000_PEEK(address + ZY1000_JTAG_BASE, data);
1300 if (!writeLong(data))
1301 return;
1302 break;
1303 }
1304 case ZY1000_CMD_SLEEP:
1305 {
1306 uint32_t data;
1307 if (!readLong(&data))
1308 return;
1309 jtag_sleep(data);
1310 break;
1311 }
1312 case ZY1000_CMD_WAITIDLE:
1313 {
1314 waitIdle();
1315 break;
1316 }
1317 default:
1318 return;
1319 }
1320 }
1321 }
1322
1323
1324 static void tcpip_server(cyg_addrword_t data)
1325 {
1326 int so_reuseaddr_option = 1;
1327
1328 int fd;
1329 if ((fd = socket(AF_INET, SOCK_STREAM, 0)) == -1)
1330 {
1331 LOG_ERROR("error creating socket: %s", strerror(errno));
1332 exit(-1);
1333 }
1334
1335 setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (void*) &so_reuseaddr_option,
1336 sizeof(int));
1337
1338 struct sockaddr_in sin;
1339 unsigned int address_size;
1340 address_size = sizeof(sin);
1341 memset(&sin, 0, sizeof(sin));
1342 sin.sin_family = AF_INET;
1343 sin.sin_addr.s_addr = INADDR_ANY;
1344 sin.sin_port = htons(7777);
1345
1346 if (bind(fd, (struct sockaddr *) &sin, sizeof(sin)) == -1)
1347 {
1348 LOG_ERROR("couldn't bind to socket: %s", strerror(errno));
1349 exit(-1);
1350 }
1351
1352 if (listen(fd, 1) == -1)
1353 {
1354 LOG_ERROR("couldn't listen on socket: %s", strerror(errno));
1355 exit(-1);
1356 }
1357
1358
1359 for (;;)
1360 {
1361 tcp_ip = accept(fd, (struct sockaddr *) &sin, &address_size);
1362 if (tcp_ip < 0)
1363 {
1364 continue;
1365 }
1366
1367 int flag = 1;
1368 setsockopt(tcp_ip, /* socket affected */
1369 IPPROTO_TCP, /* set option at TCP level */
1370 TCP_NODELAY, /* name of option */
1371 (char *)&flag, /* the cast is historical cruft */
1372 sizeof(int)); /* length of option value */
1373
1374 bool save_poll = jtag_poll_get_enabled();
1375
1376 /* polling will screw up the "connection" */
1377 jtag_poll_set_enabled(false);
1378
1379 tcpipserver();
1380
1381 jtag_poll_set_enabled(save_poll);
1382
1383 close(tcp_ip);
1384
1385 }
1386 close(fd);
1387
1388 }
1389
1390 #ifdef WATCHDOG_BASE
1391 /* If we connect to port 8888 we must send a char every 10s or the board resets itself */
1392 static void watchdog_server(cyg_addrword_t data)
1393 {
1394 int so_reuseaddr_option = 1;
1395
1396 int fd;
1397 if ((fd = socket(AF_INET, SOCK_STREAM, 0)) == -1)
1398 {
1399 LOG_ERROR("error creating socket: %s", strerror(errno));
1400 exit(-1);
1401 }
1402
1403 setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (void*) &so_reuseaddr_option,
1404 sizeof(int));
1405
1406 struct sockaddr_in sin;
1407 unsigned int address_size;
1408 address_size = sizeof(sin);
1409 memset(&sin, 0, sizeof(sin));
1410 sin.sin_family = AF_INET;
1411 sin.sin_addr.s_addr = INADDR_ANY;
1412 sin.sin_port = htons(8888);
1413
1414 if (bind(fd, (struct sockaddr *) &sin, sizeof(sin)) == -1)
1415 {
1416 LOG_ERROR("couldn't bind to socket: %s", strerror(errno));
1417 exit(-1);
1418 }
1419
1420 if (listen(fd, 1) == -1)
1421 {
1422 LOG_ERROR("couldn't listen on socket: %s", strerror(errno));
1423 exit(-1);
1424 }
1425
1426
1427 for (;;)
1428 {
1429 int watchdog_ip = accept(fd, (struct sockaddr *) &sin, &address_size);
1430
1431 /* Start watchdog, must be reset every 10 seconds. */
1432 HAL_WRITE_UINT32(WATCHDOG_BASE + 4, 4);
1433
1434 if (watchdog_ip < 0)
1435 {
1436 LOG_ERROR("couldn't open watchdog socket: %s", strerror(errno));
1437 exit(-1);
1438 }
1439
1440 int flag = 1;
1441 setsockopt(watchdog_ip, /* socket affected */
1442 IPPROTO_TCP, /* set option at TCP level */
1443 TCP_NODELAY, /* name of option */
1444 (char *)&flag, /* the cast is historical cruft */
1445 sizeof(int)); /* length of option value */
1446
1447
1448 char buf;
1449 for (;;)
1450 {
1451 if (read(watchdog_ip, &buf, 1) == 1)
1452 {
1453 /* Reset timer */
1454 HAL_WRITE_UINT32(WATCHDOG_BASE + 8, 0x1234);
1455 /* Echo so we can telnet in and see that resetting works */
1456 write(watchdog_ip, &buf, 1);
1457 } else
1458 {
1459 /* Stop tickling the watchdog, the CPU will reset in < 10 seconds
1460 * now.
1461 */
1462 return;
1463 }
1464
1465 }
1466
1467 /* Never reached */
1468 }
1469 }
1470 #endif
1471
1472 int interface_jtag_add_sleep(uint32_t us)
1473 {
1474 jtag_sleep(us);
1475 return ERROR_OK;
1476 }
1477
1478 #endif
1479
1480
1481 int zy1000_init(void)
1482 {
1483 #if BUILD_ECOSBOARD
1484 LOG_USER("%s", ZYLIN_OPENOCD_VERSION);
1485 #endif
1486
1487 ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x30); // Turn on LED1 & LED2
1488
1489 setPower(true); // on by default
1490
1491
1492 /* deassert resets. Important to avoid infinite loop waiting for SRST to deassert */
1493 zy1000_reset(0, 0);
1494 zy1000_speed(jtag_get_speed());
1495
1496
1497 #if BUILD_ECOSBOARD
1498 cyg_thread_create(1, tcpip_server, (cyg_addrword_t) 0, "tcip/ip server",
1499 (void *) tcpip_stack, sizeof(tcpip_stack),
1500 &tcpip_thread_handle, &tcpip_thread_object);
1501 cyg_thread_resume(tcpip_thread_handle);
1502 #ifdef WATCHDOG_BASE
1503 cyg_thread_create(1, watchdog_server, (cyg_addrword_t) 0, "watchdog tcip/ip server",
1504 (void *) watchdog_stack, sizeof(watchdog_stack),
1505 &watchdog_thread_handle, &watchdog_thread_object);
1506 cyg_thread_resume(watchdog_thread_handle);
1507 #endif
1508 #endif
1509
1510 return ERROR_OK;
1511 }
1512
1513
1514
1515 struct jtag_interface zy1000_interface =
1516 {
1517 .name = "ZY1000",
1518 .supported = DEBUG_CAP_TMS_SEQ,
1519 .execute_queue = NULL,
1520 .speed = zy1000_speed,
1521 .commands = zy1000_commands,
1522 .init = zy1000_init,
1523 .quit = zy1000_quit,
1524 .khz = zy1000_khz,
1525 .speed_div = zy1000_speed_div,
1526 .power_dropout = zy1000_power_dropout,
1527 .srst_asserted = zy1000_srst_asserted,
1528 };
1529

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SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)