src/rtos/rtos_standard_stackings.c

   1 /***************************************************************************
   2  *   Copyright (C) 2011 by Broadcom Corporation                            *
   3  *   Evan Hunter - ehunter@broadcom.com                                    *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  19  ***************************************************************************/
  20
  21 #ifdef HAVE_CONFIG_H
  22 #include "config.h"
  23 #endif
  24
  25 #include "rtos.h"
  26 #include "target/armv7m.h"
  27
  28 static const struct stack_register_offset rtos_standard_Cortex_M3_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
  29         { 0x20, 32 },           /* r0   */
  30         { 0x24, 32 },           /* r1   */
  31         { 0x28, 32 },           /* r2   */
  32         { 0x2c, 32 },           /* r3   */
  33         { 0x00, 32 },           /* r4   */
  34         { 0x04, 32 },           /* r5   */
  35         { 0x08, 32 },           /* r6   */
  36         { 0x0c, 32 },           /* r7   */
  37         { 0x10, 32 },           /* r8   */
  38         { 0x14, 32 },           /* r9   */
  39         { 0x18, 32 },           /* r10  */
  40         { 0x1c, 32 },           /* r11  */
  41         { 0x30, 32 },           /* r12  */
  42         { -2,   32 },           /* sp   */
  43         { 0x34, 32 },           /* lr   */
  44         { 0x38, 32 },           /* pc   */
  45         { 0x3c, 32 },           /* xPSR */
  46 };
  47
  48 static const struct stack_register_offset rtos_standard_Cortex_M4F_stack_offsets[] = {
  49         { 0x24, 32 },           /* r0   */
  50         { 0x28, 32 },           /* r1   */
  51         { 0x2c, 32 },           /* r2   */
  52         { 0x30, 32 },           /* r3   */
  53         { 0x00, 32 },           /* r4   */
  54         { 0x04, 32 },           /* r5   */
  55         { 0x08, 32 },           /* r6   */
  56         { 0x0c, 32 },           /* r7   */
  57         { 0x10, 32 },           /* r8   */
  58         { 0x14, 32 },           /* r9   */
  59         { 0x18, 32 },           /* r10  */
  60         { 0x1c, 32 },           /* r11  */
  61         { 0x34, 32 },           /* r12  */
  62         { -2,   32 },           /* sp   */
  63         { 0x38, 32 },           /* lr   */
  64         { 0x3c, 32 },           /* pc   */
  65         { 0x40, 32 },           /* xPSR */
  66 };
  67
  68 static const struct stack_register_offset rtos_standard_Cortex_M4F_FPU_stack_offsets[] = {
  69         { 0x64, 32 },           /* r0   */
  70         { 0x68, 32 },           /* r1   */
  71         { 0x6c, 32 },           /* r2   */
  72         { 0x70, 32 },           /* r3   */
  73         { 0x00, 32 },           /* r4   */
  74         { 0x04, 32 },           /* r5   */
  75         { 0x08, 32 },           /* r6   */
  76         { 0x0c, 32 },           /* r7   */
  77         { 0x10, 32 },           /* r8   */
  78         { 0x14, 32 },           /* r9   */
  79         { 0x18, 32 },           /* r10  */
  80         { 0x1c, 32 },           /* r11  */
  81         { 0x74, 32 },           /* r12  */
  82         { -2,   32 },           /* sp   */
  83         { 0x78, 32 },           /* lr   */
  84         { 0x7c, 32 },           /* pc   */
  85         { 0x80, 32 },           /* xPSR */
  86 };
  87
  88
  89 static const struct stack_register_offset rtos_standard_Cortex_R4_stack_offsets[] = {
  90         { 0x08, 32 },           /* r0  (a1)   */
  91         { 0x0c, 32 },           /* r1  (a2)  */
  92         { 0x10, 32 },           /* r2  (a3)  */
  93         { 0x14, 32 },           /* r3  (a4)  */
  94         { 0x18, 32 },           /* r4  (v1)  */
  95         { 0x1c, 32 },           /* r5  (v2)  */
  96         { 0x20, 32 },           /* r6  (v3)  */
  97         { 0x24, 32 },           /* r7  (v4)  */
  98         { 0x28, 32 },           /* r8  (a1)  */
  99         { 0x2c, 32 },           /* r9  (sb)  */
 100         { 0x30, 32 },           /* r10 (sl) */
 101         { 0x34, 32 },           /* r11 (fp) */
 102         { 0x38, 32 },           /* r12 (ip) */
 103         { -2,   32 },           /* sp   */
 104         { 0x3c, 32 },           /* lr   */
 105         { 0x40, 32 },           /* pc   */
 106         { -1,   96 },           /* FPA1 */
 107         { -1,   96 },           /* FPA2 */
 108         { -1,   96 },           /* FPA3 */
 109         { -1,   96 },           /* FPA4 */
 110         { -1,   96 },           /* FPA5 */
 111         { -1,   96 },           /* FPA6 */
 112         { -1,   96 },           /* FPA7 */
 113         { -1,   96 },           /* FPA8 */
 114         { -1,   32 },           /* FPS  */
 115         { 0x04, 32 },           /* CSPR */
 116 };
 117
 118 static const struct stack_register_offset rtos_standard_NDS32_N1068_stack_offsets[] = {
 119         { 0x88, 32 },           /* R0  */
 120         { 0x8C, 32 },           /* R1 */
 121         { 0x14, 32 },           /* R2 */
 122         { 0x18, 32 },           /* R3 */
 123         { 0x1C, 32 },           /* R4 */
 124         { 0x20, 32 },           /* R5 */
 125         { 0x24, 32 },           /* R6 */
 126         { 0x28, 32 },           /* R7 */
 127         { 0x2C, 32 },           /* R8 */
 128         { 0x30, 32 },           /* R9 */
 129         { 0x34, 32 },           /* R10 */
 130         { 0x38, 32 },           /* R11 */
 131         { 0x3C, 32 },           /* R12 */
 132         { 0x40, 32 },           /* R13 */
 133         { 0x44, 32 },           /* R14 */
 134         { 0x48, 32 },           /* R15 */
 135         { 0x4C, 32 },           /* R16 */
 136         { 0x50, 32 },           /* R17 */
 137         { 0x54, 32 },           /* R18 */
 138         { 0x58, 32 },           /* R19 */
 139         { 0x5C, 32 },           /* R20 */
 140         { 0x60, 32 },           /* R21 */
 141         { 0x64, 32 },           /* R22 */
 142         { 0x68, 32 },           /* R23 */
 143         { 0x6C, 32 },           /* R24 */
 144         { 0x70, 32 },           /* R25 */
 145         { 0x74, 32 },           /* R26 */
 146         { 0x78, 32 },           /* R27 */
 147         { 0x7C, 32 },           /* R28 */
 148         { 0x80, 32 },           /* R29 */
 149         { 0x84, 32 },           /* R30 (LP) */
 150         { 0x00, 32 },           /* R31 (SP) */
 151         { 0x04, 32 },           /* PSW */
 152         { 0x08, 32 },           /* IPC */
 153         { 0x0C, 32 },           /* IPSW */
 154         { 0x10, 32 },           /* IFC_LP */
 155 };
 156
 157 static int64_t rtos_generic_stack_align(struct target *target,
 158         const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
 159         int64_t stack_ptr, int align)
 160 {
 161         int64_t new_stack_ptr;
 162         int64_t aligned_stack_ptr;
 163         new_stack_ptr = stack_ptr - stacking->stack_growth_direction *
 164                 stacking->stack_registers_size;
 165         aligned_stack_ptr = new_stack_ptr & ~((int64_t)align - 1);
 166         if (aligned_stack_ptr != new_stack_ptr &&
 167                 stacking->stack_growth_direction == -1) {
 168                 /* If we have a downward growing stack, the simple alignment code
 169                  * above results in a wrong result (since it rounds down to nearest
 170                  * alignment).  We want to round up so add an extra align.
 171                  */
 172                 aligned_stack_ptr += (int64_t)align;
 173         }
 174         return aligned_stack_ptr;
 175 }
 176
 177 int64_t rtos_generic_stack_align8(struct target *target,
 178         const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
 179         int64_t stack_ptr)
 180 {
 181         return rtos_generic_stack_align(target, stack_data,
 182                         stacking, stack_ptr, 8);
 183 }
 184
 185 /* The Cortex M3 will indicate that an alignment adjustment
 186  * has been done on the stack by setting bit 9 of the stacked xPSR
 187  * register.  In this case, we can just add an extra 4 bytes to get
 188  * to the program stack.  Note that some places in the ARM documentation
 189  * make this a little unclear but the padding takes place before the
 190  * normal exception stacking - so xPSR is always available at a fixed
 191  * location.
 192  *
 193  * Relevant documentation:
 194  *    Cortex-M series processors -> Cortex-M3 -> Revision: xxx ->
 195  *        Cortex-M3 Devices Generic User Guide -> The Cortex-M3 Processor ->
 196  *        Exception Model -> Exception entry and return -> Exception entry
 197  *    Cortex-M series processors -> Cortex-M3 -> Revision: xxx ->
 198  *        Cortex-M3 Devices Generic User Guide -> Cortex-M3 Peripherals ->
 199  *        System control block -> Configuration and Control Register (STKALIGN)
 200  *
 201  * This is just a helper function for use in the calculate_process_stack
 202  * function for a given architecture/rtos.
 203  */
 204 int64_t rtos_Cortex_M_stack_align(struct target *target,
 205         const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
 206         int64_t stack_ptr, size_t xpsr_offset)
 207 {
 208         const uint32_t ALIGN_NEEDED = (1 << 9);
 209         uint32_t xpsr;
 210         int64_t new_stack_ptr;
 211
 212         new_stack_ptr = stack_ptr - stacking->stack_growth_direction *
 213                 stacking->stack_registers_size;
 214         xpsr = (target->endianness == TARGET_LITTLE_ENDIAN) ?
 215                         le_to_h_u32(&stack_data[xpsr_offset]) :
 216                         be_to_h_u32(&stack_data[xpsr_offset]);
 217         if ((xpsr & ALIGN_NEEDED) != 0) {
 218                 LOG_DEBUG("XPSR(0x%08" PRIx32 ") indicated stack alignment was necessary\r\n",
 219                         xpsr);
 220                 new_stack_ptr -= (stacking->stack_growth_direction * 4);
 221         }
 222         return new_stack_ptr;
 223 }
 224
 225 static int64_t rtos_standard_Cortex_M3_stack_align(struct target *target,
 226         const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
 227         int64_t stack_ptr)
 228 {
 229         const int XPSR_OFFSET = 0x3c;
 230         return rtos_Cortex_M_stack_align(target, stack_data, stacking,
 231                 stack_ptr, XPSR_OFFSET);
 232 }
 233
 234 const struct rtos_register_stacking rtos_standard_Cortex_M3_stacking = {
 235         0x40,                                   /* stack_registers_size */
 236         -1,                                             /* stack_growth_direction */
 237         ARMV7M_NUM_CORE_REGS,   /* num_output_registers */
 238         rtos_standard_Cortex_M3_stack_align,    /* stack_alignment */
 239         rtos_standard_Cortex_M3_stack_offsets   /* register_offsets */
 240 };
 241
 242 const struct rtos_register_stacking rtos_standard_Cortex_M4F_stacking = {
 243         0x44,                                   /* stack_registers_size 4 more for LR*/
 244         -1,                                             /* stack_growth_direction */
 245         ARMV7M_NUM_CORE_REGS,   /* num_output_registers */
 246         rtos_standard_Cortex_M3_stack_align,    /* stack_alignment */
 247         rtos_standard_Cortex_M4F_stack_offsets  /* register_offsets */
 248 };
 249
 250 const struct rtos_register_stacking rtos_standard_Cortex_M4F_FPU_stacking = {
 251         0xcc,                                   /* stack_registers_size 4 more for LR + 48 more for FPU S0-S15 register*/
 252         -1,                                             /* stack_growth_direction */
 253         ARMV7M_NUM_CORE_REGS,   /* num_output_registers */
 254         rtos_standard_Cortex_M3_stack_align,    /* stack_alignment */
 255         rtos_standard_Cortex_M4F_FPU_stack_offsets      /* register_offsets */
 256 };
 257
 258 const struct rtos_register_stacking rtos_standard_Cortex_R4_stacking = {
 259         0x48,                           /* stack_registers_size */
 260         -1,                                     /* stack_growth_direction */
 261         26,                                     /* num_output_registers */
 262         rtos_generic_stack_align8,      /* stack_alignment */
 263         rtos_standard_Cortex_R4_stack_offsets   /* register_offsets */
 264 };
 265
 266 const struct rtos_register_stacking rtos_standard_NDS32_N1068_stacking = {
 267         0x90,                           /* stack_registers_size */
 268         -1,                                     /* stack_growth_direction */
 269         32,                                     /* num_output_registers */
 270         rtos_generic_stack_align8,      /* stack_alignment */
 271         rtos_standard_NDS32_N1068_stack_offsets /* register_offsets */
 272 };