src/rtos/rtos_standard_stackings.c

   1 /***************************************************************************
   2  *   Copyright (C) 2011 by Broadcom Corporation                            *
   3  *   Evan Hunter - ehunter@broadcom.com                                    *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  17  ***************************************************************************/
  18
  19 #ifdef HAVE_CONFIG_H
  20 #include "config.h"
  21 #endif
  22
  23 #include "rtos.h"
  24 #include "target/armv7m.h"
  25
  26 static const struct stack_register_offset rtos_standard_cortex_m3_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
  27         { ARMV7M_R0,   0x20, 32 },              /* r0   */
  28         { ARMV7M_R1,   0x24, 32 },              /* r1   */
  29         { ARMV7M_R2,   0x28, 32 },              /* r2   */
  30         { ARMV7M_R3,   0x2c, 32 },              /* r3   */
  31         { ARMV7M_R4,   0x00, 32 },              /* r4   */
  32         { ARMV7M_R5,   0x04, 32 },              /* r5   */
  33         { ARMV7M_R6,   0x08, 32 },              /* r6   */
  34         { ARMV7M_R7,   0x0c, 32 },              /* r7   */
  35         { ARMV7M_R8,   0x10, 32 },              /* r8   */
  36         { ARMV7M_R9,   0x14, 32 },              /* r9   */
  37         { ARMV7M_R10,  0x18, 32 },              /* r10  */
  38         { ARMV7M_R11,  0x1c, 32 },              /* r11  */
  39         { ARMV7M_R12,  0x30, 32 },              /* r12  */
  40         { ARMV7M_R13,  -2,   32 },              /* sp   */
  41         { ARMV7M_R14,  0x34, 32 },              /* lr   */
  42         { ARMV7M_PC,   0x38, 32 },              /* pc   */
  43         { ARMV7M_xPSR, 0x3c, 32 },              /* xPSR */
  44 };
  45
  46 static const struct stack_register_offset rtos_standard_cortex_m4f_stack_offsets[] = {
  47         { ARMV7M_R0,   0x24, 32 },              /* r0   */
  48         { ARMV7M_R1,   0x28, 32 },              /* r1   */
  49         { ARMV7M_R2,   0x2c, 32 },              /* r2   */
  50         { ARMV7M_R3,   0x30, 32 },              /* r3   */
  51         { ARMV7M_R4,   0x00, 32 },              /* r4   */
  52         { ARMV7M_R5,   0x04, 32 },              /* r5   */
  53         { ARMV7M_R6,   0x08, 32 },              /* r6   */
  54         { ARMV7M_R7,   0x0c, 32 },              /* r7   */
  55         { ARMV7M_R8,   0x10, 32 },              /* r8   */
  56         { ARMV7M_R9,   0x14, 32 },              /* r9   */
  57         { ARMV7M_R10,  0x18, 32 },              /* r10  */
  58         { ARMV7M_R11,  0x1c, 32 },              /* r11  */
  59         { ARMV7M_R12,  0x34, 32 },              /* r12  */
  60         { ARMV7M_R13,  -2,   32 },              /* sp   */
  61         { ARMV7M_R14,  0x38, 32 },              /* lr   */
  62         { ARMV7M_PC,   0x3c, 32 },              /* pc   */
  63         { ARMV7M_xPSR, 0x40, 32 },              /* xPSR */
  64 };
  65
  66 static const struct stack_register_offset rtos_standard_cortex_m4f_fpu_stack_offsets[] = {
  67         { ARMV7M_R0,   0x64, 32 },              /* r0   */
  68         { ARMV7M_R1,   0x68, 32 },              /* r1   */
  69         { ARMV7M_R2,   0x6c, 32 },              /* r2   */
  70         { ARMV7M_R3,   0x70, 32 },              /* r3   */
  71         { ARMV7M_R4,   0x00, 32 },              /* r4   */
  72         { ARMV7M_R5,   0x04, 32 },              /* r5   */
  73         { ARMV7M_R6,   0x08, 32 },              /* r6   */
  74         { ARMV7M_R7,   0x0c, 32 },              /* r7   */
  75         { ARMV7M_R8,   0x10, 32 },              /* r8   */
  76         { ARMV7M_R9,   0x14, 32 },              /* r9   */
  77         { ARMV7M_R10,  0x18, 32 },              /* r10  */
  78         { ARMV7M_R11,  0x1c, 32 },              /* r11  */
  79         { ARMV7M_R12,  0x74, 32 },              /* r12  */
  80         { ARMV7M_R13,  -2,   32 },              /* sp   */
  81         { ARMV7M_R14,  0x78, 32 },              /* lr   */
  82         { ARMV7M_PC,   0x7c, 32 },              /* pc   */
  83         { ARMV7M_xPSR, 0x80, 32 },              /* xPSR */
  84 };
  85
  86
  87 static const struct stack_register_offset rtos_standard_cortex_r4_stack_offsets[] = {
  88         { 0,  0x08, 32 },               /* r0  (a1)   */
  89         { 1,  0x0c, 32 },               /* r1  (a2)  */
  90         { 2,  0x10, 32 },               /* r2  (a3)  */
  91         { 3,  0x14, 32 },               /* r3  (a4)  */
  92         { 4,  0x18, 32 },               /* r4  (v1)  */
  93         { 5,  0x1c, 32 },               /* r5  (v2)  */
  94         { 6,  0x20, 32 },               /* r6  (v3)  */
  95         { 7,  0x24, 32 },               /* r7  (v4)  */
  96         { 8,  0x28, 32 },               /* r8  (a1)  */
  97         { 10, 0x2c, 32 },               /* r9  (sb)  */
  98         { 11, 0x30, 32 },               /* r10 (sl) */
  99         { 12, 0x34, 32 },               /* r11 (fp) */
 100         { 13, 0x38, 32 },               /* r12 (ip) */
 101         { 14, -2,   32 },               /* sp   */
 102         { 15, 0x3c, 32 },               /* lr   */
 103         { 16, 0x40, 32 },               /* pc   */
 104         { 17, -1,   96 },               /* FPA1 */
 105         { 18, -1,   96 },               /* FPA2 */
 106         { 19, -1,   96 },               /* FPA3 */
 107         { 20, -1,   96 },               /* FPA4 */
 108         { 21, -1,   96 },               /* FPA5 */
 109         { 22, -1,   96 },               /* FPA6 */
 110         { 23, -1,   96 },               /* FPA7 */
 111         { 24, -1,   96 },               /* FPA8 */
 112         { 25, -1,   32 },               /* FPS  */
 113         { 26, 0x04, 32 },               /* CSPR */
 114 };
 115
 116 static const struct stack_register_offset rtos_standard_nds32_n1068_stack_offsets[] = {
 117         { 0,  0x88, 32 },               /* R0  */
 118         { 1,  0x8C, 32 },               /* R1 */
 119         { 2,  0x14, 32 },               /* R2 */
 120         { 3,  0x18, 32 },               /* R3 */
 121         { 4,  0x1C, 32 },               /* R4 */
 122         { 5,  0x20, 32 },               /* R5 */
 123         { 6,  0x24, 32 },               /* R6 */
 124         { 7,  0x28, 32 },               /* R7 */
 125         { 8,  0x2C, 32 },               /* R8 */
 126         { 9,  0x30, 32 },               /* R9 */
 127         { 10, 0x34, 32 },               /* R10 */
 128         { 11, 0x38, 32 },               /* R11 */
 129         { 12, 0x3C, 32 },               /* R12 */
 130         { 13, 0x40, 32 },               /* R13 */
 131         { 14, 0x44, 32 },               /* R14 */
 132         { 15, 0x48, 32 },               /* R15 */
 133         { 16, 0x4C, 32 },               /* R16 */
 134         { 17, 0x50, 32 },               /* R17 */
 135         { 18, 0x54, 32 },               /* R18 */
 136         { 19, 0x58, 32 },               /* R19 */
 137         { 20, 0x5C, 32 },               /* R20 */
 138         { 21, 0x60, 32 },               /* R21 */
 139         { 22, 0x64, 32 },               /* R22 */
 140         { 23, 0x68, 32 },               /* R23 */
 141         { 24, 0x6C, 32 },               /* R24 */
 142         { 25, 0x70, 32 },               /* R25 */
 143         { 26, 0x74, 32 },               /* R26 */
 144         { 27, 0x78, 32 },               /* R27 */
 145         { 28, 0x7C, 32 },               /* R28 */
 146         { 29, 0x80, 32 },               /* R29 */
 147         { 30, 0x84, 32 },               /* R30 (LP) */
 148         { 31, 0x00, 32 },               /* R31 (SP) */
 149         { 32, 0x04, 32 },               /* PSW */
 150         { 33, 0x08, 32 },               /* IPC */
 151         { 34, 0x0C, 32 },               /* IPSW */
 152         { 35, 0x10, 32 },               /* IFC_LP */
 153 };
 154
 155 static int64_t rtos_generic_stack_align(struct target *target,
 156         const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
 157         int64_t stack_ptr, int align)
 158 {
 159         int64_t new_stack_ptr;
 160         int64_t aligned_stack_ptr;
 161         new_stack_ptr = stack_ptr - stacking->stack_growth_direction *
 162                 stacking->stack_registers_size;
 163         aligned_stack_ptr = new_stack_ptr & ~((int64_t)align - 1);
 164         if (aligned_stack_ptr != new_stack_ptr &&
 165                 stacking->stack_growth_direction == -1) {
 166                 /* If we have a downward growing stack, the simple alignment code
 167                  * above results in a wrong result (since it rounds down to nearest
 168                  * alignment).  We want to round up so add an extra align.
 169                  */
 170                 aligned_stack_ptr += (int64_t)align;
 171         }
 172         return aligned_stack_ptr;
 173 }
 174
 175 int64_t rtos_generic_stack_align8(struct target *target,
 176         const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
 177         int64_t stack_ptr)
 178 {
 179         return rtos_generic_stack_align(target, stack_data,
 180                         stacking, stack_ptr, 8);
 181 }
 182
 183 /* The Cortex-M3 will indicate that an alignment adjustment
 184  * has been done on the stack by setting bit 9 of the stacked xPSR
 185  * register.  In this case, we can just add an extra 4 bytes to get
 186  * to the program stack.  Note that some places in the ARM documentation
 187  * make this a little unclear but the padding takes place before the
 188  * normal exception stacking - so xPSR is always available at a fixed
 189  * location.
 190  *
 191  * Relevant documentation:
 192  *    Cortex-M series processors -> Cortex-M3 -> Revision: xxx ->
 193  *        Cortex-M3 Devices Generic User Guide -> The Cortex-M3 Processor ->
 194  *        Exception Model -> Exception entry and return -> Exception entry
 195  *    Cortex-M series processors -> Cortex-M3 -> Revision: xxx ->
 196  *        Cortex-M3 Devices Generic User Guide -> Cortex-M3 Peripherals ->
 197  *        System control block -> Configuration and Control Register (STKALIGN)
 198  *
 199  * This is just a helper function for use in the calculate_process_stack
 200  * function for a given architecture/rtos.
 201  */
 202 int64_t rtos_cortex_m_stack_align(struct target *target,
 203         const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
 204         int64_t stack_ptr, size_t xpsr_offset)
 205 {
 206         const uint32_t ALIGN_NEEDED = (1 << 9);
 207         uint32_t xpsr;
 208         int64_t new_stack_ptr;
 209
 210         new_stack_ptr = stack_ptr - stacking->stack_growth_direction *
 211                 stacking->stack_registers_size;
 212         xpsr = (target->endianness == TARGET_LITTLE_ENDIAN) ?
 213                         le_to_h_u32(&stack_data[xpsr_offset]) :
 214                         be_to_h_u32(&stack_data[xpsr_offset]);
 215         if ((xpsr & ALIGN_NEEDED) != 0) {
 216                 LOG_DEBUG("XPSR(0x%08" PRIx32 ") indicated stack alignment was necessary\r\n",
 217                         xpsr);
 218                 new_stack_ptr -= (stacking->stack_growth_direction * 4);
 219         }
 220         return new_stack_ptr;
 221 }
 222
 223 static int64_t rtos_standard_cortex_m3_stack_align(struct target *target,
 224         const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
 225         int64_t stack_ptr)
 226 {
 227         const int XPSR_OFFSET = 0x3c;
 228         return rtos_cortex_m_stack_align(target, stack_data, stacking,
 229                 stack_ptr, XPSR_OFFSET);
 230 }
 231
 232 static int64_t rtos_standard_cortex_m4f_stack_align(struct target *target,
 233         const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
 234         int64_t stack_ptr)
 235 {
 236         const int XPSR_OFFSET = 0x40;
 237         return rtos_cortex_m_stack_align(target, stack_data, stacking,
 238                 stack_ptr, XPSR_OFFSET);
 239 }
 240
 241 static int64_t rtos_standard_cortex_m4f_fpu_stack_align(struct target *target,
 242         const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
 243         int64_t stack_ptr)
 244 {
 245         const int XPSR_OFFSET = 0x80;
 246         return rtos_cortex_m_stack_align(target, stack_data, stacking,
 247                 stack_ptr, XPSR_OFFSET);
 248 }
 249
 250
 251 const struct rtos_register_stacking rtos_standard_cortex_m3_stacking = {
 252         0x40,                                   /* stack_registers_size */
 253         -1,                                             /* stack_growth_direction */
 254         ARMV7M_NUM_CORE_REGS,   /* num_output_registers */
 255         rtos_standard_cortex_m3_stack_align,    /* stack_alignment */
 256         rtos_standard_cortex_m3_stack_offsets   /* register_offsets */
 257 };
 258
 259 const struct rtos_register_stacking rtos_standard_cortex_m4f_stacking = {
 260         0x44,                                   /* stack_registers_size 4 more for LR*/
 261         -1,                                             /* stack_growth_direction */
 262         ARMV7M_NUM_CORE_REGS,   /* num_output_registers */
 263         rtos_standard_cortex_m4f_stack_align,   /* stack_alignment */
 264         rtos_standard_cortex_m4f_stack_offsets  /* register_offsets */
 265 };
 266
 267 const struct rtos_register_stacking rtos_standard_cortex_m4f_fpu_stacking = {
 268         0xcc,                                   /* stack_registers_size 4 more for LR + 48 more for FPU S0-S15 register*/
 269         -1,                                             /* stack_growth_direction */
 270         ARMV7M_NUM_CORE_REGS,   /* num_output_registers */
 271         rtos_standard_cortex_m4f_fpu_stack_align,       /* stack_alignment */
 272         rtos_standard_cortex_m4f_fpu_stack_offsets      /* register_offsets */
 273 };
 274
 275 const struct rtos_register_stacking rtos_standard_cortex_r4_stacking = {
 276         0x48,                           /* stack_registers_size */
 277         -1,                                     /* stack_growth_direction */
 278         26,                                     /* num_output_registers */
 279         rtos_generic_stack_align8,      /* stack_alignment */
 280         rtos_standard_cortex_r4_stack_offsets   /* register_offsets */
 281 };
 282
 283 const struct rtos_register_stacking rtos_standard_nds32_n1068_stacking = {
 284         0x90,                           /* stack_registers_size */
 285         -1,                                     /* stack_growth_direction */
 286         32,                                     /* num_output_registers */
 287         rtos_generic_stack_align8,      /* stack_alignment */
 288         rtos_standard_nds32_n1068_stack_offsets /* register_offsets */
 289 };