src/target/adi_v5_swd.c

   1 /***************************************************************************
   2  *
   3  *   Copyright (C) 2010 by David Brownell
   4  *
   5  *   This program is free software; you can redistribute it and/or modify
   6  *   it under the terms of the GNU General Public License as published by
   7  *   the Free Software Foundation; either version 2 of the License, or
   8  *   (at your option) any later version.
   9  *
  10  *   This program is distributed in the hope that it will be useful,
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *   GNU General Public License for more details.
  14  *
  15  *   You should have received a copy of the GNU General Public License
  16  *   along with this program; if not, write to the
  17  *   Free Software Foundation, Inc.,
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  19  ***************************************************************************/
  20
  21 /**
  22  * @file
  23  * Utilities to support ARM "Serial Wire Debug" (SWD), a low pin-count debug
  24  * link protocol used in cases where JTAG is not wanted.  This is coupled to
  25  * recent versions of ARM's "CoreSight" debug framework.  This specific code
  26  * is a transport level interface, with "target/arm_adi_v5.[hc]" code
  27  * understanding operation semantics, shared with the JTAG transport.
  28  *
  29  * Single-DAP support only.
  30  *
  31  * for details, see "ARM IHI 0031A"
  32  * ARM Debug Interface v5 Architecture Specification
  33  * especially section 5.3 for SWD protocol
  34  *
  35  * On many chips (most current Cortex-M3 parts) SWD is a run-time alternative
  36  * to JTAG.  Boards may support one or both.  There are also SWD-only chips,
  37  * (using SW-DP not SWJ-DP).
  38  *
  39  * Even boards that also support JTAG can benefit from SWD support, because
  40  * usually there's no way to access the SWO trace view mechanism in JTAG mode.
  41  * That is, trace access may require SWD support.
  42  *
  43  */
  44
  45 #ifdef HAVE_CONFIG_H
  46 #include "config.h"
  47 #endif
  48
  49 #include "arm.h"
  50 #include "arm_adi_v5.h"
  51 #include <helper/time_support.h>
  52
  53 #include <transport/transport.h>
  54 #include <jtag/interface.h>
  55
  56 #include <jtag/swd.h>
  57
  58 /* YUK! - but this is currently a global.... */
  59 extern struct jtag_interface *jtag_interface;
  60
  61 static int swd_finish_read(struct adiv5_dap *dap)
  62 {
  63         const struct swd_driver *swd = jtag_interface->swd;
  64         int retval = ERROR_OK;
  65         if (dap->last_read != NULL) {
  66                 retval = swd->read_reg(swd_cmd(true, false, DP_RDBUFF), dap->last_read);
  67                 dap->last_read = NULL;
  68         }
  69         return retval;
  70 }
  71
  72 static int (swd_queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
  73                 uint32_t data);
  74
  75 static int swd_clear_sticky_errors(struct adiv5_dap *dap)
  76 {
  77         const struct swd_driver *swd = jtag_interface->swd;
  78         assert(swd);
  79
  80         return swd->write_reg(swd_cmd(false,  false, DP_ABORT),
  81                 STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR);
  82 }
  83
  84 static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
  85 {
  86         const struct swd_driver *swd = jtag_interface->swd;
  87         assert(swd);
  88
  89         return swd->write_reg(swd_cmd(false,  false, DP_ABORT),
  90                 DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR);
  91 }
  92
  93 /** Select the DP register bank matching bits 7:4 of reg. */
  94 static int swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
  95 {
  96         uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
  97
  98         if (reg == DP_SELECT)
  99                 return ERROR_OK;
 100
 101         if (select_dp_bank == dap->dp_bank_value)
 102                 return ERROR_OK;
 103
 104         dap->dp_bank_value = select_dp_bank;
 105         select_dp_bank |= dap->ap_current | dap->ap_bank_value;
 106
 107         return swd_queue_dp_write(dap, DP_SELECT, select_dp_bank);
 108 }
 109
 110 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
 111                 uint32_t *data)
 112 {
 113         int retval;
 114         /* REVISIT status return vs ack ... */
 115         const struct swd_driver *swd = jtag_interface->swd;
 116         assert(swd);
 117
 118         retval = swd_queue_dp_bankselect(dap, reg);
 119         if (retval != ERROR_OK)
 120                 return retval;
 121
 122         retval = swd->read_reg(swd_cmd(true,  false, reg), data);
 123
 124         if (retval != ERROR_OK) {
 125                 /* fault response */
 126                 swd_clear_sticky_errors(dap);
 127         }
 128
 129         return retval;
 130 }
 131
 132
 133 static int (swd_queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
 134                 uint32_t data)
 135 {
 136         int retval;
 137         /* REVISIT status return vs ack ... */
 138         const struct swd_driver *swd = jtag_interface->swd;
 139         assert(swd);
 140
 141         retval = swd_finish_read(dap);
 142         if (retval != ERROR_OK)
 143                 return retval;
 144
 145         retval = swd_queue_dp_bankselect(dap, reg);
 146         if (retval != ERROR_OK)
 147                 return retval;
 148
 149         retval = swd->write_reg(swd_cmd(false,  false, reg), data);
 150
 151         if (retval != ERROR_OK) {
 152                 /* fault response */
 153                 swd_clear_sticky_errors(dap);
 154         }
 155
 156         return retval;
 157 }
 158
 159 /** Select the AP register bank matching bits 7:4 of reg. */
 160 static int swd_queue_ap_bankselect(struct adiv5_dap *dap, unsigned reg)
 161 {
 162         uint32_t select_ap_bank = reg & 0x000000F0;
 163
 164         if (select_ap_bank == dap->ap_bank_value)
 165                 return ERROR_OK;
 166
 167         dap->ap_bank_value = select_ap_bank;
 168         select_ap_bank |= dap->ap_current | dap->dp_bank_value;
 169
 170         return swd_queue_dp_write(dap, DP_SELECT, select_ap_bank);
 171 }
 172
 173 static int (swd_queue_ap_read)(struct adiv5_dap *dap, unsigned reg,
 174                 uint32_t *data)
 175 {
 176         /* REVISIT status return ... */
 177         const struct swd_driver *swd = jtag_interface->swd;
 178         assert(swd);
 179
 180         int retval = swd_queue_ap_bankselect(dap, reg);
 181         if (retval != ERROR_OK)
 182                 return retval;
 183
 184         retval = swd->read_reg(swd_cmd(true,  true, reg), dap->last_read);
 185         dap->last_read = data;
 186
 187         if (retval != ERROR_OK) {
 188                 /* fault response */
 189                 swd_clear_sticky_errors(dap);
 190                 return retval;
 191         }
 192
 193         return retval;
 194 }
 195
 196 static int (swd_queue_ap_write)(struct adiv5_dap *dap, unsigned reg,
 197                 uint32_t data)
 198 {
 199         /* REVISIT status return ... */
 200         const struct swd_driver *swd = jtag_interface->swd;
 201         assert(swd);
 202         int retval;
 203
 204         retval = swd_finish_read(dap);
 205         if (retval != ERROR_OK)
 206                 return retval;
 207
 208         retval = swd_queue_ap_bankselect(dap, reg);
 209         if (retval != ERROR_OK)
 210                 return retval;
 211
 212         retval = swd->write_reg(swd_cmd(false,  true, reg), data);
 213
 214         if (retval != ERROR_OK) {
 215                 /* fault response */
 216                 swd_clear_sticky_errors(dap);
 217         }
 218
 219         return retval;
 220 }
 221
 222 /** Executes all queued DAP operations. */
 223 static int swd_run(struct adiv5_dap *dap)
 224 {
 225         /* for now the SWD interface hard-wires a zero-size queue.  */
 226
 227         int retval = swd_finish_read(dap);
 228
 229         /* FIXME but we still need to check and scrub
 230          * any hardware errors ...
 231          */
 232         return retval;
 233 }
 234
 235 const struct dap_ops swd_dap_ops = {
 236         .is_swd = true,
 237
 238         .queue_dp_read = swd_queue_dp_read,
 239         .queue_dp_write = swd_queue_dp_write,
 240         .queue_ap_read = swd_queue_ap_read,
 241         .queue_ap_write = swd_queue_ap_write,
 242         .queue_ap_abort = swd_queue_ap_abort,
 243         .run = swd_run,
 244 };
 245
 246 /*
 247  * This represents the bits which must be sent out on TMS/SWDIO to
 248  * switch a DAP implemented using an SWJ-DP module into SWD mode.
 249  * These bits are stored (and transmitted) LSB-first.
 250  *
 251  * See the DAP-Lite specification, section 2.2.5 for information
 252  * about making the debug link select SWD or JTAG.  (Similar info
 253  * is in a few other ARM documents.)
 254  */
 255 static const uint8_t jtag2swd_bitseq[] = {
 256         /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
 257          * putting both JTAG and SWD logic into reset state.
 258          */
 259         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 260         /* Switching sequence enables SWD and disables JTAG
 261          * NOTE: bits in the DP's IDCODE may expose the need for
 262          * an old/obsolete/deprecated sequence (0xb6 0xed).
 263          */
 264         0x9e, 0xe7,
 265         /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
 266          * putting both JTAG and SWD logic into reset state.
 267          */
 268         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 269 };
 270
 271 /**
 272  * Put the debug link into SWD mode, if the target supports it.
 273  * The link's initial mode may be either JTAG (for example,
 274  * with SWJ-DP after reset) or SWD.
 275  *
 276  * @param target Enters SWD mode (if possible).
 277  *
 278  * Note that targets using the JTAG-DP do not support SWD, and that
 279  * some targets which could otherwise support it may have have been
 280  * configured to disable SWD signaling
 281  *
 282  * @return ERROR_OK or else a fault code.
 283  */
 284 int dap_to_swd(struct target *target)
 285 {
 286         struct arm *arm = target_to_arm(target);
 287         int retval;
 288
 289         LOG_DEBUG("Enter SWD mode");
 290
 291         /* REVISIT it's ugly to need to make calls to a "jtag"
 292          * subsystem if the link may not be in JTAG mode...
 293          */
 294
 295         retval =  jtag_add_tms_seq(8 * sizeof(jtag2swd_bitseq),
 296                         jtag2swd_bitseq, TAP_INVALID);
 297         if (retval == ERROR_OK)
 298                 retval = jtag_execute_queue();
 299
 300         /* set up the DAP's ops vector for SWD mode. */
 301         arm->dap->ops = &swd_dap_ops;
 302
 303         return retval;
 304 }
 305
 306 COMMAND_HANDLER(handle_swd_wcr)
 307 {
 308         int retval;
 309         struct target *target = get_current_target(CMD_CTX);
 310         struct arm *arm = target_to_arm(target);
 311         struct adiv5_dap *dap = arm->dap;
 312         uint32_t wcr;
 313         unsigned trn, scale = 0;
 314
 315         switch (CMD_ARGC) {
 316         /* no-args: just dump state */
 317         case 0:
 318                 /*retval = swd_queue_dp_read(dap, DP_WCR, &wcr); */
 319                 retval = dap_queue_dp_read(dap, DP_WCR, &wcr);
 320                 if (retval == ERROR_OK)
 321                         dap->ops->run(dap);
 322                 if (retval != ERROR_OK) {
 323                         LOG_ERROR("can't read WCR?");
 324                         return retval;
 325                 }
 326
 327                 command_print(CMD_CTX,
 328                         "turnaround=%" PRIu32 ", prescale=%" PRIu32,
 329                         WCR_TO_TRN(wcr),
 330                         WCR_TO_PRESCALE(wcr));
 331         return ERROR_OK;
 332
 333         case 2:         /* TRN and prescale */
 334                 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], scale);
 335                 if (scale > 7) {
 336                         LOG_ERROR("prescale %d is too big", scale);
 337                         return ERROR_FAIL;
 338                 }
 339                 /* FALL THROUGH */
 340
 341         case 1:         /* TRN only */
 342                 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], trn);
 343                 if (trn < 1 || trn > 4) {
 344                         LOG_ERROR("turnaround %d is invalid", trn);
 345                         return ERROR_FAIL;
 346                 }
 347
 348                 wcr = ((trn - 1) << 8) | scale;
 349                 /* FIXME
 350                  * write WCR ...
 351                  * then, re-init adapter with new TRN
 352                  */
 353                 LOG_ERROR("can't yet modify WCR");
 354                 return ERROR_FAIL;
 355
 356         default:        /* too many arguments */
 357                 return ERROR_COMMAND_SYNTAX_ERROR;
 358         }
 359 }
 360
 361 static const struct command_registration swd_commands[] = {
 362         {
 363                 /*
 364                  * Set up SWD and JTAG targets identically, unless/until
 365                  * infrastructure improves ...  meanwhile, ignore all
 366                  * JTAG-specific stuff like IR length for SWD.
 367                  *
 368                  * REVISIT can we verify "just one SWD DAP" here/early?
 369                  */
 370                 .name = "newdap",
 371                 .jim_handler = jim_jtag_newtap,
 372                 .mode = COMMAND_CONFIG,
 373                 .help = "declare a new SWD DAP"
 374         },
 375         {
 376                 .name = "wcr",
 377                 .handler = handle_swd_wcr,
 378                 .mode = COMMAND_ANY,
 379                 .help = "display or update DAP's WCR register",
 380                 .usage = "turnaround (1..4), prescale (0..7)",
 381         },
 382
 383         /* REVISIT -- add a command for SWV trace on/off */
 384         COMMAND_REGISTRATION_DONE
 385 };
 386
 387 static const struct command_registration swd_handlers[] = {
 388         {
 389                 .name = "swd",
 390                 .mode = COMMAND_ANY,
 391                 .help = "SWD command group",
 392                 .chain = swd_commands,
 393         },
 394         COMMAND_REGISTRATION_DONE
 395 };
 396
 397 static int swd_select(struct command_context *ctx)
 398 {
 399         int retval;
 400
 401         retval = register_commands(ctx, NULL, swd_handlers);
 402
 403         if (retval != ERROR_OK)
 404                 return retval;
 405
 406         const struct swd_driver *swd = jtag_interface->swd;
 407
 408          /* be sure driver is in SWD mode; start
 409           * with hardware default TRN (1), it can be changed later
 410           */
 411         if (!swd || !swd->read_reg || !swd->write_reg || !swd->init) {
 412                 LOG_DEBUG("no SWD driver?");
 413                 return ERROR_FAIL;
 414         }
 415
 416         retval = swd->init(1);
 417         if (retval != ERROR_OK) {
 418                 LOG_DEBUG("can't init SWD driver");
 419                 return retval;
 420         }
 421
 422         /* force DAP into SWD mode (not JTAG) */
 423         /*retval = dap_to_swd(target);*/
 424
 425         if (ctx->current_target) {
 426                 /* force DAP into SWD mode (not JTAG) */
 427                 struct target *target = get_current_target(ctx);
 428                 retval = dap_to_swd(target);
 429         }
 430
 431         return retval;
 432 }
 433
 434 static int swd_init(struct command_context *ctx)
 435 {
 436         struct target *target = get_current_target(ctx);
 437         struct arm *arm = target_to_arm(target);
 438         struct adiv5_dap *dap = arm->dap;
 439         uint32_t idcode;
 440         int status;
 441
 442         /* Force the DAP's ops vector for SWD mode.
 443          * messy - is there a better way? */
 444         arm->dap->ops = &swd_dap_ops;
 445
 446         /* FIXME validate transport config ... is the
 447          * configured DAP present (check IDCODE)?
 448          * Is *only* one DAP configured?
 449          *
 450          * MUST READ IDCODE
 451          */
 452
 453  /* Note, debugport_init() does setup too */
 454
 455         status = swd_queue_dp_read(dap, DP_IDCODE, &idcode);
 456
 457         if (status == ERROR_OK)
 458                 LOG_INFO("SWD IDCODE %#8.8" PRIx32, idcode);
 459
 460         /* force clear all sticky faults */
 461         swd_clear_sticky_errors(dap);
 462
 463         /* this is a workaround to get polling working */
 464         jtag_add_reset(0, 0);
 465
 466         return status;
 467 }
 468
 469 static struct transport swd_transport = {
 470         .name = "swd",
 471         .select = swd_select,
 472         .init = swd_init,
 473 };
 474
 475 static void swd_constructor(void) __attribute__((constructor));
 476 static void swd_constructor(void)
 477 {
 478         transport_register(&swd_transport);
 479 }
 480
 481 /** Returns true if the current debug session
 482  * is using SWD as its transport.
 483  */
 484 bool transport_is_swd(void)
 485 {
 486         return get_current_transport() == &swd_transport;
 487 }