src/target/adi_v5_swd.c

   1 /***************************************************************************
   2  *
   3  *   Copyright (C) 2010 by David Brownell
   4  *
   5  *   This program is free software; you can redistribute it and/or modify
   6  *   it under the terms of the GNU General Public License as published by
   7  *   the Free Software Foundation; either version 2 of the License, or
   8  *   (at your option) any later version.
   9  *
  10  *   This program is distributed in the hope that it will be useful,
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *   GNU General Public License for more details.
  14  *
  15  *   You should have received a copy of the GNU General Public License
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  ***************************************************************************/
  18
  19 /**
  20  * @file
  21  * Utilities to support ARM "Serial Wire Debug" (SWD), a low pin-count debug
  22  * link protocol used in cases where JTAG is not wanted.  This is coupled to
  23  * recent versions of ARM's "CoreSight" debug framework.  This specific code
  24  * is a transport level interface, with "target/arm_adi_v5.[hc]" code
  25  * understanding operation semantics, shared with the JTAG transport.
  26  *
  27  * Single-DAP support only.
  28  *
  29  * for details, see "ARM IHI 0031A"
  30  * ARM Debug Interface v5 Architecture Specification
  31  * especially section 5.3 for SWD protocol
  32  *
  33  * On many chips (most current Cortex-M3 parts) SWD is a run-time alternative
  34  * to JTAG.  Boards may support one or both.  There are also SWD-only chips,
  35  * (using SW-DP not SWJ-DP).
  36  *
  37  * Even boards that also support JTAG can benefit from SWD support, because
  38  * usually there's no way to access the SWO trace view mechanism in JTAG mode.
  39  * That is, trace access may require SWD support.
  40  *
  41  */
  42
  43 #ifdef HAVE_CONFIG_H
  44 #include "config.h"
  45 #endif
  46
  47 #include "arm.h"
  48 #include "arm_adi_v5.h"
  49 #include <helper/time_support.h>
  50
  51 #include <transport/transport.h>
  52 #include <jtag/interface.h>
  53
  54 #include <jtag/swd.h>
  55
  56 /* for debug, set do_sync to true to force synchronous transfers */
  57 static bool do_sync;
  58
  59 static void swd_finish_read(struct adiv5_dap *dap)
  60 {
  61         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
  62         if (dap->last_read) {
  63                 swd->read_reg(swd_cmd(true, false, DP_RDBUFF), dap->last_read, 0);
  64                 dap->last_read = NULL;
  65         }
  66 }
  67
  68 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
  69                 uint32_t data);
  70 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
  71                 uint32_t *data);
  72
  73 static void swd_clear_sticky_errors(struct adiv5_dap *dap)
  74 {
  75         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
  76         assert(swd);
  77
  78         swd->write_reg(swd_cmd(false, false, DP_ABORT),
  79                 STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
  80 }
  81
  82 static int swd_run_inner(struct adiv5_dap *dap)
  83 {
  84         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
  85         int retval;
  86
  87         retval = swd->run();
  88
  89         if (retval != ERROR_OK) {
  90                 /* fault response */
  91                 dap->do_reconnect = true;
  92         }
  93
  94         return retval;
  95 }
  96
  97 static int swd_connect(struct adiv5_dap *dap)
  98 {
  99         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 100         uint32_t dpidr = 0xdeadbeef;
 101         int status;
 102
 103         /* FIXME validate transport config ... is the
 104          * configured DAP present (check IDCODE)?
 105          * Is *only* one DAP configured?
 106          *
 107          * MUST READ DPIDR
 108          */
 109
 110         /* Check if we should reset srst already when connecting, but not if reconnecting. */
 111         if (!dap->do_reconnect) {
 112                 enum reset_types jtag_reset_config = jtag_get_reset_config();
 113
 114                 if (jtag_reset_config & RESET_CNCT_UNDER_SRST) {
 115                         if (jtag_reset_config & RESET_SRST_NO_GATING)
 116                                 adapter_assert_reset();
 117                         else
 118                                 LOG_WARNING("\'srst_nogate\' reset_config option is required");
 119                 }
 120         }
 121
 122
 123         int64_t timeout = timeval_ms() + 500;
 124
 125         do {
 126                 /* Note, debugport_init() does setup too */
 127                 swd->switch_seq(JTAG_TO_SWD);
 128
 129                 /* Clear link state, including the SELECT cache. */
 130                 dap->do_reconnect = false;
 131                 dap_invalidate_cache(dap);
 132
 133                 status = swd_queue_dp_read(dap, DP_DPIDR, &dpidr);
 134                 if (status == ERROR_OK) {
 135                         status = swd_run_inner(dap);
 136                         if (status == ERROR_OK)
 137                                 break;
 138                 }
 139
 140                 alive_sleep(1);
 141
 142         } while (timeval_ms() < timeout);
 143
 144         if (status != ERROR_OK) {
 145                 LOG_ERROR("Error connecting DP: cannot read IDR");
 146                 return status;
 147         }
 148
 149         LOG_INFO("SWD DPIDR %#8.8" PRIx32, dpidr);
 150
 151         do {
 152                 dap->do_reconnect = false;
 153
 154                 /* force clear all sticky faults */
 155                 swd_clear_sticky_errors(dap);
 156
 157                 status = swd_run_inner(dap);
 158                 if (status != ERROR_WAIT)
 159                         break;
 160
 161                 alive_sleep(10);
 162
 163         } while (timeval_ms() < timeout);
 164
 165         /* IHI 0031E B4.3.2:
 166          * "A WAIT response must not be issued to the ...
 167          * ... writes to the ABORT register"
 168          * swd_clear_sticky_errors() writes to the ABORT register only.
 169          *
 170          * Unfortunately at least Microchip SAMD51/E53/E54 returns WAIT
 171          * in a corner case. Just try if ABORT resolves the problem.
 172          */
 173         if (status == ERROR_WAIT) {
 174                 LOG_WARNING("Connecting DP: stalled AP operation, issuing ABORT");
 175
 176                 dap->do_reconnect = false;
 177
 178                 swd->write_reg(swd_cmd(false, false, DP_ABORT),
 179                         DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
 180                 status = swd_run_inner(dap);
 181         }
 182
 183         if (status == ERROR_OK)
 184                 status = dap_dp_init(dap);
 185
 186         return status;
 187 }
 188
 189 static int swd_send_sequence(struct adiv5_dap *dap, enum swd_special_seq seq)
 190 {
 191         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 192         assert(swd);
 193
 194         return swd->switch_seq(seq);
 195 }
 196
 197 static inline int check_sync(struct adiv5_dap *dap)
 198 {
 199         return do_sync ? swd_run_inner(dap) : ERROR_OK;
 200 }
 201
 202 static int swd_check_reconnect(struct adiv5_dap *dap)
 203 {
 204         if (dap->do_reconnect)
 205                 return swd_connect(dap);
 206
 207         return ERROR_OK;
 208 }
 209
 210 static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
 211 {
 212         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 213         assert(swd);
 214
 215         swd->write_reg(swd_cmd(false,  false, DP_ABORT),
 216                 DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
 217         return check_sync(dap);
 218 }
 219
 220 /** Select the DP register bank matching bits 7:4 of reg. */
 221 static int swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
 222 {
 223         /* Only register address 4 is banked. */
 224         if ((reg & 0xf) != 4)
 225                 return ERROR_OK;
 226
 227         uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
 228         uint32_t sel = select_dp_bank
 229                         | (dap->select & (DP_SELECT_APSEL | DP_SELECT_APBANK));
 230
 231         if (sel == dap->select)
 232                 return ERROR_OK;
 233
 234         dap->select = sel;
 235
 236         int retval = swd_queue_dp_write(dap, DP_SELECT, sel);
 237         if (retval != ERROR_OK)
 238                 dap->select = DP_SELECT_INVALID;
 239
 240         return retval;
 241 }
 242
 243 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
 244                 uint32_t *data)
 245 {
 246         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 247         assert(swd);
 248
 249         int retval = swd_check_reconnect(dap);
 250         if (retval != ERROR_OK)
 251                 return retval;
 252
 253         retval = swd_queue_dp_bankselect(dap, reg);
 254         if (retval != ERROR_OK)
 255                 return retval;
 256
 257         swd->read_reg(swd_cmd(true,  false, reg), data, 0);
 258
 259         return check_sync(dap);
 260 }
 261
 262 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
 263                 uint32_t data)
 264 {
 265         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 266         assert(swd);
 267
 268         int retval = swd_check_reconnect(dap);
 269         if (retval != ERROR_OK)
 270                 return retval;
 271
 272         swd_finish_read(dap);
 273         if (reg == DP_SELECT) {
 274                 dap->select = data & (DP_SELECT_APSEL | DP_SELECT_APBANK | DP_SELECT_DPBANK);
 275
 276                 swd->write_reg(swd_cmd(false,  false, reg), data, 0);
 277
 278                 retval = check_sync(dap);
 279                 if (retval != ERROR_OK)
 280                         dap->select = DP_SELECT_INVALID;
 281
 282                 return retval;
 283         }
 284
 285         retval = swd_queue_dp_bankselect(dap, reg);
 286         if (retval != ERROR_OK)
 287                 return retval;
 288
 289         swd->write_reg(swd_cmd(false,  false, reg), data, 0);
 290
 291         return check_sync(dap);
 292 }
 293
 294 /** Select the AP register bank matching bits 7:4 of reg. */
 295 static int swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
 296 {
 297         struct adiv5_dap *dap = ap->dap;
 298         uint32_t sel = ((uint32_t)ap->ap_num << 24)
 299                         | (reg & 0x000000F0)
 300                         | (dap->select & DP_SELECT_DPBANK);
 301
 302         if (sel == dap->select)
 303                 return ERROR_OK;
 304
 305         dap->select = sel;
 306
 307         int retval = swd_queue_dp_write(dap, DP_SELECT, sel);
 308         if (retval != ERROR_OK)
 309                 dap->select = DP_SELECT_INVALID;
 310
 311         return retval;
 312 }
 313
 314 static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
 315                 uint32_t *data)
 316 {
 317         struct adiv5_dap *dap = ap->dap;
 318         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 319         assert(swd);
 320
 321         int retval = swd_check_reconnect(dap);
 322         if (retval != ERROR_OK)
 323                 return retval;
 324
 325         retval = swd_queue_ap_bankselect(ap, reg);
 326         if (retval != ERROR_OK)
 327                 return retval;
 328
 329         swd->read_reg(swd_cmd(true, true, reg), dap->last_read, ap->memaccess_tck);
 330         dap->last_read = data;
 331
 332         return check_sync(dap);
 333 }
 334
 335 static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg,
 336                 uint32_t data)
 337 {
 338         struct adiv5_dap *dap = ap->dap;
 339         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 340         assert(swd);
 341
 342         int retval = swd_check_reconnect(dap);
 343         if (retval != ERROR_OK)
 344                 return retval;
 345
 346         swd_finish_read(dap);
 347         retval = swd_queue_ap_bankselect(ap, reg);
 348         if (retval != ERROR_OK)
 349                 return retval;
 350
 351         swd->write_reg(swd_cmd(false, true, reg), data, ap->memaccess_tck);
 352
 353         return check_sync(dap);
 354 }
 355
 356 /** Executes all queued DAP operations. */
 357 static int swd_run(struct adiv5_dap *dap)
 358 {
 359         swd_finish_read(dap);
 360         return swd_run_inner(dap);
 361 }
 362
 363 /** Put the SWJ-DP back to JTAG mode */
 364 static void swd_quit(struct adiv5_dap *dap)
 365 {
 366         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 367
 368         swd->switch_seq(SWD_TO_JTAG);
 369         /* flush the queue before exit */
 370         swd->run();
 371 }
 372
 373 const struct dap_ops swd_dap_ops = {
 374         .connect = swd_connect,
 375         .send_sequence = swd_send_sequence,
 376         .queue_dp_read = swd_queue_dp_read,
 377         .queue_dp_write = swd_queue_dp_write,
 378         .queue_ap_read = swd_queue_ap_read,
 379         .queue_ap_write = swd_queue_ap_write,
 380         .queue_ap_abort = swd_queue_ap_abort,
 381         .run = swd_run,
 382         .quit = swd_quit,
 383 };
 384
 385 static const struct command_registration swd_commands[] = {
 386         {
 387                 /*
 388                  * Set up SWD and JTAG targets identically, unless/until
 389                  * infrastructure improves ...  meanwhile, ignore all
 390                  * JTAG-specific stuff like IR length for SWD.
 391                  *
 392                  * REVISIT can we verify "just one SWD DAP" here/early?
 393                  */
 394                 .name = "newdap",
 395                 .jim_handler = jim_jtag_newtap,
 396                 .mode = COMMAND_CONFIG,
 397                 .help = "declare a new SWD DAP"
 398         },
 399         COMMAND_REGISTRATION_DONE
 400 };
 401
 402 static const struct command_registration swd_handlers[] = {
 403         {
 404                 .name = "swd",
 405                 .mode = COMMAND_ANY,
 406                 .help = "SWD command group",
 407                 .chain = swd_commands,
 408                 .usage = "",
 409         },
 410         COMMAND_REGISTRATION_DONE
 411 };
 412
 413 static int swd_select(struct command_context *ctx)
 414 {
 415         /* FIXME: only place where global 'adapter_driver' is still needed */
 416         extern struct adapter_driver *adapter_driver;
 417         const struct swd_driver *swd = adapter_driver->swd_ops;
 418         int retval;
 419
 420         retval = register_commands(ctx, NULL, swd_handlers);
 421         if (retval != ERROR_OK)
 422                 return retval;
 423
 424          /* be sure driver is in SWD mode; start
 425           * with hardware default TRN (1), it can be changed later
 426           */
 427         if (!swd || !swd->read_reg || !swd->write_reg || !swd->init) {
 428                 LOG_DEBUG("no SWD driver?");
 429                 return ERROR_FAIL;
 430         }
 431
 432         retval = swd->init();
 433         if (retval != ERROR_OK) {
 434                 LOG_DEBUG("can't init SWD driver");
 435                 return retval;
 436         }
 437
 438         return retval;
 439 }
 440
 441 static int swd_init(struct command_context *ctx)
 442 {
 443         /* nothing done here, SWD is initialized
 444          * together with the DAP */
 445         return ERROR_OK;
 446 }
 447
 448 static struct transport swd_transport = {
 449         .name = "swd",
 450         .select = swd_select,
 451         .init = swd_init,
 452 };
 453
 454 static void swd_constructor(void) __attribute__((constructor));
 455 static void swd_constructor(void)
 456 {
 457         transport_register(&swd_transport);
 458 }
 459
 460 /** Returns true if the current debug session
 461  * is using SWD as its transport.
 462  */
 463 bool transport_is_swd(void)
 464 {
 465         return get_current_transport() == &swd_transport;
 466 }