1 /***************************************************************************
3 * Copyright (C) 2010 by David Brownell
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the
17 * Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 ***************************************************************************/
23 * Utilities to support ARM "Serial Wire Debug" (SWD), a low pin-count debug
24 * link protocol used in cases where JTAG is not wanted. This is coupled to
25 * recent versions of ARM's "CoreSight" debug framework. This specific code
26 * is a transport level interface, with "target/arm_adi_v5.[hc]" code
27 * understanding operation semantics, shared with the JTAG transport.
29 * Single-DAP support only.
31 * for details, see "ARM IHI 0031A"
32 * ARM Debug Interface v5 Architecture Specification
33 * especially section 5.3 for SWD protocol
35 * On many chips (most current Cortex-M3 parts) SWD is a run-time alternative
36 * to JTAG. Boards may support one or both. There are also SWD-only chips,
37 * (using SW-DP not SWJ-DP).
39 * Even boards that also support JTAG can benefit from SWD support, because
40 * usually there's no way to access the SWO trace view mechanism in JTAG mode.
41 * That is, trace access may require SWD support.
50 #include "arm_adi_v5.h"
51 #include <helper/time_support.h>
53 #include <transport/transport.h>
54 #include <jtag/interface.h>
58 /* YUK! - but this is currently a global.... */
59 extern struct jtag_interface
*jtag_interface
;
62 static void swd_finish_read(struct adiv5_dap
*dap
)
64 const struct swd_driver
*swd
= jtag_interface
->swd
;
65 if (dap
->last_read
!= NULL
) {
66 swd
->read_reg(dap
, swd_cmd(true, false, DP_RDBUFF
), dap
->last_read
);
67 dap
->last_read
= NULL
;
71 static int swd_queue_dp_write(struct adiv5_dap
*dap
, unsigned reg
,
74 static void swd_clear_sticky_errors(struct adiv5_dap
*dap
)
76 const struct swd_driver
*swd
= jtag_interface
->swd
;
79 swd
->write_reg(dap
, swd_cmd(false, false, DP_ABORT
),
80 STKCMPCLR
| STKERRCLR
| WDERRCLR
| ORUNERRCLR
);
83 static int swd_run_inner(struct adiv5_dap
*dap
)
85 const struct swd_driver
*swd
= jtag_interface
->swd
;
87 int retval
= swd
->run(dap
);
89 if (retval
!= ERROR_OK
) {
91 swd_clear_sticky_errors(dap
);
97 static inline int check_sync(struct adiv5_dap
*dap
)
99 return do_sync
? swd_run_inner(dap
) : ERROR_OK
;
102 static int swd_queue_ap_abort(struct adiv5_dap
*dap
, uint8_t *ack
)
104 const struct swd_driver
*swd
= jtag_interface
->swd
;
107 swd
->write_reg(dap
, swd_cmd(false, false, DP_ABORT
),
108 DAPABORT
| STKCMPCLR
| STKERRCLR
| WDERRCLR
| ORUNERRCLR
);
109 return check_sync(dap
);
112 /** Select the DP register bank matching bits 7:4 of reg. */
113 static void swd_queue_dp_bankselect(struct adiv5_dap
*dap
, unsigned reg
)
115 uint32_t select_dp_bank
= (reg
& 0x000000F0) >> 4;
117 if (reg
== DP_SELECT
)
120 if (select_dp_bank
== dap
->dp_bank_value
)
123 dap
->dp_bank_value
= select_dp_bank
;
124 select_dp_bank
|= dap
->ap_current
| dap
->ap_bank_value
;
126 swd_queue_dp_write(dap
, DP_SELECT
, select_dp_bank
);
129 static int swd_queue_dp_read(struct adiv5_dap
*dap
, unsigned reg
,
132 const struct swd_driver
*swd
= jtag_interface
->swd
;
135 swd_queue_dp_bankselect(dap
, reg
);
136 swd
->read_reg(dap
, swd_cmd(true, false, reg
), data
);
138 return check_sync(dap
);
142 static int swd_queue_dp_write(struct adiv5_dap
*dap
, unsigned reg
,
145 const struct swd_driver
*swd
= jtag_interface
->swd
;
148 swd_finish_read(dap
);
149 swd_queue_dp_bankselect(dap
, reg
);
150 swd
->write_reg(dap
, swd_cmd(false, false, reg
), data
);
152 return check_sync(dap
);
155 /** Select the AP register bank matching bits 7:4 of reg. */
156 static void swd_queue_ap_bankselect(struct adiv5_dap
*dap
, unsigned reg
)
158 uint32_t select_ap_bank
= reg
& 0x000000F0;
160 if (select_ap_bank
== dap
->ap_bank_value
)
163 dap
->ap_bank_value
= select_ap_bank
;
164 select_ap_bank
|= dap
->ap_current
| dap
->dp_bank_value
;
166 swd_queue_dp_write(dap
, DP_SELECT
, select_ap_bank
);
169 static int swd_queue_ap_read(struct adiv5_dap
*dap
, unsigned reg
,
172 const struct swd_driver
*swd
= jtag_interface
->swd
;
175 swd_queue_ap_bankselect(dap
, reg
);
176 swd
->read_reg(dap
, swd_cmd(true, true, reg
), dap
->last_read
);
177 dap
->last_read
= data
;
179 return check_sync(dap
);
182 static int swd_queue_ap_write(struct adiv5_dap
*dap
, unsigned reg
,
185 const struct swd_driver
*swd
= jtag_interface
->swd
;
188 swd_finish_read(dap
);
189 swd_queue_ap_bankselect(dap
, reg
);
190 swd
->write_reg(dap
, swd_cmd(false, true, reg
), data
);
192 return check_sync(dap
);
195 /** Executes all queued DAP operations. */
196 static int swd_run(struct adiv5_dap
*dap
)
198 swd_finish_read(dap
);
199 return swd_run_inner(dap
);
202 const struct dap_ops swd_dap_ops
= {
205 .queue_dp_read
= swd_queue_dp_read
,
206 .queue_dp_write
= swd_queue_dp_write
,
207 .queue_ap_read
= swd_queue_ap_read
,
208 .queue_ap_write
= swd_queue_ap_write
,
209 .queue_ap_abort
= swd_queue_ap_abort
,
214 * This represents the bits which must be sent out on TMS/SWDIO to
215 * switch a DAP implemented using an SWJ-DP module into SWD mode.
216 * These bits are stored (and transmitted) LSB-first.
218 * See the DAP-Lite specification, section 2.2.5 for information
219 * about making the debug link select SWD or JTAG. (Similar info
220 * is in a few other ARM documents.)
222 static const uint8_t jtag2swd_bitseq
[] = {
223 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
224 * putting both JTAG and SWD logic into reset state.
226 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
227 /* Switching sequence enables SWD and disables JTAG
228 * NOTE: bits in the DP's IDCODE may expose the need for
229 * an old/obsolete/deprecated sequence (0xb6 0xed).
232 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
233 * putting both JTAG and SWD logic into reset state.
235 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
239 * Put the debug link into SWD mode, if the target supports it.
240 * The link's initial mode may be either JTAG (for example,
241 * with SWJ-DP after reset) or SWD.
243 * @param target Enters SWD mode (if possible).
245 * Note that targets using the JTAG-DP do not support SWD, and that
246 * some targets which could otherwise support it may have have been
247 * configured to disable SWD signaling
249 * @return ERROR_OK or else a fault code.
251 int dap_to_swd(struct target
*target
)
253 struct arm
*arm
= target_to_arm(target
);
257 LOG_ERROR("SWD mode is not available");
261 LOG_DEBUG("Enter SWD mode");
263 /* REVISIT it's ugly to need to make calls to a "jtag"
264 * subsystem if the link may not be in JTAG mode...
267 retval
= jtag_add_tms_seq(8 * sizeof(jtag2swd_bitseq
),
268 jtag2swd_bitseq
, TAP_INVALID
);
269 if (retval
== ERROR_OK
)
270 retval
= jtag_execute_queue();
272 /* set up the DAP's ops vector for SWD mode. */
273 arm
->dap
->ops
= &swd_dap_ops
;
278 COMMAND_HANDLER(handle_swd_wcr
)
281 struct target
*target
= get_current_target(CMD_CTX
);
282 struct arm
*arm
= target_to_arm(target
);
283 struct adiv5_dap
*dap
= arm
->dap
;
285 unsigned trn
, scale
= 0;
288 /* no-args: just dump state */
290 /*retval = swd_queue_dp_read(dap, DP_WCR, &wcr); */
291 retval
= dap_queue_dp_read(dap
, DP_WCR
, &wcr
);
292 if (retval
== ERROR_OK
)
294 if (retval
!= ERROR_OK
) {
295 LOG_ERROR("can't read WCR?");
299 command_print(CMD_CTX
,
300 "turnaround=%" PRIu32
", prescale=%" PRIu32
,
302 WCR_TO_PRESCALE(wcr
));
305 case 2: /* TRN and prescale */
306 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[1], scale
);
308 LOG_ERROR("prescale %d is too big", scale
);
313 case 1: /* TRN only */
314 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[0], trn
);
315 if (trn
< 1 || trn
> 4) {
316 LOG_ERROR("turnaround %d is invalid", trn
);
320 wcr
= ((trn
- 1) << 8) | scale
;
323 * then, re-init adapter with new TRN
325 LOG_ERROR("can't yet modify WCR");
328 default: /* too many arguments */
329 return ERROR_COMMAND_SYNTAX_ERROR
;
333 static const struct command_registration swd_commands
[] = {
336 * Set up SWD and JTAG targets identically, unless/until
337 * infrastructure improves ... meanwhile, ignore all
338 * JTAG-specific stuff like IR length for SWD.
340 * REVISIT can we verify "just one SWD DAP" here/early?
343 .jim_handler
= jim_jtag_newtap
,
344 .mode
= COMMAND_CONFIG
,
345 .help
= "declare a new SWD DAP"
349 .handler
= handle_swd_wcr
,
351 .help
= "display or update DAP's WCR register",
352 .usage
= "turnaround (1..4), prescale (0..7)",
355 /* REVISIT -- add a command for SWV trace on/off */
356 COMMAND_REGISTRATION_DONE
359 static const struct command_registration swd_handlers
[] = {
363 .help
= "SWD command group",
364 .chain
= swd_commands
,
366 COMMAND_REGISTRATION_DONE
369 static int swd_select(struct command_context
*ctx
)
373 retval
= register_commands(ctx
, NULL
, swd_handlers
);
375 if (retval
!= ERROR_OK
)
378 const struct swd_driver
*swd
= jtag_interface
->swd
;
380 /* be sure driver is in SWD mode; start
381 * with hardware default TRN (1), it can be changed later
383 if (!swd
|| !swd
->read_reg
|| !swd
->write_reg
|| !swd
->init
) {
384 LOG_DEBUG("no SWD driver?");
388 retval
= swd
->init();
389 if (retval
!= ERROR_OK
) {
390 LOG_DEBUG("can't init SWD driver");
394 /* force DAP into SWD mode (not JTAG) */
395 /*retval = dap_to_swd(target);*/
397 if (ctx
->current_target
) {
398 /* force DAP into SWD mode (not JTAG) */
399 struct target
*target
= get_current_target(ctx
);
400 retval
= dap_to_swd(target
);
406 static int swd_init(struct command_context
*ctx
)
408 struct target
*target
= get_current_target(ctx
);
409 struct arm
*arm
= target_to_arm(target
);
410 struct adiv5_dap
*dap
= arm
->dap
;
414 /* Force the DAP's ops vector for SWD mode.
415 * messy - is there a better way? */
416 arm
->dap
->ops
= &swd_dap_ops
;
418 /* FIXME validate transport config ... is the
419 * configured DAP present (check IDCODE)?
420 * Is *only* one DAP configured?
425 /* Note, debugport_init() does setup too */
427 swd_queue_dp_read(dap
, DP_IDCODE
, &idcode
);
429 /* force clear all sticky faults */
430 swd_clear_sticky_errors(dap
);
432 status
= swd_run(dap
);
434 if (status
== ERROR_OK
)
435 LOG_INFO("SWD IDCODE %#8.8" PRIx32
, idcode
);
440 static struct transport swd_transport
= {
442 .select
= swd_select
,
446 static void swd_constructor(void) __attribute__((constructor
));
447 static void swd_constructor(void)
449 transport_register(&swd_transport
);
452 /** Returns true if the current debug session
453 * is using SWD as its transport.
455 bool transport_is_swd(void)
457 return get_current_transport() == &swd_transport
;
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