target/arm_adi_v5,arm_dap: introduce multidrop_targetsel and its configuration
[openocd.git] / src / target / adi_v5_swd.c
1 /***************************************************************************
2 *
3 * Copyright (C) 2010 by David Brownell
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 ***************************************************************************/
18
19 /**
20 * @file
21 * Utilities to support ARM "Serial Wire Debug" (SWD), a low pin-count debug
22 * link protocol used in cases where JTAG is not wanted. This is coupled to
23 * recent versions of ARM's "CoreSight" debug framework. This specific code
24 * is a transport level interface, with "target/arm_adi_v5.[hc]" code
25 * understanding operation semantics, shared with the JTAG transport.
26 *
27 * Single-DAP support only.
28 *
29 * for details, see "ARM IHI 0031A"
30 * ARM Debug Interface v5 Architecture Specification
31 * especially section 5.3 for SWD protocol
32 *
33 * On many chips (most current Cortex-M3 parts) SWD is a run-time alternative
34 * to JTAG. Boards may support one or both. There are also SWD-only chips,
35 * (using SW-DP not SWJ-DP).
36 *
37 * Even boards that also support JTAG can benefit from SWD support, because
38 * usually there's no way to access the SWO trace view mechanism in JTAG mode.
39 * That is, trace access may require SWD support.
40 *
41 */
42
43 #ifdef HAVE_CONFIG_H
44 #include "config.h"
45 #endif
46
47 #include "arm.h"
48 #include "arm_adi_v5.h"
49 #include <helper/time_support.h>
50
51 #include <transport/transport.h>
52 #include <jtag/interface.h>
53
54 #include <jtag/swd.h>
55
56 /* for debug, set do_sync to true to force synchronous transfers */
57 static bool do_sync;
58
59
60 static int swd_run(struct adiv5_dap *dap);
61 static int swd_queue_dp_write_inner(struct adiv5_dap *dap, unsigned int reg,
62 uint32_t data);
63
64
65 static int swd_send_sequence(struct adiv5_dap *dap, enum swd_special_seq seq)
66 {
67 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
68 assert(swd);
69
70 return swd->switch_seq(seq);
71 }
72
73 static void swd_finish_read(struct adiv5_dap *dap)
74 {
75 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
76 if (dap->last_read) {
77 swd->read_reg(swd_cmd(true, false, DP_RDBUFF), dap->last_read, 0);
78 dap->last_read = NULL;
79 }
80 }
81
82 static void swd_clear_sticky_errors(struct adiv5_dap *dap)
83 {
84 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
85 assert(swd);
86
87 swd->write_reg(swd_cmd(false, false, DP_ABORT),
88 STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
89 }
90
91 static int swd_run_inner(struct adiv5_dap *dap)
92 {
93 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
94 int retval;
95
96 retval = swd->run();
97
98 if (retval != ERROR_OK) {
99 /* fault response */
100 dap->do_reconnect = true;
101 }
102
103 return retval;
104 }
105
106 static inline int check_sync(struct adiv5_dap *dap)
107 {
108 return do_sync ? swd_run_inner(dap) : ERROR_OK;
109 }
110
111 /** Select the DP register bank matching bits 7:4 of reg. */
112 static int swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned int reg)
113 {
114 /* Only register address 4 is banked. */
115 if ((reg & 0xf) != 4)
116 return ERROR_OK;
117
118 uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
119 uint32_t sel = select_dp_bank
120 | (dap->select & (DP_SELECT_APSEL | DP_SELECT_APBANK));
121
122 if (sel == dap->select)
123 return ERROR_OK;
124
125 dap->select = sel;
126
127 int retval = swd_queue_dp_write_inner(dap, DP_SELECT, sel);
128 if (retval != ERROR_OK)
129 dap->select = DP_SELECT_INVALID;
130
131 return retval;
132 }
133
134 static int swd_queue_dp_read_inner(struct adiv5_dap *dap, unsigned int reg,
135 uint32_t *data)
136 {
137 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
138 assert(swd);
139
140 int retval = swd_queue_dp_bankselect(dap, reg);
141 if (retval != ERROR_OK)
142 return retval;
143
144 swd->read_reg(swd_cmd(true, false, reg), data, 0);
145
146 return check_sync(dap);
147 }
148
149 static int swd_queue_dp_write_inner(struct adiv5_dap *dap, unsigned int reg,
150 uint32_t data)
151 {
152 int retval;
153 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
154 assert(swd);
155
156 swd_finish_read(dap);
157
158 if (reg == DP_SELECT) {
159 dap->select = data & (DP_SELECT_APSEL | DP_SELECT_APBANK | DP_SELECT_DPBANK);
160
161 swd->write_reg(swd_cmd(false, false, reg), data, 0);
162
163 retval = check_sync(dap);
164 if (retval != ERROR_OK)
165 dap->select = DP_SELECT_INVALID;
166
167 return retval;
168 }
169
170 retval = swd_queue_dp_bankselect(dap, reg);
171 if (retval != ERROR_OK)
172 return retval;
173
174 swd->write_reg(swd_cmd(false, false, reg), data, 0);
175
176 return check_sync(dap);
177 }
178
179 static int swd_connect(struct adiv5_dap *dap)
180 {
181 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
182 uint32_t dpidr = 0xdeadbeef;
183 int status;
184
185 /* FIXME validate transport config ... is the
186 * configured DAP present (check IDCODE)?
187 * Is *only* one DAP configured?
188 *
189 * MUST READ DPIDR
190 */
191
192 /* Check if we should reset srst already when connecting, but not if reconnecting. */
193 if (!dap->do_reconnect) {
194 enum reset_types jtag_reset_config = jtag_get_reset_config();
195
196 if (jtag_reset_config & RESET_CNCT_UNDER_SRST) {
197 if (jtag_reset_config & RESET_SRST_NO_GATING)
198 adapter_assert_reset();
199 else
200 LOG_WARNING("\'srst_nogate\' reset_config option is required");
201 }
202 }
203
204
205 int64_t timeout = timeval_ms() + 500;
206
207 do {
208 /* Note, debugport_init() does setup too */
209 swd->switch_seq(JTAG_TO_SWD);
210
211 /* Clear link state, including the SELECT cache. */
212 dap->do_reconnect = false;
213 dap_invalidate_cache(dap);
214
215 status = swd_queue_dp_read_inner(dap, DP_DPIDR, &dpidr);
216 if (status == ERROR_OK) {
217 status = swd_run_inner(dap);
218 if (status == ERROR_OK)
219 break;
220 }
221
222 alive_sleep(1);
223
224 } while (timeval_ms() < timeout);
225
226 if (status != ERROR_OK) {
227 LOG_ERROR("Error connecting DP: cannot read IDR");
228 return status;
229 }
230
231 LOG_INFO("SWD DPIDR %#8.8" PRIx32, dpidr);
232
233 do {
234 dap->do_reconnect = false;
235
236 /* force clear all sticky faults */
237 swd_clear_sticky_errors(dap);
238
239 status = swd_run_inner(dap);
240 if (status != ERROR_WAIT)
241 break;
242
243 alive_sleep(10);
244
245 } while (timeval_ms() < timeout);
246
247 /* IHI 0031E B4.3.2:
248 * "A WAIT response must not be issued to the ...
249 * ... writes to the ABORT register"
250 * swd_clear_sticky_errors() writes to the ABORT register only.
251 *
252 * Unfortunately at least Microchip SAMD51/E53/E54 returns WAIT
253 * in a corner case. Just try if ABORT resolves the problem.
254 */
255 if (status == ERROR_WAIT) {
256 LOG_WARNING("Connecting DP: stalled AP operation, issuing ABORT");
257
258 dap->do_reconnect = false;
259
260 swd->write_reg(swd_cmd(false, false, DP_ABORT),
261 DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
262 status = swd_run_inner(dap);
263 }
264
265 if (status == ERROR_OK)
266 status = dap_dp_init(dap);
267
268 return status;
269 }
270
271 static int swd_check_reconnect(struct adiv5_dap *dap)
272 {
273 if (dap->do_reconnect)
274 return swd_connect(dap);
275
276 return ERROR_OK;
277 }
278
279 static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
280 {
281 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
282 assert(swd);
283
284 swd->write_reg(swd_cmd(false, false, DP_ABORT),
285 DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
286 return check_sync(dap);
287 }
288
289 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
290 uint32_t *data)
291 {
292 int retval = swd_check_reconnect(dap);
293 if (retval != ERROR_OK)
294 return retval;
295
296 return swd_queue_dp_read_inner(dap, reg, data);
297 }
298
299 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
300 uint32_t data)
301 {
302 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
303 assert(swd);
304
305 int retval = swd_check_reconnect(dap);
306 if (retval != ERROR_OK)
307 return retval;
308
309 return swd_queue_dp_write_inner(dap, reg, data);
310 }
311
312 /** Select the AP register bank matching bits 7:4 of reg. */
313 static int swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
314 {
315 struct adiv5_dap *dap = ap->dap;
316 uint32_t sel = ((uint32_t)ap->ap_num << 24)
317 | (reg & 0x000000F0)
318 | (dap->select & DP_SELECT_DPBANK);
319
320 if (sel == dap->select)
321 return ERROR_OK;
322
323 dap->select = sel;
324
325 int retval = swd_queue_dp_write_inner(dap, DP_SELECT, sel);
326 if (retval != ERROR_OK)
327 dap->select = DP_SELECT_INVALID;
328
329 return retval;
330 }
331
332 static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
333 uint32_t *data)
334 {
335 struct adiv5_dap *dap = ap->dap;
336 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
337 assert(swd);
338
339 int retval = swd_check_reconnect(dap);
340 if (retval != ERROR_OK)
341 return retval;
342
343 retval = swd_queue_ap_bankselect(ap, reg);
344 if (retval != ERROR_OK)
345 return retval;
346
347 swd->read_reg(swd_cmd(true, true, reg), dap->last_read, ap->memaccess_tck);
348 dap->last_read = data;
349
350 return check_sync(dap);
351 }
352
353 static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg,
354 uint32_t data)
355 {
356 struct adiv5_dap *dap = ap->dap;
357 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
358 assert(swd);
359
360 int retval = swd_check_reconnect(dap);
361 if (retval != ERROR_OK)
362 return retval;
363
364 swd_finish_read(dap);
365 retval = swd_queue_ap_bankselect(ap, reg);
366 if (retval != ERROR_OK)
367 return retval;
368
369 swd->write_reg(swd_cmd(false, true, reg), data, ap->memaccess_tck);
370
371 return check_sync(dap);
372 }
373
374 /** Executes all queued DAP operations. */
375 static int swd_run(struct adiv5_dap *dap)
376 {
377 swd_finish_read(dap);
378 return swd_run_inner(dap);
379 }
380
381 /** Put the SWJ-DP back to JTAG mode */
382 static void swd_quit(struct adiv5_dap *dap)
383 {
384 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
385
386 swd->switch_seq(SWD_TO_JTAG);
387 /* flush the queue before exit */
388 swd->run();
389 }
390
391 const struct dap_ops swd_dap_ops = {
392 .connect = swd_connect,
393 .send_sequence = swd_send_sequence,
394 .queue_dp_read = swd_queue_dp_read,
395 .queue_dp_write = swd_queue_dp_write,
396 .queue_ap_read = swd_queue_ap_read,
397 .queue_ap_write = swd_queue_ap_write,
398 .queue_ap_abort = swd_queue_ap_abort,
399 .run = swd_run,
400 .quit = swd_quit,
401 };
402
403 static const struct command_registration swd_commands[] = {
404 {
405 /*
406 * Set up SWD and JTAG targets identically, unless/until
407 * infrastructure improves ... meanwhile, ignore all
408 * JTAG-specific stuff like IR length for SWD.
409 *
410 * REVISIT can we verify "just one SWD DAP" here/early?
411 */
412 .name = "newdap",
413 .jim_handler = jim_jtag_newtap,
414 .mode = COMMAND_CONFIG,
415 .help = "declare a new SWD DAP"
416 },
417 COMMAND_REGISTRATION_DONE
418 };
419
420 static const struct command_registration swd_handlers[] = {
421 {
422 .name = "swd",
423 .mode = COMMAND_ANY,
424 .help = "SWD command group",
425 .chain = swd_commands,
426 .usage = "",
427 },
428 COMMAND_REGISTRATION_DONE
429 };
430
431 static int swd_select(struct command_context *ctx)
432 {
433 /* FIXME: only place where global 'adapter_driver' is still needed */
434 extern struct adapter_driver *adapter_driver;
435 const struct swd_driver *swd = adapter_driver->swd_ops;
436 int retval;
437
438 retval = register_commands(ctx, NULL, swd_handlers);
439 if (retval != ERROR_OK)
440 return retval;
441
442 /* be sure driver is in SWD mode; start
443 * with hardware default TRN (1), it can be changed later
444 */
445 if (!swd || !swd->read_reg || !swd->write_reg || !swd->init) {
446 LOG_DEBUG("no SWD driver?");
447 return ERROR_FAIL;
448 }
449
450 retval = swd->init();
451 if (retval != ERROR_OK) {
452 LOG_DEBUG("can't init SWD driver");
453 return retval;
454 }
455
456 return retval;
457 }
458
459 static int swd_init(struct command_context *ctx)
460 {
461 /* nothing done here, SWD is initialized
462 * together with the DAP */
463 return ERROR_OK;
464 }
465
466 static struct transport swd_transport = {
467 .name = "swd",
468 .select = swd_select,
469 .init = swd_init,
470 };
471
472 static void swd_constructor(void) __attribute__((constructor));
473 static void swd_constructor(void)
474 {
475 transport_register(&swd_transport);
476 }
477
478 /** Returns true if the current debug session
479 * is using SWD as its transport.
480 */
481 bool transport_is_swd(void)
482 {
483 return get_current_transport() == &swd_transport;
484 }

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)