1 /***************************************************************************
3 * Copyright (C) 2010 by David Brownell
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 ***************************************************************************/
21 * Utilities to support ARM "Serial Wire Debug" (SWD), a low pin-count debug
22 * link protocol used in cases where JTAG is not wanted. This is coupled to
23 * recent versions of ARM's "CoreSight" debug framework. This specific code
24 * is a transport level interface, with "target/arm_adi_v5.[hc]" code
25 * understanding operation semantics, shared with the JTAG transport.
27 * Single-DAP support only.
29 * for details, see "ARM IHI 0031A"
30 * ARM Debug Interface v5 Architecture Specification
31 * especially section 5.3 for SWD protocol
33 * On many chips (most current Cortex-M3 parts) SWD is a run-time alternative
34 * to JTAG. Boards may support one or both. There are also SWD-only chips,
35 * (using SW-DP not SWJ-DP).
37 * Even boards that also support JTAG can benefit from SWD support, because
38 * usually there's no way to access the SWO trace view mechanism in JTAG mode.
39 * That is, trace access may require SWD support.
48 #include "arm_adi_v5.h"
49 #include <helper/time_support.h>
51 #include <transport/transport.h>
52 #include <jtag/interface.h>
56 /* for debug, set do_sync to true to force synchronous transfers */
60 static int swd_run(struct adiv5_dap
*dap
);
61 static int swd_queue_dp_write_inner(struct adiv5_dap
*dap
, unsigned int reg
,
65 static int swd_send_sequence(struct adiv5_dap
*dap
, enum swd_special_seq seq
)
67 const struct swd_driver
*swd
= adiv5_dap_swd_driver(dap
);
70 return swd
->switch_seq(seq
);
73 static void swd_finish_read(struct adiv5_dap
*dap
)
75 const struct swd_driver
*swd
= adiv5_dap_swd_driver(dap
);
77 swd
->read_reg(swd_cmd(true, false, DP_RDBUFF
), dap
->last_read
, 0);
78 dap
->last_read
= NULL
;
82 static void swd_clear_sticky_errors(struct adiv5_dap
*dap
)
84 const struct swd_driver
*swd
= adiv5_dap_swd_driver(dap
);
87 swd
->write_reg(swd_cmd(false, false, DP_ABORT
),
88 STKCMPCLR
| STKERRCLR
| WDERRCLR
| ORUNERRCLR
, 0);
91 static int swd_run_inner(struct adiv5_dap
*dap
)
93 const struct swd_driver
*swd
= adiv5_dap_swd_driver(dap
);
98 if (retval
!= ERROR_OK
) {
100 dap
->do_reconnect
= true;
106 static inline int check_sync(struct adiv5_dap
*dap
)
108 return do_sync
? swd_run_inner(dap
) : ERROR_OK
;
111 /** Select the DP register bank matching bits 7:4 of reg. */
112 static int swd_queue_dp_bankselect(struct adiv5_dap
*dap
, unsigned int reg
)
114 /* Only register address 4 is banked. */
115 if ((reg
& 0xf) != 4)
118 uint32_t select_dp_bank
= (reg
& 0x000000F0) >> 4;
119 uint32_t sel
= select_dp_bank
120 | (dap
->select
& (DP_SELECT_APSEL
| DP_SELECT_APBANK
));
122 if (sel
== dap
->select
)
127 int retval
= swd_queue_dp_write_inner(dap
, DP_SELECT
, sel
);
128 if (retval
!= ERROR_OK
)
129 dap
->select
= DP_SELECT_INVALID
;
134 static int swd_queue_dp_read_inner(struct adiv5_dap
*dap
, unsigned int reg
,
137 const struct swd_driver
*swd
= adiv5_dap_swd_driver(dap
);
140 int retval
= swd_queue_dp_bankselect(dap
, reg
);
141 if (retval
!= ERROR_OK
)
144 swd
->read_reg(swd_cmd(true, false, reg
), data
, 0);
146 return check_sync(dap
);
149 static int swd_queue_dp_write_inner(struct adiv5_dap
*dap
, unsigned int reg
,
153 const struct swd_driver
*swd
= adiv5_dap_swd_driver(dap
);
156 swd_finish_read(dap
);
158 if (reg
== DP_SELECT
) {
159 dap
->select
= data
& (DP_SELECT_APSEL
| DP_SELECT_APBANK
| DP_SELECT_DPBANK
);
161 swd
->write_reg(swd_cmd(false, false, reg
), data
, 0);
163 retval
= check_sync(dap
);
164 if (retval
!= ERROR_OK
)
165 dap
->select
= DP_SELECT_INVALID
;
170 retval
= swd_queue_dp_bankselect(dap
, reg
);
171 if (retval
!= ERROR_OK
)
174 swd
->write_reg(swd_cmd(false, false, reg
), data
, 0);
176 return check_sync(dap
);
179 static int swd_connect(struct adiv5_dap
*dap
)
181 const struct swd_driver
*swd
= adiv5_dap_swd_driver(dap
);
182 uint32_t dpidr
= 0xdeadbeef;
185 /* FIXME validate transport config ... is the
186 * configured DAP present (check IDCODE)?
187 * Is *only* one DAP configured?
192 /* Check if we should reset srst already when connecting, but not if reconnecting. */
193 if (!dap
->do_reconnect
) {
194 enum reset_types jtag_reset_config
= jtag_get_reset_config();
196 if (jtag_reset_config
& RESET_CNCT_UNDER_SRST
) {
197 if (jtag_reset_config
& RESET_SRST_NO_GATING
)
198 adapter_assert_reset();
200 LOG_WARNING("\'srst_nogate\' reset_config option is required");
205 int64_t timeout
= timeval_ms() + 500;
208 /* Note, debugport_init() does setup too */
209 swd
->switch_seq(JTAG_TO_SWD
);
211 /* Clear link state, including the SELECT cache. */
212 dap
->do_reconnect
= false;
213 dap_invalidate_cache(dap
);
215 status
= swd_queue_dp_read_inner(dap
, DP_DPIDR
, &dpidr
);
216 if (status
== ERROR_OK
) {
217 status
= swd_run_inner(dap
);
218 if (status
== ERROR_OK
)
224 } while (timeval_ms() < timeout
);
226 if (status
!= ERROR_OK
) {
227 LOG_ERROR("Error connecting DP: cannot read IDR");
231 LOG_INFO("SWD DPIDR %#8.8" PRIx32
, dpidr
);
234 dap
->do_reconnect
= false;
236 /* force clear all sticky faults */
237 swd_clear_sticky_errors(dap
);
239 status
= swd_run_inner(dap
);
240 if (status
!= ERROR_WAIT
)
245 } while (timeval_ms() < timeout
);
248 * "A WAIT response must not be issued to the ...
249 * ... writes to the ABORT register"
250 * swd_clear_sticky_errors() writes to the ABORT register only.
252 * Unfortunately at least Microchip SAMD51/E53/E54 returns WAIT
253 * in a corner case. Just try if ABORT resolves the problem.
255 if (status
== ERROR_WAIT
) {
256 LOG_WARNING("Connecting DP: stalled AP operation, issuing ABORT");
258 dap
->do_reconnect
= false;
260 swd
->write_reg(swd_cmd(false, false, DP_ABORT
),
261 DAPABORT
| STKCMPCLR
| STKERRCLR
| WDERRCLR
| ORUNERRCLR
, 0);
262 status
= swd_run_inner(dap
);
265 if (status
== ERROR_OK
)
266 status
= dap_dp_init(dap
);
271 static int swd_check_reconnect(struct adiv5_dap
*dap
)
273 if (dap
->do_reconnect
)
274 return swd_connect(dap
);
279 static int swd_queue_ap_abort(struct adiv5_dap
*dap
, uint8_t *ack
)
281 const struct swd_driver
*swd
= adiv5_dap_swd_driver(dap
);
284 swd
->write_reg(swd_cmd(false, false, DP_ABORT
),
285 DAPABORT
| STKCMPCLR
| STKERRCLR
| WDERRCLR
| ORUNERRCLR
, 0);
286 return check_sync(dap
);
289 static int swd_queue_dp_read(struct adiv5_dap
*dap
, unsigned reg
,
292 int retval
= swd_check_reconnect(dap
);
293 if (retval
!= ERROR_OK
)
296 return swd_queue_dp_read_inner(dap
, reg
, data
);
299 static int swd_queue_dp_write(struct adiv5_dap
*dap
, unsigned reg
,
302 const struct swd_driver
*swd
= adiv5_dap_swd_driver(dap
);
305 int retval
= swd_check_reconnect(dap
);
306 if (retval
!= ERROR_OK
)
309 return swd_queue_dp_write_inner(dap
, reg
, data
);
312 /** Select the AP register bank matching bits 7:4 of reg. */
313 static int swd_queue_ap_bankselect(struct adiv5_ap
*ap
, unsigned reg
)
315 struct adiv5_dap
*dap
= ap
->dap
;
316 uint32_t sel
= ((uint32_t)ap
->ap_num
<< 24)
318 | (dap
->select
& DP_SELECT_DPBANK
);
320 if (sel
== dap
->select
)
325 int retval
= swd_queue_dp_write_inner(dap
, DP_SELECT
, sel
);
326 if (retval
!= ERROR_OK
)
327 dap
->select
= DP_SELECT_INVALID
;
332 static int swd_queue_ap_read(struct adiv5_ap
*ap
, unsigned reg
,
335 struct adiv5_dap
*dap
= ap
->dap
;
336 const struct swd_driver
*swd
= adiv5_dap_swd_driver(dap
);
339 int retval
= swd_check_reconnect(dap
);
340 if (retval
!= ERROR_OK
)
343 retval
= swd_queue_ap_bankselect(ap
, reg
);
344 if (retval
!= ERROR_OK
)
347 swd
->read_reg(swd_cmd(true, true, reg
), dap
->last_read
, ap
->memaccess_tck
);
348 dap
->last_read
= data
;
350 return check_sync(dap
);
353 static int swd_queue_ap_write(struct adiv5_ap
*ap
, unsigned reg
,
356 struct adiv5_dap
*dap
= ap
->dap
;
357 const struct swd_driver
*swd
= adiv5_dap_swd_driver(dap
);
360 int retval
= swd_check_reconnect(dap
);
361 if (retval
!= ERROR_OK
)
364 swd_finish_read(dap
);
365 retval
= swd_queue_ap_bankselect(ap
, reg
);
366 if (retval
!= ERROR_OK
)
369 swd
->write_reg(swd_cmd(false, true, reg
), data
, ap
->memaccess_tck
);
371 return check_sync(dap
);
374 /** Executes all queued DAP operations. */
375 static int swd_run(struct adiv5_dap
*dap
)
377 swd_finish_read(dap
);
378 return swd_run_inner(dap
);
381 /** Put the SWJ-DP back to JTAG mode */
382 static void swd_quit(struct adiv5_dap
*dap
)
384 const struct swd_driver
*swd
= adiv5_dap_swd_driver(dap
);
386 swd
->switch_seq(SWD_TO_JTAG
);
387 /* flush the queue before exit */
391 const struct dap_ops swd_dap_ops
= {
392 .connect
= swd_connect
,
393 .send_sequence
= swd_send_sequence
,
394 .queue_dp_read
= swd_queue_dp_read
,
395 .queue_dp_write
= swd_queue_dp_write
,
396 .queue_ap_read
= swd_queue_ap_read
,
397 .queue_ap_write
= swd_queue_ap_write
,
398 .queue_ap_abort
= swd_queue_ap_abort
,
403 static const struct command_registration swd_commands
[] = {
406 * Set up SWD and JTAG targets identically, unless/until
407 * infrastructure improves ... meanwhile, ignore all
408 * JTAG-specific stuff like IR length for SWD.
410 * REVISIT can we verify "just one SWD DAP" here/early?
413 .jim_handler
= jim_jtag_newtap
,
414 .mode
= COMMAND_CONFIG
,
415 .help
= "declare a new SWD DAP"
417 COMMAND_REGISTRATION_DONE
420 static const struct command_registration swd_handlers
[] = {
424 .help
= "SWD command group",
425 .chain
= swd_commands
,
428 COMMAND_REGISTRATION_DONE
431 static int swd_select(struct command_context
*ctx
)
433 /* FIXME: only place where global 'adapter_driver' is still needed */
434 extern struct adapter_driver
*adapter_driver
;
435 const struct swd_driver
*swd
= adapter_driver
->swd_ops
;
438 retval
= register_commands(ctx
, NULL
, swd_handlers
);
439 if (retval
!= ERROR_OK
)
442 /* be sure driver is in SWD mode; start
443 * with hardware default TRN (1), it can be changed later
445 if (!swd
|| !swd
->read_reg
|| !swd
->write_reg
|| !swd
->init
) {
446 LOG_DEBUG("no SWD driver?");
450 retval
= swd
->init();
451 if (retval
!= ERROR_OK
) {
452 LOG_DEBUG("can't init SWD driver");
459 static int swd_init(struct command_context
*ctx
)
461 /* nothing done here, SWD is initialized
462 * together with the DAP */
466 static struct transport swd_transport
= {
468 .select
= swd_select
,
472 static void swd_constructor(void) __attribute__((constructor
));
473 static void swd_constructor(void)
475 transport_register(&swd_transport
);
478 /** Returns true if the current debug session
479 * is using SWD as its transport.
481 bool transport_is_swd(void)
483 return get_current_transport() == &swd_transport
;
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