src/target/adi_v5_swd.c

   1 /***************************************************************************
   2  *
   3  *   Copyright (C) 2010 by David Brownell
   4  *
   5  *   This program is free software; you can redistribute it and/or modify
   6  *   it under the terms of the GNU General Public License as published by
   7  *   the Free Software Foundation; either version 2 of the License, or
   8  *   (at your option) any later version.
   9  *
  10  *   This program is distributed in the hope that it will be useful,
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *   GNU General Public License for more details.
  14  *
  15  *   You should have received a copy of the GNU General Public License
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  ***************************************************************************/
  18
  19 /**
  20  * @file
  21  * Utilities to support ARM "Serial Wire Debug" (SWD), a low pin-count debug
  22  * link protocol used in cases where JTAG is not wanted.  This is coupled to
  23  * recent versions of ARM's "CoreSight" debug framework.  This specific code
  24  * is a transport level interface, with "target/arm_adi_v5.[hc]" code
  25  * understanding operation semantics, shared with the JTAG transport.
  26  *
  27  * Single-DAP support only.
  28  *
  29  * for details, see "ARM IHI 0031A"
  30  * ARM Debug Interface v5 Architecture Specification
  31  * especially section 5.3 for SWD protocol
  32  *
  33  * On many chips (most current Cortex-M3 parts) SWD is a run-time alternative
  34  * to JTAG.  Boards may support one or both.  There are also SWD-only chips,
  35  * (using SW-DP not SWJ-DP).
  36  *
  37  * Even boards that also support JTAG can benefit from SWD support, because
  38  * usually there's no way to access the SWO trace view mechanism in JTAG mode.
  39  * That is, trace access may require SWD support.
  40  *
  41  */
  42
  43 #ifdef HAVE_CONFIG_H
  44 #include "config.h"
  45 #endif
  46
  47 #include "arm.h"
  48 #include "arm_adi_v5.h"
  49 #include <helper/time_support.h>
  50
  51 #include <transport/transport.h>
  52 #include <jtag/interface.h>
  53
  54 #include <jtag/swd.h>
  55
  56 static bool do_sync;
  57
  58 static void swd_finish_read(struct adiv5_dap *dap)
  59 {
  60         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
  61         if (dap->last_read != NULL) {
  62                 swd->read_reg(swd_cmd(true, false, DP_RDBUFF), dap->last_read, 0);
  63                 dap->last_read = NULL;
  64         }
  65 }
  66
  67 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
  68                 uint32_t data);
  69 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
  70                 uint32_t *data);
  71
  72 static void swd_clear_sticky_errors(struct adiv5_dap *dap)
  73 {
  74         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
  75         assert(swd);
  76
  77         swd->write_reg(swd_cmd(false,  false, DP_ABORT),
  78                 STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
  79 }
  80
  81 static int swd_run_inner(struct adiv5_dap *dap)
  82 {
  83         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
  84         int retval;
  85
  86         retval = swd->run();
  87
  88         if (retval != ERROR_OK) {
  89                 /* fault response */
  90                 dap->do_reconnect = true;
  91         }
  92
  93         return retval;
  94 }
  95
  96 static int swd_connect(struct adiv5_dap *dap)
  97 {
  98         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
  99         uint32_t dpidr;
 100         int status;
 101
 102         /* FIXME validate transport config ... is the
 103          * configured DAP present (check IDCODE)?
 104          * Is *only* one DAP configured?
 105          *
 106          * MUST READ DPIDR
 107          */
 108
 109         /* Check if we should reset srst already when connecting, but not if reconnecting. */
 110         if (!dap->do_reconnect) {
 111                 enum reset_types jtag_reset_config = jtag_get_reset_config();
 112
 113                 if (jtag_reset_config & RESET_CNCT_UNDER_SRST) {
 114                         if (jtag_reset_config & RESET_SRST_NO_GATING)
 115                                 swd_add_reset(1);
 116                         else
 117                                 LOG_WARNING("\'srst_nogate\' reset_config option is required");
 118                 }
 119         }
 120
 121         /* Note, debugport_init() does setup too */
 122         swd->switch_seq(JTAG_TO_SWD);
 123
 124         /* Clear link state, including the SELECT cache. */
 125         dap->do_reconnect = false;
 126         dap_invalidate_cache(dap);
 127
 128         swd_queue_dp_read(dap, DP_DPIDR, &dpidr);
 129
 130         /* force clear all sticky faults */
 131         swd_clear_sticky_errors(dap);
 132
 133         status = swd_run_inner(dap);
 134
 135         if (status == ERROR_OK) {
 136                 LOG_INFO("SWD DPIDR %#8.8" PRIx32, dpidr);
 137                 dap->do_reconnect = false;
 138                 status = dap_dp_init(dap);
 139         } else
 140                 dap->do_reconnect = true;
 141
 142         return status;
 143 }
 144
 145 static inline int check_sync(struct adiv5_dap *dap)
 146 {
 147         return do_sync ? swd_run_inner(dap) : ERROR_OK;
 148 }
 149
 150 static int swd_check_reconnect(struct adiv5_dap *dap)
 151 {
 152         if (dap->do_reconnect)
 153                 return swd_connect(dap);
 154
 155         return ERROR_OK;
 156 }
 157
 158 static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
 159 {
 160         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 161         assert(swd);
 162
 163         swd->write_reg(swd_cmd(false,  false, DP_ABORT),
 164                 DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
 165         return check_sync(dap);
 166 }
 167
 168 /** Select the DP register bank matching bits 7:4 of reg. */
 169 static void swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
 170 {
 171         /* Only register address 4 is banked. */
 172         if ((reg & 0xf) != 4)
 173                 return;
 174
 175         uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
 176         uint32_t sel = select_dp_bank
 177                         | (dap->select & (DP_SELECT_APSEL | DP_SELECT_APBANK));
 178
 179         if (sel == dap->select)
 180                 return;
 181
 182         dap->select = sel;
 183
 184         swd_queue_dp_write(dap, DP_SELECT, sel);
 185 }
 186
 187 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
 188                 uint32_t *data)
 189 {
 190         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 191         assert(swd);
 192
 193         int retval = swd_check_reconnect(dap);
 194         if (retval != ERROR_OK)
 195                 return retval;
 196
 197         swd_queue_dp_bankselect(dap, reg);
 198         swd->read_reg(swd_cmd(true,  false, reg), data, 0);
 199
 200         return check_sync(dap);
 201 }
 202
 203 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
 204                 uint32_t data)
 205 {
 206         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 207         assert(swd);
 208
 209         int retval = swd_check_reconnect(dap);
 210         if (retval != ERROR_OK)
 211                 return retval;
 212
 213         swd_finish_read(dap);
 214         swd_queue_dp_bankselect(dap, reg);
 215         swd->write_reg(swd_cmd(false,  false, reg), data, 0);
 216
 217         return check_sync(dap);
 218 }
 219
 220 /** Select the AP register bank matching bits 7:4 of reg. */
 221 static void swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
 222 {
 223         struct adiv5_dap *dap = ap->dap;
 224         uint32_t sel = ((uint32_t)ap->ap_num << 24)
 225                         | (reg & 0x000000F0)
 226                         | (dap->select & DP_SELECT_DPBANK);
 227
 228         if (sel == dap->select)
 229                 return;
 230
 231         dap->select = sel;
 232
 233         swd_queue_dp_write(dap, DP_SELECT, sel);
 234 }
 235
 236 static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
 237                 uint32_t *data)
 238 {
 239         struct adiv5_dap *dap = ap->dap;
 240         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 241         assert(swd);
 242
 243         int retval = swd_check_reconnect(dap);
 244         if (retval != ERROR_OK)
 245                 return retval;
 246
 247         swd_queue_ap_bankselect(ap, reg);
 248         swd->read_reg(swd_cmd(true,  true, reg), dap->last_read, ap->memaccess_tck);
 249         dap->last_read = data;
 250
 251         return check_sync(dap);
 252 }
 253
 254 static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg,
 255                 uint32_t data)
 256 {
 257         struct adiv5_dap *dap = ap->dap;
 258         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 259         assert(swd);
 260
 261         int retval = swd_check_reconnect(dap);
 262         if (retval != ERROR_OK)
 263                 return retval;
 264
 265         swd_finish_read(dap);
 266         swd_queue_ap_bankselect(ap, reg);
 267         swd->write_reg(swd_cmd(false,  true, reg), data, ap->memaccess_tck);
 268
 269         return check_sync(dap);
 270 }
 271
 272 /** Executes all queued DAP operations. */
 273 static int swd_run(struct adiv5_dap *dap)
 274 {
 275         swd_finish_read(dap);
 276         return swd_run_inner(dap);
 277 }
 278
 279 /** Put the SWJ-DP back to JTAG mode */
 280 static void swd_quit(struct adiv5_dap *dap)
 281 {
 282         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 283
 284         swd->switch_seq(SWD_TO_JTAG);
 285         /* flush the queue before exit */
 286         swd->run();
 287 }
 288
 289 const struct dap_ops swd_dap_ops = {
 290         .connect = swd_connect,
 291         .queue_dp_read = swd_queue_dp_read,
 292         .queue_dp_write = swd_queue_dp_write,
 293         .queue_ap_read = swd_queue_ap_read,
 294         .queue_ap_write = swd_queue_ap_write,
 295         .queue_ap_abort = swd_queue_ap_abort,
 296         .run = swd_run,
 297         .quit = swd_quit,
 298 };
 299
 300 /*
 301  * This represents the bits which must be sent out on TMS/SWDIO to
 302  * switch a DAP implemented using an SWJ-DP module into SWD mode.
 303  * These bits are stored (and transmitted) LSB-first.
 304  *
 305  * See the DAP-Lite specification, section 2.2.5 for information
 306  * about making the debug link select SWD or JTAG.  (Similar info
 307  * is in a few other ARM documents.)
 308  */
 309 static const uint8_t jtag2swd_bitseq[] = {
 310         /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
 311          * putting both JTAG and SWD logic into reset state.
 312          */
 313         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 314         /* Switching sequence enables SWD and disables JTAG
 315          * NOTE: bits in the DP's IDCODE may expose the need for
 316          * an old/obsolete/deprecated sequence (0xb6 0xed).
 317          */
 318         0x9e, 0xe7,
 319         /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
 320          * putting both JTAG and SWD logic into reset state.
 321          */
 322         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 323 };
 324
 325 /**
 326  * Put the debug link into SWD mode, if the target supports it.
 327  * The link's initial mode may be either JTAG (for example,
 328  * with SWJ-DP after reset) or SWD.
 329  *
 330  * @param target Enters SWD mode (if possible).
 331  *
 332  * Note that targets using the JTAG-DP do not support SWD, and that
 333  * some targets which could otherwise support it may have have been
 334  * configured to disable SWD signaling
 335  *
 336  * @return ERROR_OK or else a fault code.
 337  */
 338 int dap_to_swd(struct target *target)
 339 {
 340         struct arm *arm = target_to_arm(target);
 341         int retval;
 342
 343         if (!arm->dap) {
 344                 LOG_ERROR("SWD mode is not available");
 345                 return ERROR_FAIL;
 346         }
 347
 348         LOG_DEBUG("Enter SWD mode");
 349
 350         /* REVISIT it's ugly to need to make calls to a "jtag"
 351          * subsystem if the link may not be in JTAG mode...
 352          */
 353
 354         retval =  jtag_add_tms_seq(8 * sizeof(jtag2swd_bitseq),
 355                         jtag2swd_bitseq, TAP_INVALID);
 356         if (retval == ERROR_OK)
 357                 retval = jtag_execute_queue();
 358
 359         /* set up the DAP's ops vector for SWD mode. */
 360         arm->dap->ops = &swd_dap_ops;
 361
 362         return retval;
 363 }
 364
 365 static const struct command_registration swd_commands[] = {
 366         {
 367                 /*
 368                  * Set up SWD and JTAG targets identically, unless/until
 369                  * infrastructure improves ...  meanwhile, ignore all
 370                  * JTAG-specific stuff like IR length for SWD.
 371                  *
 372                  * REVISIT can we verify "just one SWD DAP" here/early?
 373                  */
 374                 .name = "newdap",
 375                 .jim_handler = jim_jtag_newtap,
 376                 .mode = COMMAND_CONFIG,
 377                 .help = "declare a new SWD DAP"
 378         },
 379         COMMAND_REGISTRATION_DONE
 380 };
 381
 382 static const struct command_registration swd_handlers[] = {
 383         {
 384                 .name = "swd",
 385                 .mode = COMMAND_ANY,
 386                 .help = "SWD command group",
 387                 .chain = swd_commands,
 388         },
 389         COMMAND_REGISTRATION_DONE
 390 };
 391
 392 static int swd_select(struct command_context *ctx)
 393 {
 394         /* FIXME: only place where global 'jtag_interface' is still needed */
 395         extern struct jtag_interface *jtag_interface;
 396         const struct swd_driver *swd = jtag_interface->swd;
 397         int retval;
 398
 399         retval = register_commands(ctx, NULL, swd_handlers);
 400         if (retval != ERROR_OK)
 401                 return retval;
 402
 403          /* be sure driver is in SWD mode; start
 404           * with hardware default TRN (1), it can be changed later
 405           */
 406         if (!swd || !swd->read_reg || !swd->write_reg || !swd->init) {
 407                 LOG_DEBUG("no SWD driver?");
 408                 return ERROR_FAIL;
 409         }
 410
 411         retval = swd->init();
 412         if (retval != ERROR_OK) {
 413                 LOG_DEBUG("can't init SWD driver");
 414                 return retval;
 415         }
 416
 417         return retval;
 418 }
 419
 420 static int swd_init(struct command_context *ctx)
 421 {
 422         /* nothing done here, SWD is initialized
 423          * together with the DAP */
 424         return ERROR_OK;
 425 }
 426
 427 static struct transport swd_transport = {
 428         .name = "swd",
 429         .select = swd_select,
 430         .init = swd_init,
 431 };
 432
 433 static void swd_constructor(void) __attribute__((constructor));
 434 static void swd_constructor(void)
 435 {
 436         transport_register(&swd_transport);
 437 }
 438
 439 /** Returns true if the current debug session
 440  * is using SWD as its transport.
 441  */
 442 bool transport_is_swd(void)
 443 {
 444         return get_current_transport() == &swd_transport;
 445 }