src/target/adi_v5_swd.c

   1 /***************************************************************************
   2  *
   3  *   Copyright (C) 2010 by David Brownell
   4  *
   5  *   This program is free software; you can redistribute it and/or modify
   6  *   it under the terms of the GNU General Public License as published by
   7  *   the Free Software Foundation; either version 2 of the License, or
   8  *   (at your option) any later version.
   9  *
  10  *   This program is distributed in the hope that it will be useful,
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *   GNU General Public License for more details.
  14  *
  15  *   You should have received a copy of the GNU General Public License
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  ***************************************************************************/
  18
  19 /**
  20  * @file
  21  * Utilities to support ARM "Serial Wire Debug" (SWD), a low pin-count debug
  22  * link protocol used in cases where JTAG is not wanted.  This is coupled to
  23  * recent versions of ARM's "CoreSight" debug framework.  This specific code
  24  * is a transport level interface, with "target/arm_adi_v5.[hc]" code
  25  * understanding operation semantics, shared with the JTAG transport.
  26  *
  27  * Single-DAP support only.
  28  *
  29  * for details, see "ARM IHI 0031A"
  30  * ARM Debug Interface v5 Architecture Specification
  31  * especially section 5.3 for SWD protocol
  32  *
  33  * On many chips (most current Cortex-M3 parts) SWD is a run-time alternative
  34  * to JTAG.  Boards may support one or both.  There are also SWD-only chips,
  35  * (using SW-DP not SWJ-DP).
  36  *
  37  * Even boards that also support JTAG can benefit from SWD support, because
  38  * usually there's no way to access the SWO trace view mechanism in JTAG mode.
  39  * That is, trace access may require SWD support.
  40  *
  41  */
  42
  43 #ifdef HAVE_CONFIG_H
  44 #include "config.h"
  45 #endif
  46
  47 #include "arm.h"
  48 #include "arm_adi_v5.h"
  49 #include <helper/time_support.h>
  50
  51 #include <transport/transport.h>
  52 #include <jtag/interface.h>
  53
  54 #include <jtag/swd.h>
  55
  56 /* YUK! - but this is currently a global.... */
  57 extern struct jtag_interface *jtag_interface;
  58 static bool do_sync;
  59
  60 static void swd_finish_read(struct adiv5_dap *dap)
  61 {
  62         const struct swd_driver *swd = jtag_interface->swd;
  63         if (dap->last_read != NULL) {
  64                 swd->read_reg(swd_cmd(true, false, DP_RDBUFF), dap->last_read, 0);
  65                 dap->last_read = NULL;
  66         }
  67 }
  68
  69 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
  70                 uint32_t data);
  71 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
  72                 uint32_t *data);
  73
  74 static void swd_clear_sticky_errors(struct adiv5_dap *dap)
  75 {
  76         const struct swd_driver *swd = jtag_interface->swd;
  77         assert(swd);
  78
  79         swd->write_reg(swd_cmd(false,  false, DP_ABORT),
  80                 STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
  81 }
  82
  83 static int swd_run_inner(struct adiv5_dap *dap)
  84 {
  85         const struct swd_driver *swd = jtag_interface->swd;
  86         int retval;
  87
  88         retval = swd->run();
  89
  90         if (retval != ERROR_OK) {
  91                 /* fault response */
  92                 dap->do_reconnect = true;
  93         }
  94
  95         return retval;
  96 }
  97
  98 static int swd_connect(struct adiv5_dap *dap)
  99 {
 100         uint32_t dpidr;
 101         int status;
 102
 103         /* FIXME validate transport config ... is the
 104          * configured DAP present (check IDCODE)?
 105          * Is *only* one DAP configured?
 106          *
 107          * MUST READ DPIDR
 108          */
 109
 110         /* Check if we should reset srst already when connecting, but not if reconnecting. */
 111         if (!dap->do_reconnect) {
 112                 enum reset_types jtag_reset_config = jtag_get_reset_config();
 113
 114                 if (jtag_reset_config & RESET_CNCT_UNDER_SRST) {
 115                         if (jtag_reset_config & RESET_SRST_NO_GATING)
 116                                 swd_add_reset(1);
 117                         else
 118                                 LOG_WARNING("\'srst_nogate\' reset_config option is required");
 119                 }
 120         }
 121
 122         /* Note, debugport_init() does setup too */
 123         jtag_interface->swd->switch_seq(JTAG_TO_SWD);
 124
 125         /* Clear link state, including the SELECT cache. */
 126         dap->do_reconnect = false;
 127         dap_invalidate_cache(dap);
 128
 129         swd_queue_dp_read(dap, DP_DPIDR, &dpidr);
 130
 131         /* force clear all sticky faults */
 132         swd_clear_sticky_errors(dap);
 133
 134         status = swd_run_inner(dap);
 135
 136         if (status == ERROR_OK) {
 137                 LOG_INFO("SWD DPIDR %#8.8" PRIx32, dpidr);
 138                 dap->do_reconnect = false;
 139         } else
 140                 dap->do_reconnect = true;
 141
 142         return status;
 143 }
 144
 145 static inline int check_sync(struct adiv5_dap *dap)
 146 {
 147         return do_sync ? swd_run_inner(dap) : ERROR_OK;
 148 }
 149
 150 static int swd_check_reconnect(struct adiv5_dap *dap)
 151 {
 152         if (dap->do_reconnect)
 153                 return swd_connect(dap);
 154
 155         return ERROR_OK;
 156 }
 157
 158 static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
 159 {
 160         const struct swd_driver *swd = jtag_interface->swd;
 161         assert(swd);
 162
 163         swd->write_reg(swd_cmd(false,  false, DP_ABORT),
 164                 DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
 165         return check_sync(dap);
 166 }
 167
 168 /** Select the DP register bank matching bits 7:4 of reg. */
 169 static void swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
 170 {
 171         /* Only register address 4 is banked. */
 172         if ((reg & 0xf) != 4)
 173                 return;
 174
 175         uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
 176         uint32_t sel = select_dp_bank
 177                         | (dap->select & (DP_SELECT_APSEL | DP_SELECT_APBANK));
 178
 179         if (sel == dap->select)
 180                 return;
 181
 182         dap->select = sel;
 183
 184         swd_queue_dp_write(dap, DP_SELECT, sel);
 185 }
 186
 187 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
 188                 uint32_t *data)
 189 {
 190         const struct swd_driver *swd = jtag_interface->swd;
 191         assert(swd);
 192
 193         int retval = swd_check_reconnect(dap);
 194         if (retval != ERROR_OK)
 195                 return retval;
 196
 197         swd_queue_dp_bankselect(dap, reg);
 198         swd->read_reg(swd_cmd(true,  false, reg), data, 0);
 199
 200         return check_sync(dap);
 201 }
 202
 203 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
 204                 uint32_t data)
 205 {
 206         const struct swd_driver *swd = jtag_interface->swd;
 207         assert(swd);
 208
 209         int retval = swd_check_reconnect(dap);
 210         if (retval != ERROR_OK)
 211                 return retval;
 212
 213         swd_finish_read(dap);
 214         swd_queue_dp_bankselect(dap, reg);
 215         swd->write_reg(swd_cmd(false,  false, reg), data, 0);
 216
 217         return check_sync(dap);
 218 }
 219
 220 /** Select the AP register bank matching bits 7:4 of reg. */
 221 static void swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
 222 {
 223         struct adiv5_dap *dap = ap->dap;
 224         uint32_t sel = ((uint32_t)ap->ap_num << 24)
 225                         | (reg & 0x000000F0)
 226                         | (dap->select & DP_SELECT_DPBANK);
 227
 228         if (sel == dap->select)
 229                 return;
 230
 231         dap->select = sel;
 232
 233         swd_queue_dp_write(dap, DP_SELECT, sel);
 234 }
 235
 236 static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
 237                 uint32_t *data)
 238 {
 239         const struct swd_driver *swd = jtag_interface->swd;
 240         assert(swd);
 241
 242         struct adiv5_dap *dap = ap->dap;
 243
 244         int retval = swd_check_reconnect(dap);
 245         if (retval != ERROR_OK)
 246                 return retval;
 247
 248         swd_queue_ap_bankselect(ap, reg);
 249         swd->read_reg(swd_cmd(true,  true, reg), dap->last_read, ap->memaccess_tck);
 250         dap->last_read = data;
 251
 252         return check_sync(dap);
 253 }
 254
 255 static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg,
 256                 uint32_t data)
 257 {
 258         const struct swd_driver *swd = jtag_interface->swd;
 259         assert(swd);
 260
 261         struct adiv5_dap *dap = ap->dap;
 262
 263         int retval = swd_check_reconnect(dap);
 264         if (retval != ERROR_OK)
 265                 return retval;
 266
 267         swd_finish_read(dap);
 268         swd_queue_ap_bankselect(ap, reg);
 269         swd->write_reg(swd_cmd(false,  true, reg), data, ap->memaccess_tck);
 270
 271         return check_sync(dap);
 272 }
 273
 274 /** Executes all queued DAP operations. */
 275 static int swd_run(struct adiv5_dap *dap)
 276 {
 277         swd_finish_read(dap);
 278         return swd_run_inner(dap);
 279 }
 280
 281 const struct dap_ops swd_dap_ops = {
 282         .queue_dp_read = swd_queue_dp_read,
 283         .queue_dp_write = swd_queue_dp_write,
 284         .queue_ap_read = swd_queue_ap_read,
 285         .queue_ap_write = swd_queue_ap_write,
 286         .queue_ap_abort = swd_queue_ap_abort,
 287         .run = swd_run,
 288 };
 289
 290 /*
 291  * This represents the bits which must be sent out on TMS/SWDIO to
 292  * switch a DAP implemented using an SWJ-DP module into SWD mode.
 293  * These bits are stored (and transmitted) LSB-first.
 294  *
 295  * See the DAP-Lite specification, section 2.2.5 for information
 296  * about making the debug link select SWD or JTAG.  (Similar info
 297  * is in a few other ARM documents.)
 298  */
 299 static const uint8_t jtag2swd_bitseq[] = {
 300         /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
 301          * putting both JTAG and SWD logic into reset state.
 302          */
 303         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 304         /* Switching sequence enables SWD and disables JTAG
 305          * NOTE: bits in the DP's IDCODE may expose the need for
 306          * an old/obsolete/deprecated sequence (0xb6 0xed).
 307          */
 308         0x9e, 0xe7,
 309         /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
 310          * putting both JTAG and SWD logic into reset state.
 311          */
 312         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 313 };
 314
 315 /**
 316  * Put the debug link into SWD mode, if the target supports it.
 317  * The link's initial mode may be either JTAG (for example,
 318  * with SWJ-DP after reset) or SWD.
 319  *
 320  * @param target Enters SWD mode (if possible).
 321  *
 322  * Note that targets using the JTAG-DP do not support SWD, and that
 323  * some targets which could otherwise support it may have have been
 324  * configured to disable SWD signaling
 325  *
 326  * @return ERROR_OK or else a fault code.
 327  */
 328 int dap_to_swd(struct target *target)
 329 {
 330         struct arm *arm = target_to_arm(target);
 331         int retval;
 332
 333         if (!arm->dap) {
 334                 LOG_ERROR("SWD mode is not available");
 335                 return ERROR_FAIL;
 336         }
 337
 338         LOG_DEBUG("Enter SWD mode");
 339
 340         /* REVISIT it's ugly to need to make calls to a "jtag"
 341          * subsystem if the link may not be in JTAG mode...
 342          */
 343
 344         retval =  jtag_add_tms_seq(8 * sizeof(jtag2swd_bitseq),
 345                         jtag2swd_bitseq, TAP_INVALID);
 346         if (retval == ERROR_OK)
 347                 retval = jtag_execute_queue();
 348
 349         /* set up the DAP's ops vector for SWD mode. */
 350         arm->dap->ops = &swd_dap_ops;
 351
 352         return retval;
 353 }
 354
 355 static const struct command_registration swd_commands[] = {
 356         {
 357                 /*
 358                  * Set up SWD and JTAG targets identically, unless/until
 359                  * infrastructure improves ...  meanwhile, ignore all
 360                  * JTAG-specific stuff like IR length for SWD.
 361                  *
 362                  * REVISIT can we verify "just one SWD DAP" here/early?
 363                  */
 364                 .name = "newdap",
 365                 .jim_handler = jim_jtag_newtap,
 366                 .mode = COMMAND_CONFIG,
 367                 .help = "declare a new SWD DAP"
 368         },
 369         COMMAND_REGISTRATION_DONE
 370 };
 371
 372 static const struct command_registration swd_handlers[] = {
 373         {
 374                 .name = "swd",
 375                 .mode = COMMAND_ANY,
 376                 .help = "SWD command group",
 377                 .chain = swd_commands,
 378         },
 379         COMMAND_REGISTRATION_DONE
 380 };
 381
 382 static int swd_select(struct command_context *ctx)
 383 {
 384         int retval;
 385
 386         retval = register_commands(ctx, NULL, swd_handlers);
 387
 388         if (retval != ERROR_OK)
 389                 return retval;
 390
 391         const struct swd_driver *swd = jtag_interface->swd;
 392
 393          /* be sure driver is in SWD mode; start
 394           * with hardware default TRN (1), it can be changed later
 395           */
 396         if (!swd || !swd->read_reg || !swd->write_reg || !swd->init) {
 397                 LOG_DEBUG("no SWD driver?");
 398                 return ERROR_FAIL;
 399         }
 400
 401         retval = swd->init();
 402         if (retval != ERROR_OK) {
 403                 LOG_DEBUG("can't init SWD driver");
 404                 return retval;
 405         }
 406
 407         /* force DAP into SWD mode (not JTAG) */
 408         /*retval = dap_to_swd(target);*/
 409
 410         if (ctx->current_target) {
 411                 /* force DAP into SWD mode (not JTAG) */
 412                 struct target *target = get_current_target(ctx);
 413                 retval = dap_to_swd(target);
 414         }
 415
 416         return retval;
 417 }
 418
 419 static int swd_init(struct command_context *ctx)
 420 {
 421         struct target *target = get_current_target(ctx);
 422         struct arm *arm = target_to_arm(target);
 423         struct adiv5_dap *dap = arm->dap;
 424         /* Force the DAP's ops vector for SWD mode.
 425          * messy - is there a better way? */
 426         arm->dap->ops = &swd_dap_ops;
 427         /* First connect after init is not reconnecting. */
 428         dap->do_reconnect = false;
 429
 430         int retval = swd_connect(dap);
 431         if (retval != ERROR_OK)
 432                 LOG_ERROR("SWD connect failed");
 433         return retval;
 434 }
 435
 436 static struct transport swd_transport = {
 437         .name = "swd",
 438         .select = swd_select,
 439         .init = swd_init,
 440 };
 441
 442 static void swd_constructor(void) __attribute__((constructor));
 443 static void swd_constructor(void)
 444 {
 445         transport_register(&swd_transport);
 446 }
 447
 448 /** Returns true if the current debug session
 449  * is using SWD as its transport.
 450  */
 451 bool transport_is_swd(void)
 452 {
 453         return get_current_transport() == &swd_transport;
 454 }