1 /***************************************************************************
3 * Copyright (C) 2010 by David Brownell
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the
17 * Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 ***************************************************************************/
23 * Utilities to support ARM "Serial Wire Debug" (SWD), a low pin-count debug
24 * link protocol used in cases where JTAG is not wanted. This is coupled to
25 * recent versions of ARM's "CoreSight" debug framework. This specific code
26 * is a transport level interface, with "target/arm_adi_v5.[hc]" code
27 * understanding operation semantics, shared with the JTAG transport.
29 * Single-DAP support only.
31 * for details, see "ARM IHI 0031A"
32 * ARM Debug Interface v5 Architecture Specification
33 * especially section 5.3 for SWD protocol
35 * On many chips (most current Cortex-M3 parts) SWD is a run-time alternative
36 * to JTAG. Boards may support one or both. There are also SWD-only chips,
37 * (using SW-DP not SWJ-DP).
39 * Even boards that also support JTAG can benefit from SWD support, because
40 * usually there's no way to access the SWO trace view mechanism in JTAG mode.
41 * That is, trace access may require SWD support.
50 #include "arm_adi_v5.h"
51 #include <helper/time_support.h>
53 #include <transport/transport.h>
54 #include <jtag/interface.h>
58 /* YUK! - but this is currently a global.... */
59 extern struct jtag_interface
*jtag_interface
;
61 static int (swd_queue_dp_write
)(struct adiv5_dap
*dap
, unsigned reg
,
64 static int swd_queue_ap_abort(struct adiv5_dap
*dap
, uint8_t *ack
)
66 const struct swd_driver
*swd
= jtag_interface
->swd
;
69 return swd
->write_reg(swd_cmd(false, false, DP_ABORT
),
70 STKCMPCLR
| STKERRCLR
| WDERRCLR
| ORUNERRCLR
);
73 /** Select the DP register bank matching bits 7:4 of reg. */
74 static int swd_queue_dp_bankselect(struct adiv5_dap
*dap
, unsigned reg
)
76 uint32_t select_dp_bank
= (reg
& 0x000000F0) >> 4;
81 if (select_dp_bank
== dap
->dp_bank_value
)
84 dap
->dp_bank_value
= select_dp_bank
;
85 select_dp_bank
|= dap
->ap_current
| dap
->ap_bank_value
;
87 return swd_queue_dp_write(dap
, DP_SELECT
, select_dp_bank
);
90 static int swd_queue_dp_read(struct adiv5_dap
*dap
, unsigned reg
,
94 /* REVISIT status return vs ack ... */
95 const struct swd_driver
*swd
= jtag_interface
->swd
;
98 retval
= swd_queue_dp_bankselect(dap
, reg
);
99 if (retval
!= ERROR_OK
)
102 retval
= swd
->read_reg(swd_cmd(true, false, reg
), data
);
104 if (retval
!= ERROR_OK
) {
106 uint8_t ack
= retval
& 0xff;
107 swd_queue_ap_abort(dap
, &ack
);
113 static int swd_queue_idcode_read(struct adiv5_dap
*dap
,
114 uint8_t *ack
, uint32_t *data
)
116 int status
= swd_queue_dp_read(dap
, DP_IDCODE
, data
);
124 static int (swd_queue_dp_write
)(struct adiv5_dap
*dap
, unsigned reg
,
128 /* REVISIT status return vs ack ... */
129 const struct swd_driver
*swd
= jtag_interface
->swd
;
132 retval
= swd_queue_dp_bankselect(dap
, reg
);
133 if (retval
!= ERROR_OK
)
136 retval
= swd
->write_reg(swd_cmd(false, false, reg
), data
);
138 if (retval
!= ERROR_OK
) {
140 uint8_t ack
= retval
& 0xff;
141 swd_queue_ap_abort(dap
, &ack
);
147 /** Select the AP register bank matching bits 7:4 of reg. */
148 static int swd_queue_ap_bankselect(struct adiv5_dap
*dap
, unsigned reg
)
150 uint32_t select_ap_bank
= reg
& 0x000000F0;
152 if (select_ap_bank
== dap
->ap_bank_value
)
155 dap
->ap_bank_value
= select_ap_bank
;
156 select_ap_bank
|= dap
->ap_current
| dap
->dp_bank_value
;
158 return swd_queue_dp_write(dap
, DP_SELECT
, select_ap_bank
);
161 static int (swd_queue_ap_read
)(struct adiv5_dap
*dap
, unsigned reg
,
164 /* REVISIT status return ... */
165 const struct swd_driver
*swd
= jtag_interface
->swd
;
168 int retval
= swd_queue_ap_bankselect(dap
, reg
);
169 if (retval
!= ERROR_OK
)
172 retval
= swd
->read_reg(swd_cmd(true, true, reg
), data
);
174 if (retval
!= ERROR_OK
) {
176 uint8_t ack
= retval
& 0xff;
177 swd_queue_ap_abort(dap
, &ack
);
183 static int (swd_queue_ap_write
)(struct adiv5_dap
*dap
, unsigned reg
,
186 /* REVISIT status return ... */
187 const struct swd_driver
*swd
= jtag_interface
->swd
;
190 int retval
= swd_queue_ap_bankselect(dap
, reg
);
191 if (retval
!= ERROR_OK
)
194 retval
= swd
->write_reg(swd_cmd(false, true, reg
), data
);
196 if (retval
!= ERROR_OK
) {
198 uint8_t ack
= retval
& 0xff;
199 swd_queue_ap_abort(dap
, &ack
);
205 /** Executes all queued DAP operations. */
206 static int swd_run(struct adiv5_dap
*dap
)
208 /* for now the SWD interface hard-wires a zero-size queue. */
210 /* FIXME but we still need to check and scrub
211 * any hardware errors ...
216 const struct dap_ops swd_dap_ops
= {
219 .queue_idcode_read
= swd_queue_idcode_read
,
220 .queue_dp_read
= swd_queue_dp_read
,
221 .queue_dp_write
= swd_queue_dp_write
,
222 .queue_ap_read
= swd_queue_ap_read
,
223 .queue_ap_write
= swd_queue_ap_write
,
224 .queue_ap_abort
= swd_queue_ap_abort
,
229 * This represents the bits which must be sent out on TMS/SWDIO to
230 * switch a DAP implemented using an SWJ-DP module into SWD mode.
231 * These bits are stored (and transmitted) LSB-first.
233 * See the DAP-Lite specification, section 2.2.5 for information
234 * about making the debug link select SWD or JTAG. (Similar info
235 * is in a few other ARM documents.)
237 static const uint8_t jtag2swd_bitseq
[] = {
238 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
239 * putting both JTAG and SWD logic into reset state.
241 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
242 /* Switching sequence enables SWD and disables JTAG
243 * NOTE: bits in the DP's IDCODE may expose the need for
244 * an old/obsolete/deprecated sequence (0xb6 0xed).
247 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
248 * putting both JTAG and SWD logic into reset state.
250 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
254 * Put the debug link into SWD mode, if the target supports it.
255 * The link's initial mode may be either JTAG (for example,
256 * with SWJ-DP after reset) or SWD.
258 * @param target Enters SWD mode (if possible).
260 * Note that targets using the JTAG-DP do not support SWD, and that
261 * some targets which could otherwise support it may have have been
262 * configured to disable SWD signaling
264 * @return ERROR_OK or else a fault code.
266 int dap_to_swd(struct target
*target
)
268 struct arm
*arm
= target_to_arm(target
);
271 LOG_DEBUG("Enter SWD mode");
273 /* REVISIT it's ugly to need to make calls to a "jtag"
274 * subsystem if the link may not be in JTAG mode...
277 retval
= jtag_add_tms_seq(8 * sizeof(jtag2swd_bitseq
),
278 jtag2swd_bitseq
, TAP_INVALID
);
279 if (retval
== ERROR_OK
)
280 retval
= jtag_execute_queue();
282 /* set up the DAP's ops vector for SWD mode. */
283 arm
->dap
->ops
= &swd_dap_ops
;
288 COMMAND_HANDLER(handle_swd_wcr
)
291 struct target
*target
= get_current_target(CMD_CTX
);
292 struct arm
*arm
= target_to_arm(target
);
293 struct adiv5_dap
*dap
= arm
->dap
;
295 unsigned trn
, scale
= 0;
298 /* no-args: just dump state */
300 /*retval = swd_queue_dp_read(dap, DP_WCR, &wcr); */
301 retval
= dap_queue_dp_read(dap
, DP_WCR
, &wcr
);
302 if (retval
== ERROR_OK
)
304 if (retval
!= ERROR_OK
) {
305 LOG_ERROR("can't read WCR?");
309 command_print(CMD_CTX
,
310 "turnaround=%" PRIu32
", prescale=%" PRIu32
,
312 WCR_TO_PRESCALE(wcr
));
315 case 2: /* TRN and prescale */
316 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[1], scale
);
318 LOG_ERROR("prescale %d is too big", scale
);
323 case 1: /* TRN only */
324 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[0], trn
);
325 if (trn
< 1 || trn
> 4) {
326 LOG_ERROR("turnaround %d is invalid", trn
);
330 wcr
= ((trn
- 1) << 8) | scale
;
333 * then, re-init adapter with new TRN
335 LOG_ERROR("can't yet modify WCR");
338 default: /* too many arguments */
339 return ERROR_COMMAND_SYNTAX_ERROR
;
343 static const struct command_registration swd_commands
[] = {
346 * Set up SWD and JTAG targets identically, unless/until
347 * infrastructure improves ... meanwhile, ignore all
348 * JTAG-specific stuff like IR length for SWD.
350 * REVISIT can we verify "just one SWD DAP" here/early?
353 .jim_handler
= jim_jtag_newtap
,
354 .mode
= COMMAND_CONFIG
,
355 .help
= "declare a new SWD DAP"
359 .handler
= handle_swd_wcr
,
361 .help
= "display or update DAP's WCR register",
362 .usage
= "turnaround (1..4), prescale (0..7)",
365 /* REVISIT -- add a command for SWV trace on/off */
366 COMMAND_REGISTRATION_DONE
369 static const struct command_registration swd_handlers
[] = {
373 .help
= "SWD command group",
374 .chain
= swd_commands
,
376 COMMAND_REGISTRATION_DONE
379 static int swd_select(struct command_context
*ctx
)
383 retval
= register_commands(ctx
, NULL
, swd_handlers
);
385 if (retval
!= ERROR_OK
)
388 const struct swd_driver
*swd
= jtag_interface
->swd
;
390 /* be sure driver is in SWD mode; start
391 * with hardware default TRN (1), it can be changed later
393 if (!swd
|| !swd
->read_reg
|| !swd
->write_reg
|| !swd
->init
) {
394 LOG_DEBUG("no SWD driver?");
398 retval
= swd
->init(1);
399 if (retval
!= ERROR_OK
) {
400 LOG_DEBUG("can't init SWD driver");
404 /* force DAP into SWD mode (not JTAG) */
405 /*retval = dap_to_swd(target);*/
407 if (ctx
->current_target
) {
408 /* force DAP into SWD mode (not JTAG) */
409 struct target
*target
= get_current_target(ctx
);
410 retval
= dap_to_swd(target
);
416 static int swd_init(struct command_context
*ctx
)
418 struct target
*target
= get_current_target(ctx
);
419 struct arm
*arm
= target_to_arm(target
);
420 struct adiv5_dap
*dap
= arm
->dap
;
424 /* Force the DAP's ops vector for SWD mode.
425 * messy - is there a better way? */
426 arm
->dap
->ops
= &swd_dap_ops
;
428 /* FIXME validate transport config ... is the
429 * configured DAP present (check IDCODE)?
430 * Is *only* one DAP configured?
435 /* Note, debugport_init() does setup too */
439 status
= swd_queue_idcode_read(dap
, &ack
, &idcode
);
441 if (status
== ERROR_OK
)
442 LOG_INFO("SWD IDCODE %#8.8" PRIx32
, idcode
);
444 /* force clear all sticky faults */
445 swd_queue_ap_abort(dap
, &ack
);
447 /* this is a workaround to get polling working */
448 jtag_add_reset(0, 0);
453 static struct transport swd_transport
= {
455 .select
= swd_select
,
459 static void swd_constructor(void) __attribute__((constructor
));
460 static void swd_constructor(void)
462 transport_register(&swd_transport
);
465 /** Returns true if the current debug session
466 * is using SWD as its transport.
468 bool transport_is_swd(void)
470 return get_current_transport() == &swd_transport
;
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