src/target/adi_v5_swd.c

   1 /***************************************************************************
   2  *
   3  *   Copyright (C) 2010 by David Brownell
   4  *
   5  *   This program is free software; you can redistribute it and/or modify
   6  *   it under the terms of the GNU General Public License as published by
   7  *   the Free Software Foundation; either version 2 of the License, or
   8  *   (at your option) any later version.
   9  *
  10  *   This program is distributed in the hope that it will be useful,
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *   GNU General Public License for more details.
  14  *
  15  *   You should have received a copy of the GNU General Public License
  16  *   along with this program; if not, write to the
  17  *   Free Software Foundation, Inc.,
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  19  ***************************************************************************/
  20
  21 /**
  22  * @file
  23  * Utilities to support ARM "Serial Wire Debug" (SWD), a low pin-count debug
  24  * link protocol used in cases where JTAG is not wanted.  This is coupled to
  25  * recent versions of ARM's "CoreSight" debug framework.  This specific code
  26  * is a transport level interface, with "target/arm_adi_v5.[hc]" code
  27  * understanding operation semantics, shared with the JTAG transport.
  28  *
  29  * Single-DAP support only.
  30  *
  31  * for details, see "ARM IHI 0031A"
  32  * ARM Debug Interface v5 Architecture Specification
  33  * especially section 5.3 for SWD protocol
  34  *
  35  * On many chips (most current Cortex-M3 parts) SWD is a run-time alternative
  36  * to JTAG.  Boards may support one or both.  There are also SWD-only chips,
  37  * (using SW-DP not SWJ-DP).
  38  *
  39  * Even boards that also support JTAG can benefit from SWD support, because
  40  * usually there's no way to access the SWO trace view mechanism in JTAG mode.
  41  * That is, trace access may require SWD support.
  42  *
  43  */
  44
  45 #ifdef HAVE_CONFIG_H
  46 #include "config.h"
  47 #endif
  48
  49 #include "arm.h"
  50 #include "arm_adi_v5.h"
  51 #include <helper/time_support.h>
  52
  53 #include <transport/transport.h>
  54 #include <jtag/interface.h>
  55
  56 #include <jtag/swd.h>
  57
  58 /* YUK! - but this is currently a global.... */
  59 extern struct jtag_interface *jtag_interface;
  60
  61 static int swd_finish_read(struct adiv5_dap *dap)
  62 {
  63         const struct swd_driver *swd = jtag_interface->swd;
  64         int retval = ERROR_OK;
  65         if (dap->last_read != NULL) {
  66                 retval = swd->read_reg(swd_cmd(true, false, DP_RDBUFF), dap->last_read);
  67                 dap->last_read = NULL;
  68         }
  69         return retval;
  70 }
  71
  72 static int (swd_queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
  73                 uint32_t data);
  74
  75 static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
  76 {
  77         const struct swd_driver *swd = jtag_interface->swd;
  78         assert(swd);
  79
  80         return swd->write_reg(swd_cmd(false,  false, DP_ABORT),
  81                 STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR);
  82 }
  83
  84 /** Select the DP register bank matching bits 7:4 of reg. */
  85 static int swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
  86 {
  87         uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
  88
  89         if (reg == DP_SELECT)
  90                 return ERROR_OK;
  91
  92         if (select_dp_bank == dap->dp_bank_value)
  93                 return ERROR_OK;
  94
  95         dap->dp_bank_value = select_dp_bank;
  96         select_dp_bank |= dap->ap_current | dap->ap_bank_value;
  97
  98         return swd_queue_dp_write(dap, DP_SELECT, select_dp_bank);
  99 }
 100
 101 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
 102                 uint32_t *data)
 103 {
 104         int retval;
 105         /* REVISIT status return vs ack ... */
 106         const struct swd_driver *swd = jtag_interface->swd;
 107         assert(swd);
 108
 109         retval = swd_queue_dp_bankselect(dap, reg);
 110         if (retval != ERROR_OK)
 111                 return retval;
 112
 113         retval = swd->read_reg(swd_cmd(true,  false, reg), data);
 114
 115         if (retval != ERROR_OK) {
 116                 /* fault response */
 117                 uint8_t ack = retval & 0xff;
 118                 swd_queue_ap_abort(dap, &ack);
 119         }
 120
 121         return retval;
 122 }
 123
 124
 125 static int (swd_queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
 126                 uint32_t data)
 127 {
 128         int retval;
 129         /* REVISIT status return vs ack ... */
 130         const struct swd_driver *swd = jtag_interface->swd;
 131         assert(swd);
 132
 133         retval = swd_finish_read(dap);
 134         if (retval != ERROR_OK)
 135                 return retval;
 136
 137         retval = swd_queue_dp_bankselect(dap, reg);
 138         if (retval != ERROR_OK)
 139                 return retval;
 140
 141         retval = swd->write_reg(swd_cmd(false,  false, reg), data);
 142
 143         if (retval != ERROR_OK) {
 144                 /* fault response */
 145                 uint8_t ack = retval & 0xff;
 146                 swd_queue_ap_abort(dap, &ack);
 147         }
 148
 149         return retval;
 150 }
 151
 152 /** Select the AP register bank matching bits 7:4 of reg. */
 153 static int swd_queue_ap_bankselect(struct adiv5_dap *dap, unsigned reg)
 154 {
 155         uint32_t select_ap_bank = reg & 0x000000F0;
 156
 157         if (select_ap_bank == dap->ap_bank_value)
 158                 return ERROR_OK;
 159
 160         dap->ap_bank_value = select_ap_bank;
 161         select_ap_bank |= dap->ap_current | dap->dp_bank_value;
 162
 163         return swd_queue_dp_write(dap, DP_SELECT, select_ap_bank);
 164 }
 165
 166 static int (swd_queue_ap_read)(struct adiv5_dap *dap, unsigned reg,
 167                 uint32_t *data)
 168 {
 169         /* REVISIT status return ... */
 170         const struct swd_driver *swd = jtag_interface->swd;
 171         assert(swd);
 172
 173         int retval = swd_queue_ap_bankselect(dap, reg);
 174         if (retval != ERROR_OK)
 175                 return retval;
 176
 177         retval = swd->read_reg(swd_cmd(true,  true, reg), dap->last_read);
 178         dap->last_read = data;
 179
 180         if (retval != ERROR_OK) {
 181                 /* fault response */
 182                 uint8_t ack = retval & 0xff;
 183                 swd_queue_ap_abort(dap, &ack);
 184                 return retval;
 185         }
 186
 187         return retval;
 188 }
 189
 190 static int (swd_queue_ap_write)(struct adiv5_dap *dap, unsigned reg,
 191                 uint32_t data)
 192 {
 193         /* REVISIT status return ... */
 194         const struct swd_driver *swd = jtag_interface->swd;
 195         assert(swd);
 196         int retval;
 197
 198         retval = swd_finish_read(dap);
 199         if (retval != ERROR_OK)
 200                 return retval;
 201
 202         retval = swd_queue_ap_bankselect(dap, reg);
 203         if (retval != ERROR_OK)
 204                 return retval;
 205
 206         retval = swd->write_reg(swd_cmd(false,  true, reg), data);
 207
 208         if (retval != ERROR_OK) {
 209                 /* fault response */
 210                 uint8_t ack = retval & 0xff;
 211                 swd_queue_ap_abort(dap, &ack);
 212         }
 213
 214         return retval;
 215 }
 216
 217 /** Executes all queued DAP operations. */
 218 static int swd_run(struct adiv5_dap *dap)
 219 {
 220         /* for now the SWD interface hard-wires a zero-size queue.  */
 221
 222         int retval = swd_finish_read(dap);
 223
 224         /* FIXME but we still need to check and scrub
 225          * any hardware errors ...
 226          */
 227         return retval;
 228 }
 229
 230 const struct dap_ops swd_dap_ops = {
 231         .is_swd = true,
 232
 233         .queue_dp_read = swd_queue_dp_read,
 234         .queue_dp_write = swd_queue_dp_write,
 235         .queue_ap_read = swd_queue_ap_read,
 236         .queue_ap_write = swd_queue_ap_write,
 237         .queue_ap_abort = swd_queue_ap_abort,
 238         .run = swd_run,
 239 };
 240
 241 /*
 242  * This represents the bits which must be sent out on TMS/SWDIO to
 243  * switch a DAP implemented using an SWJ-DP module into SWD mode.
 244  * These bits are stored (and transmitted) LSB-first.
 245  *
 246  * See the DAP-Lite specification, section 2.2.5 for information
 247  * about making the debug link select SWD or JTAG.  (Similar info
 248  * is in a few other ARM documents.)
 249  */
 250 static const uint8_t jtag2swd_bitseq[] = {
 251         /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
 252          * putting both JTAG and SWD logic into reset state.
 253          */
 254         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 255         /* Switching sequence enables SWD and disables JTAG
 256          * NOTE: bits in the DP's IDCODE may expose the need for
 257          * an old/obsolete/deprecated sequence (0xb6 0xed).
 258          */
 259         0x9e, 0xe7,
 260         /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
 261          * putting both JTAG and SWD logic into reset state.
 262          */
 263         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 264 };
 265
 266 /**
 267  * Put the debug link into SWD mode, if the target supports it.
 268  * The link's initial mode may be either JTAG (for example,
 269  * with SWJ-DP after reset) or SWD.
 270  *
 271  * @param target Enters SWD mode (if possible).
 272  *
 273  * Note that targets using the JTAG-DP do not support SWD, and that
 274  * some targets which could otherwise support it may have have been
 275  * configured to disable SWD signaling
 276  *
 277  * @return ERROR_OK or else a fault code.
 278  */
 279 int dap_to_swd(struct target *target)
 280 {
 281         struct arm *arm = target_to_arm(target);
 282         int retval;
 283
 284         LOG_DEBUG("Enter SWD mode");
 285
 286         /* REVISIT it's ugly to need to make calls to a "jtag"
 287          * subsystem if the link may not be in JTAG mode...
 288          */
 289
 290         retval =  jtag_add_tms_seq(8 * sizeof(jtag2swd_bitseq),
 291                         jtag2swd_bitseq, TAP_INVALID);
 292         if (retval == ERROR_OK)
 293                 retval = jtag_execute_queue();
 294
 295         /* set up the DAP's ops vector for SWD mode. */
 296         arm->dap->ops = &swd_dap_ops;
 297
 298         return retval;
 299 }
 300
 301 COMMAND_HANDLER(handle_swd_wcr)
 302 {
 303         int retval;
 304         struct target *target = get_current_target(CMD_CTX);
 305         struct arm *arm = target_to_arm(target);
 306         struct adiv5_dap *dap = arm->dap;
 307         uint32_t wcr;
 308         unsigned trn, scale = 0;
 309
 310         switch (CMD_ARGC) {
 311         /* no-args: just dump state */
 312         case 0:
 313                 /*retval = swd_queue_dp_read(dap, DP_WCR, &wcr); */
 314                 retval = dap_queue_dp_read(dap, DP_WCR, &wcr);
 315                 if (retval == ERROR_OK)
 316                         dap->ops->run(dap);
 317                 if (retval != ERROR_OK) {
 318                         LOG_ERROR("can't read WCR?");
 319                         return retval;
 320                 }
 321
 322                 command_print(CMD_CTX,
 323                         "turnaround=%" PRIu32 ", prescale=%" PRIu32,
 324                         WCR_TO_TRN(wcr),
 325                         WCR_TO_PRESCALE(wcr));
 326         return ERROR_OK;
 327
 328         case 2:         /* TRN and prescale */
 329                 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], scale);
 330                 if (scale > 7) {
 331                         LOG_ERROR("prescale %d is too big", scale);
 332                         return ERROR_FAIL;
 333                 }
 334                 /* FALL THROUGH */
 335
 336         case 1:         /* TRN only */
 337                 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], trn);
 338                 if (trn < 1 || trn > 4) {
 339                         LOG_ERROR("turnaround %d is invalid", trn);
 340                         return ERROR_FAIL;
 341                 }
 342
 343                 wcr = ((trn - 1) << 8) | scale;
 344                 /* FIXME
 345                  * write WCR ...
 346                  * then, re-init adapter with new TRN
 347                  */
 348                 LOG_ERROR("can't yet modify WCR");
 349                 return ERROR_FAIL;
 350
 351         default:        /* too many arguments */
 352                 return ERROR_COMMAND_SYNTAX_ERROR;
 353         }
 354 }
 355
 356 static const struct command_registration swd_commands[] = {
 357         {
 358                 /*
 359                  * Set up SWD and JTAG targets identically, unless/until
 360                  * infrastructure improves ...  meanwhile, ignore all
 361                  * JTAG-specific stuff like IR length for SWD.
 362                  *
 363                  * REVISIT can we verify "just one SWD DAP" here/early?
 364                  */
 365                 .name = "newdap",
 366                 .jim_handler = jim_jtag_newtap,
 367                 .mode = COMMAND_CONFIG,
 368                 .help = "declare a new SWD DAP"
 369         },
 370         {
 371                 .name = "wcr",
 372                 .handler = handle_swd_wcr,
 373                 .mode = COMMAND_ANY,
 374                 .help = "display or update DAP's WCR register",
 375                 .usage = "turnaround (1..4), prescale (0..7)",
 376         },
 377
 378         /* REVISIT -- add a command for SWV trace on/off */
 379         COMMAND_REGISTRATION_DONE
 380 };
 381
 382 static const struct command_registration swd_handlers[] = {
 383         {
 384                 .name = "swd",
 385                 .mode = COMMAND_ANY,
 386                 .help = "SWD command group",
 387                 .chain = swd_commands,
 388         },
 389         COMMAND_REGISTRATION_DONE
 390 };
 391
 392 static int swd_select(struct command_context *ctx)
 393 {
 394         int retval;
 395
 396         retval = register_commands(ctx, NULL, swd_handlers);
 397
 398         if (retval != ERROR_OK)
 399                 return retval;
 400
 401         const struct swd_driver *swd = jtag_interface->swd;
 402
 403          /* be sure driver is in SWD mode; start
 404           * with hardware default TRN (1), it can be changed later
 405           */
 406         if (!swd || !swd->read_reg || !swd->write_reg || !swd->init) {
 407                 LOG_DEBUG("no SWD driver?");
 408                 return ERROR_FAIL;
 409         }
 410
 411         retval = swd->init(1);
 412         if (retval != ERROR_OK) {
 413                 LOG_DEBUG("can't init SWD driver");
 414                 return retval;
 415         }
 416
 417         /* force DAP into SWD mode (not JTAG) */
 418         /*retval = dap_to_swd(target);*/
 419
 420         if (ctx->current_target) {
 421                 /* force DAP into SWD mode (not JTAG) */
 422                 struct target *target = get_current_target(ctx);
 423                 retval = dap_to_swd(target);
 424         }
 425
 426         return retval;
 427 }
 428
 429 static int swd_init(struct command_context *ctx)
 430 {
 431         struct target *target = get_current_target(ctx);
 432         struct arm *arm = target_to_arm(target);
 433         struct adiv5_dap *dap = arm->dap;
 434         uint32_t idcode;
 435         int status;
 436
 437         /* Force the DAP's ops vector for SWD mode.
 438          * messy - is there a better way? */
 439         arm->dap->ops = &swd_dap_ops;
 440
 441         /* FIXME validate transport config ... is the
 442          * configured DAP present (check IDCODE)?
 443          * Is *only* one DAP configured?
 444          *
 445          * MUST READ IDCODE
 446          */
 447
 448  /* Note, debugport_init() does setup too */
 449
 450         uint8_t ack;
 451
 452         status = swd_queue_dp_read(dap, DP_IDCODE, &idcode);
 453
 454         if (status == ERROR_OK)
 455                 LOG_INFO("SWD IDCODE %#8.8" PRIx32, idcode);
 456
 457         /* force clear all sticky faults */
 458         swd_queue_ap_abort(dap, &ack);
 459
 460         /* this is a workaround to get polling working */
 461         jtag_add_reset(0, 0);
 462
 463         return status;
 464 }
 465
 466 static struct transport swd_transport = {
 467         .name = "swd",
 468         .select = swd_select,
 469         .init = swd_init,
 470 };
 471
 472 static void swd_constructor(void) __attribute__((constructor));
 473 static void swd_constructor(void)
 474 {
 475         transport_register(&swd_transport);
 476 }
 477
 478 /** Returns true if the current debug session
 479  * is using SWD as its transport.
 480  */
 481 bool transport_is_swd(void)
 482 {
 483         return get_current_transport() == &swd_transport;
 484 }