1 /***************************************************************************
3 * Copyright (C) 2010 by David Brownell
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 ***************************************************************************/
21 * Utilities to support ARM "Serial Wire Debug" (SWD), a low pin-count debug
22 * link protocol used in cases where JTAG is not wanted. This is coupled to
23 * recent versions of ARM's "CoreSight" debug framework. This specific code
24 * is a transport level interface, with "target/arm_adi_v5.[hc]" code
25 * understanding operation semantics, shared with the JTAG transport.
27 * Single-DAP support only.
29 * for details, see "ARM IHI 0031A"
30 * ARM Debug Interface v5 Architecture Specification
31 * especially section 5.3 for SWD protocol
33 * On many chips (most current Cortex-M3 parts) SWD is a run-time alternative
34 * to JTAG. Boards may support one or both. There are also SWD-only chips,
35 * (using SW-DP not SWJ-DP).
37 * Even boards that also support JTAG can benefit from SWD support, because
38 * usually there's no way to access the SWO trace view mechanism in JTAG mode.
39 * That is, trace access may require SWD support.
48 #include "arm_adi_v5.h"
49 #include <helper/time_support.h>
51 #include <transport/transport.h>
52 #include <jtag/interface.h>
56 /* YUK! - but this is currently a global.... */
57 extern struct jtag_interface
*jtag_interface
;
60 static void swd_finish_read(struct adiv5_dap
*dap
)
62 const struct swd_driver
*swd
= jtag_interface
->swd
;
63 if (dap
->last_read
!= NULL
) {
64 swd
->read_reg(swd_cmd(true, false, DP_RDBUFF
), dap
->last_read
, 0);
65 dap
->last_read
= NULL
;
69 static int swd_queue_dp_write(struct adiv5_dap
*dap
, unsigned reg
,
71 static int swd_queue_dp_read(struct adiv5_dap
*dap
, unsigned reg
,
74 static void swd_clear_sticky_errors(struct adiv5_dap
*dap
)
76 const struct swd_driver
*swd
= jtag_interface
->swd
;
79 swd
->write_reg(swd_cmd(false, false, DP_ABORT
),
80 STKCMPCLR
| STKERRCLR
| WDERRCLR
| ORUNERRCLR
, 0);
83 static int swd_run_inner(struct adiv5_dap
*dap
)
85 const struct swd_driver
*swd
= jtag_interface
->swd
;
90 if (retval
!= ERROR_OK
) {
92 dap
->do_reconnect
= true;
98 static int swd_connect(struct adiv5_dap
*dap
)
103 /* FIXME validate transport config ... is the
104 * configured DAP present (check IDCODE)?
105 * Is *only* one DAP configured?
110 /* Check if we should reset srst already when connecting, but not if reconnecting. */
111 if (!dap
->do_reconnect
) {
112 enum reset_types jtag_reset_config
= jtag_get_reset_config();
114 if (jtag_reset_config
& RESET_CNCT_UNDER_SRST
) {
115 if (jtag_reset_config
& RESET_SRST_NO_GATING
)
118 LOG_WARNING("\'srst_nogate\' reset_config option is required");
122 /* Note, debugport_init() does setup too */
123 jtag_interface
->swd
->switch_seq(JTAG_TO_SWD
);
125 /* Clear link state, including the SELECT cache. */
126 dap
->do_reconnect
= false;
127 dap
->select
= DP_SELECT_INVALID
;
129 swd_queue_dp_read(dap
, DP_DPIDR
, &dpidr
);
131 /* force clear all sticky faults */
132 swd_clear_sticky_errors(dap
);
134 status
= swd_run_inner(dap
);
136 if (status
== ERROR_OK
) {
137 LOG_INFO("SWD DPIDR %#8.8" PRIx32
, dpidr
);
138 dap
->do_reconnect
= false;
140 dap
->do_reconnect
= true;
145 static inline int check_sync(struct adiv5_dap
*dap
)
147 return do_sync
? swd_run_inner(dap
) : ERROR_OK
;
150 static int swd_check_reconnect(struct adiv5_dap
*dap
)
152 if (dap
->do_reconnect
)
153 return swd_connect(dap
);
158 static int swd_queue_ap_abort(struct adiv5_dap
*dap
, uint8_t *ack
)
160 const struct swd_driver
*swd
= jtag_interface
->swd
;
163 swd
->write_reg(swd_cmd(false, false, DP_ABORT
),
164 DAPABORT
| STKCMPCLR
| STKERRCLR
| WDERRCLR
| ORUNERRCLR
, 0);
165 return check_sync(dap
);
168 /** Select the DP register bank matching bits 7:4 of reg. */
169 static void swd_queue_dp_bankselect(struct adiv5_dap
*dap
, unsigned reg
)
171 /* Only register address 4 is banked. */
172 if ((reg
& 0xf) != 4)
175 uint32_t select_dp_bank
= (reg
& 0x000000F0) >> 4;
176 uint32_t sel
= select_dp_bank
177 | (dap
->select
& (DP_SELECT_APSEL
| DP_SELECT_APBANK
));
179 if (sel
== dap
->select
)
184 swd_queue_dp_write(dap
, DP_SELECT
, sel
);
187 static int swd_queue_dp_read(struct adiv5_dap
*dap
, unsigned reg
,
190 const struct swd_driver
*swd
= jtag_interface
->swd
;
193 int retval
= swd_check_reconnect(dap
);
194 if (retval
!= ERROR_OK
)
197 swd_queue_dp_bankselect(dap
, reg
);
198 swd
->read_reg(swd_cmd(true, false, reg
), data
, 0);
200 return check_sync(dap
);
203 static int swd_queue_dp_write(struct adiv5_dap
*dap
, unsigned reg
,
206 const struct swd_driver
*swd
= jtag_interface
->swd
;
209 int retval
= swd_check_reconnect(dap
);
210 if (retval
!= ERROR_OK
)
213 swd_finish_read(dap
);
214 swd_queue_dp_bankselect(dap
, reg
);
215 swd
->write_reg(swd_cmd(false, false, reg
), data
, 0);
217 return check_sync(dap
);
220 /** Select the AP register bank matching bits 7:4 of reg. */
221 static void swd_queue_ap_bankselect(struct adiv5_ap
*ap
, unsigned reg
)
223 struct adiv5_dap
*dap
= ap
->dap
;
224 uint32_t sel
= ((uint32_t)ap
->ap_num
<< 24)
226 | (dap
->select
& DP_SELECT_DPBANK
);
228 if (sel
== dap
->select
)
233 swd_queue_dp_write(dap
, DP_SELECT
, sel
);
236 static int swd_queue_ap_read(struct adiv5_ap
*ap
, unsigned reg
,
239 const struct swd_driver
*swd
= jtag_interface
->swd
;
242 struct adiv5_dap
*dap
= ap
->dap
;
244 int retval
= swd_check_reconnect(dap
);
245 if (retval
!= ERROR_OK
)
248 swd_queue_ap_bankselect(ap
, reg
);
249 swd
->read_reg(swd_cmd(true, true, reg
), dap
->last_read
, ap
->memaccess_tck
);
250 dap
->last_read
= data
;
252 return check_sync(dap
);
255 static int swd_queue_ap_write(struct adiv5_ap
*ap
, unsigned reg
,
258 const struct swd_driver
*swd
= jtag_interface
->swd
;
261 struct adiv5_dap
*dap
= ap
->dap
;
263 int retval
= swd_check_reconnect(dap
);
264 if (retval
!= ERROR_OK
)
267 swd_finish_read(dap
);
268 swd_queue_ap_bankselect(ap
, reg
);
269 swd
->write_reg(swd_cmd(false, true, reg
), data
, ap
->memaccess_tck
);
271 return check_sync(dap
);
274 /** Executes all queued DAP operations. */
275 static int swd_run(struct adiv5_dap
*dap
)
277 swd_finish_read(dap
);
278 return swd_run_inner(dap
);
281 const struct dap_ops swd_dap_ops
= {
282 .queue_dp_read
= swd_queue_dp_read
,
283 .queue_dp_write
= swd_queue_dp_write
,
284 .queue_ap_read
= swd_queue_ap_read
,
285 .queue_ap_write
= swd_queue_ap_write
,
286 .queue_ap_abort
= swd_queue_ap_abort
,
291 * This represents the bits which must be sent out on TMS/SWDIO to
292 * switch a DAP implemented using an SWJ-DP module into SWD mode.
293 * These bits are stored (and transmitted) LSB-first.
295 * See the DAP-Lite specification, section 2.2.5 for information
296 * about making the debug link select SWD or JTAG. (Similar info
297 * is in a few other ARM documents.)
299 static const uint8_t jtag2swd_bitseq
[] = {
300 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
301 * putting both JTAG and SWD logic into reset state.
303 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
304 /* Switching sequence enables SWD and disables JTAG
305 * NOTE: bits in the DP's IDCODE may expose the need for
306 * an old/obsolete/deprecated sequence (0xb6 0xed).
309 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
310 * putting both JTAG and SWD logic into reset state.
312 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
316 * Put the debug link into SWD mode, if the target supports it.
317 * The link's initial mode may be either JTAG (for example,
318 * with SWJ-DP after reset) or SWD.
320 * @param target Enters SWD mode (if possible).
322 * Note that targets using the JTAG-DP do not support SWD, and that
323 * some targets which could otherwise support it may have have been
324 * configured to disable SWD signaling
326 * @return ERROR_OK or else a fault code.
328 int dap_to_swd(struct target
*target
)
330 struct arm
*arm
= target_to_arm(target
);
334 LOG_ERROR("SWD mode is not available");
338 LOG_DEBUG("Enter SWD mode");
340 /* REVISIT it's ugly to need to make calls to a "jtag"
341 * subsystem if the link may not be in JTAG mode...
344 retval
= jtag_add_tms_seq(8 * sizeof(jtag2swd_bitseq
),
345 jtag2swd_bitseq
, TAP_INVALID
);
346 if (retval
== ERROR_OK
)
347 retval
= jtag_execute_queue();
349 /* set up the DAP's ops vector for SWD mode. */
350 arm
->dap
->ops
= &swd_dap_ops
;
355 static const struct command_registration swd_commands
[] = {
358 * Set up SWD and JTAG targets identically, unless/until
359 * infrastructure improves ... meanwhile, ignore all
360 * JTAG-specific stuff like IR length for SWD.
362 * REVISIT can we verify "just one SWD DAP" here/early?
365 .jim_handler
= jim_jtag_newtap
,
366 .mode
= COMMAND_CONFIG
,
367 .help
= "declare a new SWD DAP"
369 COMMAND_REGISTRATION_DONE
372 static const struct command_registration swd_handlers
[] = {
376 .help
= "SWD command group",
377 .chain
= swd_commands
,
379 COMMAND_REGISTRATION_DONE
382 static int swd_select(struct command_context
*ctx
)
386 retval
= register_commands(ctx
, NULL
, swd_handlers
);
388 if (retval
!= ERROR_OK
)
391 const struct swd_driver
*swd
= jtag_interface
->swd
;
393 /* be sure driver is in SWD mode; start
394 * with hardware default TRN (1), it can be changed later
396 if (!swd
|| !swd
->read_reg
|| !swd
->write_reg
|| !swd
->init
) {
397 LOG_DEBUG("no SWD driver?");
401 retval
= swd
->init();
402 if (retval
!= ERROR_OK
) {
403 LOG_DEBUG("can't init SWD driver");
407 /* force DAP into SWD mode (not JTAG) */
408 /*retval = dap_to_swd(target);*/
410 if (ctx
->current_target
) {
411 /* force DAP into SWD mode (not JTAG) */
412 struct target
*target
= get_current_target(ctx
);
413 retval
= dap_to_swd(target
);
419 static int swd_init(struct command_context
*ctx
)
421 struct target
*target
= get_current_target(ctx
);
422 struct arm
*arm
= target_to_arm(target
);
423 struct adiv5_dap
*dap
= arm
->dap
;
424 /* Force the DAP's ops vector for SWD mode.
425 * messy - is there a better way? */
426 arm
->dap
->ops
= &swd_dap_ops
;
427 /* First connect after init is not reconnecting. */
428 dap
->do_reconnect
= false;
430 int retval
= swd_connect(dap
);
431 if (retval
!= ERROR_OK
)
432 LOG_ERROR("SWD connect failed");
436 static struct transport swd_transport
= {
438 .select
= swd_select
,
442 static void swd_constructor(void) __attribute__((constructor
));
443 static void swd_constructor(void)
445 transport_register(&swd_transport
);
448 /** Returns true if the current debug session
449 * is using SWD as its transport.
451 bool transport_is_swd(void)
453 return get_current_transport() == &swd_transport
;
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)