target/adi_v5_swd: add support for SWD multidrop
[openocd.git] / src / target / adi_v5_swd.c
1 /***************************************************************************
2 *
3 * Copyright (C) 2010 by David Brownell
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 ***************************************************************************/
18
19 /**
20 * @file
21 * Utilities to support ARM "Serial Wire Debug" (SWD), a low pin-count debug
22 * link protocol used in cases where JTAG is not wanted. This is coupled to
23 * recent versions of ARM's "CoreSight" debug framework. This specific code
24 * is a transport level interface, with "target/arm_adi_v5.[hc]" code
25 * understanding operation semantics, shared with the JTAG transport.
26 *
27 * Single-DAP support only.
28 *
29 * for details, see "ARM IHI 0031A"
30 * ARM Debug Interface v5 Architecture Specification
31 * especially section 5.3 for SWD protocol
32 *
33 * On many chips (most current Cortex-M3 parts) SWD is a run-time alternative
34 * to JTAG. Boards may support one or both. There are also SWD-only chips,
35 * (using SW-DP not SWJ-DP).
36 *
37 * Even boards that also support JTAG can benefit from SWD support, because
38 * usually there's no way to access the SWO trace view mechanism in JTAG mode.
39 * That is, trace access may require SWD support.
40 *
41 */
42
43 #ifdef HAVE_CONFIG_H
44 #include "config.h"
45 #endif
46
47 #include "arm.h"
48 #include "arm_adi_v5.h"
49 #include <helper/time_support.h>
50
51 #include <transport/transport.h>
52 #include <jtag/interface.h>
53
54 #include <jtag/swd.h>
55
56 /* for debug, set do_sync to true to force synchronous transfers */
57 static bool do_sync;
58
59 static struct adiv5_dap *swd_multidrop_selected_dap;
60
61
62 static int swd_queue_dp_write_inner(struct adiv5_dap *dap, unsigned int reg,
63 uint32_t data);
64
65
66 static int swd_send_sequence(struct adiv5_dap *dap, enum swd_special_seq seq)
67 {
68 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
69 assert(swd);
70
71 return swd->switch_seq(seq);
72 }
73
74 static void swd_finish_read(struct adiv5_dap *dap)
75 {
76 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
77 if (dap->last_read) {
78 swd->read_reg(swd_cmd(true, false, DP_RDBUFF), dap->last_read, 0);
79 dap->last_read = NULL;
80 }
81 }
82
83 static void swd_clear_sticky_errors(struct adiv5_dap *dap)
84 {
85 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
86 assert(swd);
87
88 swd->write_reg(swd_cmd(false, false, DP_ABORT),
89 STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
90 }
91
92 static int swd_run_inner(struct adiv5_dap *dap)
93 {
94 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
95 int retval;
96
97 retval = swd->run();
98
99 if (retval != ERROR_OK) {
100 /* fault response */
101 dap->do_reconnect = true;
102 }
103
104 return retval;
105 }
106
107 static inline int check_sync(struct adiv5_dap *dap)
108 {
109 return do_sync ? swd_run_inner(dap) : ERROR_OK;
110 }
111
112 /** Select the DP register bank matching bits 7:4 of reg. */
113 static int swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned int reg)
114 {
115 /* Only register address 4 is banked. */
116 if ((reg & 0xf) != 4)
117 return ERROR_OK;
118
119 uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
120 uint32_t sel = select_dp_bank
121 | (dap->select & (DP_SELECT_APSEL | DP_SELECT_APBANK));
122
123 if (sel == dap->select)
124 return ERROR_OK;
125
126 dap->select = sel;
127
128 int retval = swd_queue_dp_write_inner(dap, DP_SELECT, sel);
129 if (retval != ERROR_OK)
130 dap->select = DP_SELECT_INVALID;
131
132 return retval;
133 }
134
135 static int swd_queue_dp_read_inner(struct adiv5_dap *dap, unsigned int reg,
136 uint32_t *data)
137 {
138 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
139 assert(swd);
140
141 int retval = swd_queue_dp_bankselect(dap, reg);
142 if (retval != ERROR_OK)
143 return retval;
144
145 swd->read_reg(swd_cmd(true, false, reg), data, 0);
146
147 return check_sync(dap);
148 }
149
150 static int swd_queue_dp_write_inner(struct adiv5_dap *dap, unsigned int reg,
151 uint32_t data)
152 {
153 int retval;
154 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
155 assert(swd);
156
157 swd_finish_read(dap);
158
159 if (reg == DP_SELECT) {
160 dap->select = data & (DP_SELECT_APSEL | DP_SELECT_APBANK | DP_SELECT_DPBANK);
161
162 swd->write_reg(swd_cmd(false, false, reg), data, 0);
163
164 retval = check_sync(dap);
165 if (retval != ERROR_OK)
166 dap->select = DP_SELECT_INVALID;
167
168 return retval;
169 }
170
171 retval = swd_queue_dp_bankselect(dap, reg);
172 if (retval != ERROR_OK)
173 return retval;
174
175 swd->write_reg(swd_cmd(false, false, reg), data, 0);
176
177 return check_sync(dap);
178 }
179
180
181 static int swd_multidrop_select_inner(struct adiv5_dap *dap, uint32_t *dpidr_ptr,
182 uint32_t *dlpidr_ptr, bool clear_sticky)
183 {
184 int retval;
185 uint32_t dpidr, dlpidr;
186
187 assert(dap_is_multidrop(dap));
188
189 swd_send_sequence(dap, LINE_RESET);
190
191 retval = swd_queue_dp_write_inner(dap, DP_TARGETSEL, dap->multidrop_targetsel);
192 if (retval != ERROR_OK)
193 return retval;
194
195 retval = swd_queue_dp_read_inner(dap, DP_DPIDR, &dpidr);
196 if (retval != ERROR_OK)
197 return retval;
198
199 if (clear_sticky) {
200 /* Clear all sticky errors (including ORUN) */
201 swd_clear_sticky_errors(dap);
202 } else {
203 /* Ideally just clear ORUN flag which is set by reset */
204 retval = swd_queue_dp_write_inner(dap, DP_ABORT, ORUNERRCLR);
205 if (retval != ERROR_OK)
206 return retval;
207 }
208
209 retval = swd_queue_dp_read_inner(dap, DP_DLPIDR, &dlpidr);
210 if (retval != ERROR_OK)
211 return retval;
212
213 retval = swd_run_inner(dap);
214 if (retval != ERROR_OK)
215 return retval;
216
217 if ((dpidr & DP_DPIDR_VERSION_MASK) < (2UL << DP_DPIDR_VERSION_SHIFT)) {
218 LOG_INFO("Read DPIDR 0x%08" PRIx32
219 " has version < 2. A non multidrop capable device connected?",
220 dpidr);
221 return ERROR_FAIL;
222 }
223
224 /* TODO: check TARGETID if DLIPDR is same for more than one DP */
225 uint32_t expected_dlpidr = DP_DLPIDR_PROTVSN |
226 (dap->multidrop_targetsel & DP_TARGETSEL_INSTANCEID_MASK);
227 if (dlpidr != expected_dlpidr) {
228 LOG_INFO("Read incorrect DLPIDR 0x%08" PRIx32
229 " (possibly CTRL/STAT value)",
230 dlpidr);
231 return ERROR_FAIL;
232 }
233
234 LOG_DEBUG_IO("Selected DP_TARGETSEL 0x%08" PRIx32, dap->multidrop_targetsel);
235 swd_multidrop_selected_dap = dap;
236
237 if (dpidr_ptr)
238 *dpidr_ptr = dpidr;
239
240 if (dlpidr_ptr)
241 *dlpidr_ptr = dlpidr;
242
243 return retval;
244 }
245
246 static int swd_multidrop_select(struct adiv5_dap *dap)
247 {
248 if (!dap_is_multidrop(dap))
249 return ERROR_OK;
250
251 if (swd_multidrop_selected_dap == dap)
252 return ERROR_OK;
253
254 int retval = ERROR_OK;
255 for (unsigned int retry = 0; ; retry++) {
256 bool clear_sticky = retry > 0;
257
258 retval = swd_multidrop_select_inner(dap, NULL, NULL, clear_sticky);
259 if (retval == ERROR_OK)
260 break;
261
262 swd_multidrop_selected_dap = NULL;
263 if (retry > 3) {
264 LOG_ERROR("Failed to select multidrop %s", adiv5_dap_name(dap));
265 return retval;
266 }
267
268 LOG_DEBUG("Failed to select multidrop %s, retrying...",
269 adiv5_dap_name(dap));
270 }
271
272 return retval;
273 }
274
275 static int swd_connect_multidrop(struct adiv5_dap *dap)
276 {
277 int retval;
278 uint32_t dpidr = 0xdeadbeef;
279 uint32_t dlpidr = 0xdeadbeef;
280 int64_t timeout = timeval_ms() + 500;
281
282 do {
283 swd_send_sequence(dap, JTAG_TO_DORMANT);
284 swd_send_sequence(dap, DORMANT_TO_SWD);
285
286 /* Clear link state, including the SELECT cache. */
287 dap->do_reconnect = false;
288 dap_invalidate_cache(dap);
289 swd_multidrop_selected_dap = NULL;
290
291 retval = swd_multidrop_select_inner(dap, &dpidr, &dlpidr, true);
292 if (retval == ERROR_OK)
293 break;
294
295 alive_sleep(1);
296
297 } while (timeval_ms() < timeout);
298
299 if (retval != ERROR_OK) {
300 swd_multidrop_selected_dap = NULL;
301 LOG_ERROR("Failed to connect multidrop %s", adiv5_dap_name(dap));
302 return retval;
303 }
304
305 LOG_INFO("SWD DPIDR 0x%08" PRIx32 ", DLPIDR 0x%08" PRIx32,
306 dpidr, dlpidr);
307
308 return retval;
309 }
310
311 static int swd_connect_single(struct adiv5_dap *dap)
312 {
313 int retval;
314 uint32_t dpidr = 0xdeadbeef;
315 int64_t timeout = timeval_ms() + 500;
316
317 do {
318 swd_send_sequence(dap, JTAG_TO_SWD);
319
320 /* Clear link state, including the SELECT cache. */
321 dap->do_reconnect = false;
322 dap_invalidate_cache(dap);
323
324 retval = swd_queue_dp_read_inner(dap, DP_DPIDR, &dpidr);
325 if (retval == ERROR_OK) {
326 retval = swd_run_inner(dap);
327 if (retval == ERROR_OK)
328 break;
329 }
330
331 alive_sleep(1);
332
333 } while (timeval_ms() < timeout);
334
335 if (retval != ERROR_OK) {
336 LOG_ERROR("Error connecting DP: cannot read IDR");
337 return retval;
338 }
339
340 LOG_INFO("SWD DPIDR 0x%08" PRIx32, dpidr);
341
342 do {
343 dap->do_reconnect = false;
344
345 /* force clear all sticky faults */
346 swd_clear_sticky_errors(dap);
347
348 retval = swd_run_inner(dap);
349 if (retval != ERROR_WAIT)
350 break;
351
352 alive_sleep(10);
353
354 } while (timeval_ms() < timeout);
355
356 return retval;
357 }
358
359 static int swd_connect(struct adiv5_dap *dap)
360 {
361 int status;
362
363 /* FIXME validate transport config ... is the
364 * configured DAP present (check IDCODE)?
365 */
366
367 /* Check if we should reset srst already when connecting, but not if reconnecting. */
368 if (!dap->do_reconnect) {
369 enum reset_types jtag_reset_config = jtag_get_reset_config();
370
371 if (jtag_reset_config & RESET_CNCT_UNDER_SRST) {
372 if (jtag_reset_config & RESET_SRST_NO_GATING)
373 adapter_assert_reset();
374 else
375 LOG_WARNING("\'srst_nogate\' reset_config option is required");
376 }
377 }
378
379 if (dap_is_multidrop(dap))
380 status = swd_connect_multidrop(dap);
381 else
382 status = swd_connect_single(dap);
383
384 /* IHI 0031E B4.3.2:
385 * "A WAIT response must not be issued to the ...
386 * ... writes to the ABORT register"
387 * swd_clear_sticky_errors() writes to the ABORT register only.
388 *
389 * Unfortunately at least Microchip SAMD51/E53/E54 returns WAIT
390 * in a corner case. Just try if ABORT resolves the problem.
391 */
392 if (status == ERROR_WAIT) {
393 LOG_WARNING("Connecting DP: stalled AP operation, issuing ABORT");
394
395 dap->do_reconnect = false;
396
397 status = swd_queue_dp_write_inner(dap, DP_ABORT,
398 DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR);
399
400 if (status == ERROR_OK)
401 status = swd_run_inner(dap);
402 }
403
404 if (status == ERROR_OK)
405 status = dap_dp_init(dap);
406
407 return status;
408 }
409
410 static int swd_check_reconnect(struct adiv5_dap *dap)
411 {
412 if (dap->do_reconnect)
413 return swd_connect(dap);
414
415 return ERROR_OK;
416 }
417
418 static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
419 {
420 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
421 assert(swd);
422
423 /* TODO: Send DAPABORT in swd_multidrop_select_inner()
424 * in the case the multidrop dap is not selected?
425 * swd_queue_ap_abort() is not currently used anyway...
426 */
427 int retval = swd_multidrop_select(dap);
428 if (retval != ERROR_OK)
429 return retval;
430
431 swd->write_reg(swd_cmd(false, false, DP_ABORT),
432 DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
433 return check_sync(dap);
434 }
435
436 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
437 uint32_t *data)
438 {
439 int retval = swd_check_reconnect(dap);
440 if (retval != ERROR_OK)
441 return retval;
442
443 retval = swd_multidrop_select(dap);
444 if (retval != ERROR_OK)
445 return retval;
446
447 return swd_queue_dp_read_inner(dap, reg, data);
448 }
449
450 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
451 uint32_t data)
452 {
453 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
454 assert(swd);
455
456 int retval = swd_check_reconnect(dap);
457 if (retval != ERROR_OK)
458 return retval;
459
460 retval = swd_multidrop_select(dap);
461 if (retval != ERROR_OK)
462 return retval;
463
464 return swd_queue_dp_write_inner(dap, reg, data);
465 }
466
467 /** Select the AP register bank matching bits 7:4 of reg. */
468 static int swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
469 {
470 struct adiv5_dap *dap = ap->dap;
471 uint32_t sel = ((uint32_t)ap->ap_num << 24)
472 | (reg & 0x000000F0)
473 | (dap->select & DP_SELECT_DPBANK);
474
475 if (sel == dap->select)
476 return ERROR_OK;
477
478 dap->select = sel;
479
480 int retval = swd_queue_dp_write_inner(dap, DP_SELECT, sel);
481 if (retval != ERROR_OK)
482 dap->select = DP_SELECT_INVALID;
483
484 return retval;
485 }
486
487 static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
488 uint32_t *data)
489 {
490 struct adiv5_dap *dap = ap->dap;
491 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
492 assert(swd);
493
494 int retval = swd_check_reconnect(dap);
495 if (retval != ERROR_OK)
496 return retval;
497
498 retval = swd_multidrop_select(dap);
499 if (retval != ERROR_OK)
500 return retval;
501
502 retval = swd_queue_ap_bankselect(ap, reg);
503 if (retval != ERROR_OK)
504 return retval;
505
506 swd->read_reg(swd_cmd(true, true, reg), dap->last_read, ap->memaccess_tck);
507 dap->last_read = data;
508
509 return check_sync(dap);
510 }
511
512 static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg,
513 uint32_t data)
514 {
515 struct adiv5_dap *dap = ap->dap;
516 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
517 assert(swd);
518
519 int retval = swd_check_reconnect(dap);
520 if (retval != ERROR_OK)
521 return retval;
522
523 retval = swd_multidrop_select(dap);
524 if (retval != ERROR_OK)
525 return retval;
526
527 swd_finish_read(dap);
528
529 retval = swd_queue_ap_bankselect(ap, reg);
530 if (retval != ERROR_OK)
531 return retval;
532
533 swd->write_reg(swd_cmd(false, true, reg), data, ap->memaccess_tck);
534
535 return check_sync(dap);
536 }
537
538 /** Executes all queued DAP operations. */
539 static int swd_run(struct adiv5_dap *dap)
540 {
541 int retval = swd_multidrop_select(dap);
542 if (retval != ERROR_OK)
543 return retval;
544
545 swd_finish_read(dap);
546
547 return swd_run_inner(dap);
548 }
549
550 /** Put the SWJ-DP back to JTAG mode */
551 static void swd_quit(struct adiv5_dap *dap)
552 {
553 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
554 static bool done;
555
556 /* There is no difference if the sequence is sent at the last
557 * or the first swd_quit() call, send it just once */
558 if (done)
559 return;
560
561 done = true;
562 if (dap_is_multidrop(dap)) {
563 swd->switch_seq(SWD_TO_DORMANT);
564 /* Revisit!
565 * Leaving DPs in dormant state was tested and offers some safety
566 * against DPs mismatch in case of unintentional use of non-multidrop SWD.
567 * To put SWJ-DPs to power-on state issue
568 * swd->switch_seq(DORMANT_TO_JTAG);
569 */
570 } else {
571 swd->switch_seq(SWD_TO_JTAG);
572 }
573
574 /* flush the queue to shift out the sequence before exit */
575 swd->run();
576 }
577
578 const struct dap_ops swd_dap_ops = {
579 .connect = swd_connect,
580 .send_sequence = swd_send_sequence,
581 .queue_dp_read = swd_queue_dp_read,
582 .queue_dp_write = swd_queue_dp_write,
583 .queue_ap_read = swd_queue_ap_read,
584 .queue_ap_write = swd_queue_ap_write,
585 .queue_ap_abort = swd_queue_ap_abort,
586 .run = swd_run,
587 .quit = swd_quit,
588 };
589
590 static const struct command_registration swd_commands[] = {
591 {
592 /*
593 * Set up SWD and JTAG targets identically, unless/until
594 * infrastructure improves ... meanwhile, ignore all
595 * JTAG-specific stuff like IR length for SWD.
596 *
597 * REVISIT can we verify "just one SWD DAP" here/early?
598 */
599 .name = "newdap",
600 .jim_handler = jim_jtag_newtap,
601 .mode = COMMAND_CONFIG,
602 .help = "declare a new SWD DAP"
603 },
604 COMMAND_REGISTRATION_DONE
605 };
606
607 static const struct command_registration swd_handlers[] = {
608 {
609 .name = "swd",
610 .mode = COMMAND_ANY,
611 .help = "SWD command group",
612 .chain = swd_commands,
613 .usage = "",
614 },
615 COMMAND_REGISTRATION_DONE
616 };
617
618 static int swd_select(struct command_context *ctx)
619 {
620 /* FIXME: only place where global 'adapter_driver' is still needed */
621 extern struct adapter_driver *adapter_driver;
622 const struct swd_driver *swd = adapter_driver->swd_ops;
623 int retval;
624
625 retval = register_commands(ctx, NULL, swd_handlers);
626 if (retval != ERROR_OK)
627 return retval;
628
629 /* be sure driver is in SWD mode; start
630 * with hardware default TRN (1), it can be changed later
631 */
632 if (!swd || !swd->read_reg || !swd->write_reg || !swd->init) {
633 LOG_DEBUG("no SWD driver?");
634 return ERROR_FAIL;
635 }
636
637 retval = swd->init();
638 if (retval != ERROR_OK) {
639 LOG_DEBUG("can't init SWD driver");
640 return retval;
641 }
642
643 return retval;
644 }
645
646 static int swd_init(struct command_context *ctx)
647 {
648 /* nothing done here, SWD is initialized
649 * together with the DAP */
650 return ERROR_OK;
651 }
652
653 static struct transport swd_transport = {
654 .name = "swd",
655 .select = swd_select,
656 .init = swd_init,
657 };
658
659 static void swd_constructor(void) __attribute__((constructor));
660 static void swd_constructor(void)
661 {
662 transport_register(&swd_transport);
663 }
664
665 /** Returns true if the current debug session
666 * is using SWD as its transport.
667 */
668 bool transport_is_swd(void)
669 {
670 return get_current_transport() == &swd_transport;
671 }

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